tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_HAL_DMA_H
  40 #define __STM32F4xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx_hal_def.h"
  48
  49 /** @addtogroup STM32F4xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup DMA
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /**
  60   * @brief  DMA Configuration Structure definition
  61   */
  62 typedef struct
  63 {
  64   uint32_t Channel;              /*!< Specifies the channel used for the specified stream.
  65                                       This parameter can be a value of @ref DMA_Channel_selection                    */
  66
  67   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
  68                                       from memory to memory or from peripheral to memory.
  69                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
  70
  71   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
  72                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
  73
  74   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
  75                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
  76
  77   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
  78                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
  79
  80   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
  81                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
  82
  83   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
  84                                       This parameter can be a value of @ref DMA_mode
  85                                       @note The circular buffer mode cannot be used if the memory-to-memory
  86                                             data transfer is configured on the selected Stream                        */
  87
  88   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
  89                                       This parameter can be a value of @ref DMA_Priority_level                       */
  90
  91   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
  92                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
  93                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
  94                                             memory-to-memory data transfer is configured on the selected stream       */
  95
  96   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
  97                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
  98
  99   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
 100                                       It specifies the amount of data to be transferred in a single non interruptable
 101                                       transaction.
 102                                       This parameter can be a value of @ref DMA_Memory_burst
 103                                       @note The burst mode is possible only if the address Increment mode is enabled. */
 104
 105   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
 106                                       It specifies the amount of data to be transferred in a single non interruptable
 107                                       transaction.
 108                                       This parameter can be a value of @ref DMA_Peripheral_burst
 109                                       @note The burst mode is possible only if the address Increment mode is enabled. */
 110 }DMA_InitTypeDef;
 111
 112 /**
 113   * @brief  HAL DMA State structures definition
 114   */
 115 typedef enum
 116 {
 117   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
 118   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
 119   HAL_DMA_STATE_READY_MEM0        = 0x11,  /*!< DMA Mem0 process success            */
 120   HAL_DMA_STATE_READY_MEM1        = 0x21,  /*!< DMA Mem1 process success            */
 121   HAL_DMA_STATE_READY_HALF_MEM0   = 0x31,  /*!< DMA Mem0 Half process success       */
 122   HAL_DMA_STATE_READY_HALF_MEM1   = 0x41,  /*!< DMA Mem1 Half process success       */
 123   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
 124   HAL_DMA_STATE_BUSY_MEM0         = 0x12,  /*!< DMA Mem0 process is ongoing         */
 125   HAL_DMA_STATE_BUSY_MEM1         = 0x22,  /*!< DMA Mem1 process is ongoing         */
 126   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
 127   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
 128 }HAL_DMA_StateTypeDef;
 129
 130 /**
 131   * @brief  HAL DMA Error Code structure definition
 132   */
 133 typedef enum
 134 {
 135   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
 136   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
 137 }HAL_DMA_LevelCompleteTypeDef;
 138
 139 /**
 140   * @brief  DMA handle Structure definition
 141   */
 142 typedef struct __DMA_HandleTypeDef
 143 {
 144   DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
 145
 146   DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */
 147
 148   HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */
 149
 150   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 151
 152   void                       *Parent;                                                      /*!< Parent object state                    */
 153
 154   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 155
 156   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 157
 158   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
 159
 160   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 161
 162   __IO uint32_t              ErrorCode;                                                    /*!< DMA Error code                         */
 163 }DMA_HandleTypeDef;
 164
 165 /* Exported constants --------------------------------------------------------*/
 166
 167 /** @defgroup DMA_Exported_Constants
 168   * @{
 169   */
 170
 171 /** @defgroup DMA_Error_Code
 172   * @{
 173   */
 174 #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
 175 #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
 176 #define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002)    /*!< FIFO error           */
 177 #define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004)    /*!< Direct Mode error    */
 178 #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
 179 /**
 180   * @}
 181   */
 182
 183 /** @defgroup DMA_Channel_selection
 184   * @{
 185   */
 186 #define DMA_CHANNEL_0        ((uint32_t)0x00000000)  /*!< DMA Channel 0 */
 187 #define DMA_CHANNEL_1        ((uint32_t)0x02000000)  /*!< DMA Channel 1 */
 188 #define DMA_CHANNEL_2        ((uint32_t)0x04000000)  /*!< DMA Channel 2 */
 189 #define DMA_CHANNEL_3        ((uint32_t)0x06000000)  /*!< DMA Channel 3 */
 190 #define DMA_CHANNEL_4        ((uint32_t)0x08000000)  /*!< DMA Channel 4 */
 191 #define DMA_CHANNEL_5        ((uint32_t)0x0A000000)  /*!< DMA Channel 5 */
 192 #define DMA_CHANNEL_6        ((uint32_t)0x0C000000)  /*!< DMA Channel 6 */
 193 #define DMA_CHANNEL_7        ((uint32_t)0x0E000000)  /*!< DMA Channel 7 */
 194
 195 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
 196                                  ((CHANNEL) == DMA_CHANNEL_1) || \
 197                                  ((CHANNEL) == DMA_CHANNEL_2) || \
 198                                  ((CHANNEL) == DMA_CHANNEL_3) || \
 199                                  ((CHANNEL) == DMA_CHANNEL_4) || \
 200                                  ((CHANNEL) == DMA_CHANNEL_5) || \
 201                                  ((CHANNEL) == DMA_CHANNEL_6) || \
 202                                  ((CHANNEL) == DMA_CHANNEL_7))
 203 /**
 204   * @}
 205   */
 206
 207 /** @defgroup DMA_Data_transfer_direction
 208   * @{
 209   */
 210 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
 211 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
 212 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
 213
 214 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 215                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 216                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 217 /**
 218   * @}
 219   */
 220
 221 /** @defgroup DMA_Data_buffer_size
 222   * @{
 223   */
 224 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 225 /**
 226   * @}
 227   */
 228
 229 /** @defgroup DMA_Peripheral_incremented_mode
 230   * @{
 231   */
 232 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
 233 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode disable */
 234
 235 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 236                                             ((STATE) == DMA_PINC_DISABLE))
 237 /**
 238   * @}
 239   */
 240
 241 /** @defgroup DMA_Memory_incremented_mode
 242   * @{
 243   */
 244 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
 245 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode disable */
 246
 247 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 248                                         ((STATE) == DMA_MINC_DISABLE))
 249 /**
 250   * @}
 251   */
 252
 253 /** @defgroup DMA_Peripheral_data_size
 254   * @{
 255   */
 256 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
 257 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
 258 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
 259
 260 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 261                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 262                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 263 /**
 264   * @}
 265   */
 266
 267
 268 /** @defgroup DMA_Memory_data_size
 269   * @{
 270   */
 271 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
 272 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
 273 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
 274
 275 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 276                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 277                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 278 /**
 279   * @}
 280   */
 281
 282 /** @defgroup DMA_mode
 283   * @{
 284   */
 285 #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
 286 #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
 287 #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
 288
 289 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 290                            ((MODE) == DMA_CIRCULAR) || \
 291                            ((MODE) == DMA_PFCTRL))
 292 /**
 293   * @}
 294   */
 295
 296 /** @defgroup DMA_Priority_level
 297   * @{
 298   */
 299 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level: Low       */
 300 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
 301 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
 302 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
 303
 304 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 305                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 306                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 307                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 308 /**
 309   * @}
 310   */
 311
 312 /** @defgroup DMA_FIFO_direct_mode
 313   * @{
 314   */
 315 #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000)       /*!< FIFO mode disable */
 316 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
 317
 318 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
 319                                        ((STATE) == DMA_FIFOMODE_ENABLE))
 320 /**
 321   * @}
 322   */
 323
 324 /** @defgroup DMA_FIFO_threshold_level
 325   * @{
 326   */
 327 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000)       /*!< FIFO threshold 1 quart full configuration  */
 328 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
 329 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
 330 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
 331
 332 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
 333                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
 334                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
 335                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
 336 /**
 337   * @}
 338   */
 339
 340 /** @defgroup DMA_Memory_burst
 341   * @{
 342   */
 343 #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000)
 344 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
 345 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
 346 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
 347
 348 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
 349                                     ((BURST) == DMA_MBURST_INC4)   || \
 350                                     ((BURST) == DMA_MBURST_INC8)   || \
 351                                     ((BURST) == DMA_MBURST_INC16))
 352 /**
 353   * @}
 354   */
 355
 356 /** @defgroup DMA_Peripheral_burst
 357   * @{
 358   */
 359 #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000)
 360 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
 361 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
 362 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
 363
 364 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
 365                                         ((BURST) == DMA_PBURST_INC4)   || \
 366                                         ((BURST) == DMA_PBURST_INC8)   || \
 367                                         ((BURST) == DMA_PBURST_INC16))
 368 /**
 369   * @}
 370   */
 371
 372 /** @defgroup DMA_interrupt_enable_definitions
 373   * @{
 374   */
 375 #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
 376 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
 377 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
 378 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
 379 #define DMA_IT_FE                         ((uint32_t)0x00000080)
 380 /**
 381   * @}
 382   */
 383
 384 /** @defgroup DMA_flag_definitions
 385   * @{
 386   */
 387 #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001)
 388 #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004)
 389 #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008)
 390 #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010)
 391 #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020)
 392 #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040)
 393 #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100)
 394 #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200)
 395 #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400)
 396 #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800)
 397 #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000)
 398 #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000)
 399 #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000)
 400 #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000)
 401 #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000)
 402 #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000)
 403 #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000)
 404 #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000)
 405 #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000)
 406 #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000)
 407 /**
 408   * @}
 409   */
 410
 411 /**
 412   * @}
 413   */
 414
 415 /* Exported macro ------------------------------------------------------------*/
 416
 417 /** @brief Reset DMA handle state
 418   * @param  __HANDLE__: specifies the DMA handle.
 419   * @retval None
 420   */
 421 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 422
 423 /**
 424   * @brief  Return the current DMA Stream FIFO filled level.
 425   * @param  __HANDLE__: DMA handle
 426   * @retval The FIFO filling state.
 427   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
 428   *                                              and not empty.
 429   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
 430   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
 431   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
 432   *           - DMA_FIFOStatus_Empty: when FIFO is empty
 433   *           - DMA_FIFOStatus_Full: when FIFO is full
 434   */
 435 #define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
 436
 437 /**
 438   * @brief  Enable the specified DMA Stream.
 439   * @param  __HANDLE__: DMA handle
 440   * @retval None
 441   */
 442 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
 443
 444 /**
 445   * @brief  Disable the specified DMA Stream.
 446   * @param  __HANDLE__: DMA handle
 447   * @retval None
 448   */
 449 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
 450
 451 /* Interrupt & Flag management */
 452
 453 /**
 454   * @brief  Return the current DMA Stream transfer complete flag.
 455   * @param  __HANDLE__: DMA handle
 456   * @retval The specified transfer complete flag index.
 457   */
 458 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 459 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 460  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 461  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 462  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 463  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 464  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 465  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 466  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 467  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 468  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 469  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
 471    DMA_FLAG_TCIF3_7)
 472
 473 /**
 474   * @brief  Return the current DMA Stream half transfer complete flag.
 475   * @param  __HANDLE__: DMA handle
 476   * @retval The specified half transfer complete flag index.
 477   */
 478 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 479 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 481  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 482  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 483  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 484  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 485  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 486  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 487  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 488  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 489  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
 491    DMA_FLAG_HTIF3_7)
 492
 493 /**
 494   * @brief  Return the current DMA Stream transfer error flag.
 495   * @param  __HANDLE__: DMA handle
 496   * @retval The specified transfer error flag index.
 497   */
 498 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 499 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 501  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 502  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 503  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 504  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 505  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 506  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 507  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 508  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 509  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 510  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
 511    DMA_FLAG_TEIF3_7)
 512
 513 /**
 514   * @brief  Return the current DMA Stream FIFO error flag.
 515   * @param  __HANDLE__: DMA handle
 516   * @retval The specified FIFO error flag index.
 517   */
 518 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
 519 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 520  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 521  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 522  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 523  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 524  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 525  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 526  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 527  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 528  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 529  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 530  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
 531    DMA_FLAG_FEIF3_7)
 532
 533 /**
 534   * @brief  Return the current DMA Stream direct mode error flag.
 535   * @param  __HANDLE__: DMA handle
 536   * @retval The specified direct mode error flag index.
 537   */
 538 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
 539 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 540  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 541  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 542  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 543  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 544  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 545  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 546  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 547  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 548  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 549  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 550  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
 551    DMA_FLAG_DMEIF3_7)
 552
 553 /**
 554   * @brief  Get the DMA Stream pending flags.
 555   * @param  __HANDLE__: DMA handle
 556   * @param  __FLAG__: Get the specified flag.
 557   *          This parameter can be any combination of the following values:
 558   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 559   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 560   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 561   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 562   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 563   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 564   * @retval The state of FLAG (SET or RESET).
 565   */
 566 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
 567 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
 568  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
 569  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
 570
 571 /**
 572   * @brief  Clear the DMA Stream pending flags.
 573   * @param  __HANDLE__: DMA handle
 574   * @param  __FLAG__: specifies the flag to clear.
 575   *          This parameter can be any combination of the following values:
 576   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
 577   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
 578   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
 579   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
 580   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
 581   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
 582   * @retval None
 583   */
 584 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
 585 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
 586  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
 587  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
 588
 589 /**
 590   * @brief  Enable the specified DMA Stream interrupts.
 591   * @param  __HANDLE__: DMA handle
 592   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 593   *        This parameter can be any combination of the following values:
 594   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
 595   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
 596   *           @arg DMA_IT_TE: Transfer error interrupt mask.
 597   *           @arg DMA_IT_FE: FIFO error interrupt mask.
 598   *           @arg DMA_IT_DME: Direct mode error interrupt.
 599   * @retval None
 600   */
 601 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
 602 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
 603
 604 /**
 605   * @brief  Disable the specified DMA Stream interrupts.
 606   * @param  __HANDLE__: DMA handle
 607   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 608   *         This parameter can be any combination of the following values:
 609   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 610   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 611   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 612   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 613   *            @arg DMA_IT_DME: Direct mode error interrupt.
 614   * @retval None
 615   */
 616 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 617 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
 618
 619 /**
 620   * @brief  Check whether the specified DMA Stream interrupt has occurred or not.
 621   * @param  __HANDLE__: DMA handle
 622   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 623   *         This parameter can be one of the following values:
 624   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
 625   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
 626   *            @arg DMA_IT_TE: Transfer error interrupt mask.
 627   *            @arg DMA_IT_FE: FIFO error interrupt mask.
 628   *            @arg DMA_IT_DME: Direct mode error interrupt.
 629   * @retval The state of DMA_IT.
 630   */
 631 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
 632                                                         ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
 633                                                         ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
 634
 635 /**
 636   * @brief  Writes the number of data units to be transferred on the DMA Stream.
 637   * @param  __HANDLE__: DMA handle
 638   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
 639   *          Number of data items depends only on the Peripheral data format.
 640   *
 641   * @note   If Peripheral data format is Bytes: number of data units is equal
 642   *         to total number of bytes to be transferred.
 643   *
 644   * @note   If Peripheral data format is Half-Word: number of data units is
 645   *         equal to total number of bytes to be transferred / 2.
 646   *
 647   * @note   If Peripheral data format is Word: number of data units is equal
 648   *         to total  number of bytes to be transferred / 4.
 649   *
 650   * @retval The number of remaining data units in the current DMAy Streamx transfer.
 651   */
 652 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
 653
 654 /**
 655   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
 656   * @param  __HANDLE__: DMA handle
 657   *
 658   * @retval The number of remaining data units in the current DMA Stream transfer.
 659   */
 660 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
 661
 662
 663 /* Include DMA HAL Extension module */
 664 #include "stm32f4xx_hal_dma_ex.h"
 665
 666 /* Exported functions --------------------------------------------------------*/
 667
 668 /* Initialization and de-initialization functions *****************************/
 669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 671
 672 /* IO operation functions *****************************************************/
 673 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 674 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 675 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 676 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 677 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 678
 679 /* Peripheral State and Error functions ***************************************/
 680 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 681 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 682
 683 /**
 684   * @}
 685   */
 686
 687 /**
 688   * @}
 689   */
 690
 691 #ifdef __cplusplus
 692 }
 693 #endif
 694
 695 #endif /* __STM32F4xx_HAL_DMA_H */
 696
 697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/