tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_ll_fmc.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   FMC Low Layer HAL module driver.
   8   *
   9   *          This file provides firmware functions to manage the following
  10   *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
  11   *           + Initialization/de-initialization functions
  12   *           + Peripheral Control functions
  13   *           + Peripheral State functions
  14   *
  15   @verbatim
  16   ==============================================================================
  17                         ##### FMC peripheral features #####
  18   ==============================================================================
  19   [..] The Flexible memory controller (FMC) includes three memory controllers:
  20        (+) The NOR/PSRAM memory controller
  21        (+) The NAND/PC Card memory controller
  22        (+) The Synchronous DRAM (SDRAM) controller
  23
  24   [..] The FMC functional block makes the interface with synchronous and asynchronous static
  25        memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
  26        (+) to translate AHB transactions into the appropriate external device protocol
  27        (+) to meet the access time requirements of the external memory devices
  28
  29   [..] All external memories share the addresses, data and control signals with the controller.
  30        Each external device is accessed by means of a unique Chip Select. The FMC performs
  31        only one access at a time to an external device.
  32        The main features of the FMC controller are the following:
  33         (+) Interface with static-memory mapped devices including:
  34            (++) Static random access memory (SRAM)
  35            (++) Read-only memory (ROM)
  36            (++) NOR Flash memory/OneNAND Flash memory
  37            (++) PSRAM (4 memory banks)
  38            (++) 16-bit PC Card compatible devices
  39            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  40                 data
  41         (+) Interface with synchronous DRAM (SDRAM) memories
  42         (+) Independent Chip Select control for each memory bank
  43         (+) Independent configuration for each memory bank
  44
  45   @endverbatim
  46   ******************************************************************************
  47   * @attention
  48   *
  49   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  50   *
  51   * Redistribution and use in source and binary forms, with or without modification,
  52   * are permitted provided that the following conditions are met:
  53   *   1. Redistributions of source code must retain the above copyright notice,
  54   *      this list of conditions and the following disclaimer.
  55   *   2. Redistributions in binary form must reproduce the above copyright notice,
  56   *      this list of conditions and the following disclaimer in the documentation
  57   *      and/or other materials provided with the distribution.
  58   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  59   *      may be used to endorse or promote products derived from this software
  60   *      without specific prior written permission.
  61   *
  62   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  63   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  64   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  65   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  66   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  67   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  68   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  69   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  70   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  71   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  72   *
  73   ******************************************************************************
  74   */
  75
  76 /* Includes ------------------------------------------------------------------*/
  77 #include "stm32f4xx_hal.h"
  78
  79 /** @addtogroup STM32F4xx_HAL_Driver
  80   * @{
  81   */
  82
  83 /** @defgroup FMC
  84   * @brief FMC driver modules
  85   * @{
  86   */
  87
  88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
  89
  90 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
  91
  92 /* Private typedef -----------------------------------------------------------*/
  93 /* Private define ------------------------------------------------------------*/
  94 /* Private macro -------------------------------------------------------------*/
  95 /* Private variables ---------------------------------------------------------*/
  96 /* Private function prototypes -----------------------------------------------*/
  97 /* Private functions ---------------------------------------------------------*/
  98
  99 /** @defgroup FMC_Private_Functions
 100   * @{
 101   */
 102
 103 /** @defgroup FMC_NORSRAM Controller functions
 104   * @brief    NORSRAM Controller functions
 105   *
 106   @verbatim
 107   ==============================================================================
 108                    ##### How to use NORSRAM device driver #####
 109   ==============================================================================
 110
 111   [..]
 112     This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
 113     to run the NORSRAM external devices.
 114
 115     (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
 116     (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
 117     (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
 118     (+) FMC NORSRAM bank extended timing configuration using the function
 119         FMC_NORSRAM_Extended_Timing_Init()
 120     (+) FMC NORSRAM bank enable/disable write operation using the functions
 121         FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
 122
 123
 124 @endverbatim
 125   * @{
 126   */
 127
 128 /** @defgroup HAL_FMC_NORSRAM_Group1 Initialization/de-initialization functions
 129   * @brief    Initialization and Configuration functions
 130   *
 131   @verbatim
 132   ==============================================================================
 133               ##### Initialization and de_initialization functions #####
 134   ==============================================================================
 135   [..]
 136     This section provides functions allowing to:
 137     (+) Initialize and configure the FMC NORSRAM interface
 138     (+) De-initialize the FMC NORSRAM interface
 139     (+) Configure the FMC clock and associated GPIOs
 140
 141 @endverbatim
 142   * @{
 143   */
 144
 145 /**
 146   * @brief  Initialize the FMC_NORSRAM device according to the specified
 147   *         control parameters in the FMC_NORSRAM_InitTypeDef
 148   * @param  Device: Pointer to NORSRAM device instance
 149   * @param  Init: Pointer to NORSRAM Initialization structure
 150   * @retval HAL status
 151   */
 152 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
 153 {
 154   uint32_t tmpr = 0;
 155
 156   /* Check the parameters */
 157   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 158   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
 159   assert_param(IS_FMC_MUX(Init->DataAddressMux));
 160   assert_param(IS_FMC_MEMORY(Init->MemoryType));
 161   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 162   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
 163   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 164   assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
 165   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 166   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
 167   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
 168   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
 169   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
 170   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
 171   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
 172
 173   /* Set NORSRAM device control parameters */
 174   tmpr = (uint32_t)(Init->DataAddressMux       |\
 175                     Init->MemoryType           |\
 176                     Init->MemoryDataWidth      |\
 177                     Init->BurstAccessMode      |\
 178                     Init->WaitSignalPolarity   |\
 179                     Init->WrapMode             |\
 180                     Init->WaitSignalActive     |\
 181                     Init->WriteOperation       |\
 182                     Init->WaitSignal           |\
 183                     Init->ExtendedMode         |\
 184                     Init->AsynchronousWait     |\
 185                     Init->WriteBurst           |\
 186                     Init->ContinuousClock
 187                     );
 188
 189   if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
 190   {
 191     tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
 192   }
 193
 194   Device->BTCR[Init->NSBank] = tmpr;
 195
 196   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
 197   if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
 198   {
 199     Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
 200     Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode  |\
 201                                                   Init->ContinuousClock);
 202   }
 203
 204   return HAL_OK;
 205 }
 206
 207
 208 /**
 209   * @brief  DeInitialize the FMC_NORSRAM peripheral
 210   * @param  Device: Pointer to NORSRAM device instance
 211   * @param  ExDevice: Pointer to NORSRAM extended mode device instance
 212   * @param  Bank: NORSRAM bank number
 213   * @retval HAL status
 214   */
 215 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 216 {
 217   /* Check the parameters */
 218   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 219   assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 220   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 221
 222   /* Disable the FMC_NORSRAM device */
 223   __FMC_NORSRAM_DISABLE(Device, Bank);
 224
 225   /* De-initialize the FMC_NORSRAM device */
 226   /* FMC_NORSRAM_BANK1 */
 227   if(Bank == FMC_NORSRAM_BANK1)
 228   {
 229     Device->BTCR[Bank] = 0x000030DB;
 230   }
 231   /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
 232   else
 233   {
 234     Device->BTCR[Bank] = 0x000030D2;
 235   }
 236
 237   Device->BTCR[Bank + 1] = 0x0FFFFFFF;
 238   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
 239
 240   return HAL_OK;
 241 }
 242
 243
 244 /**
 245   * @brief  Initialize the FMC_NORSRAM Timing according to the specified
 246   *         parameters in the FMC_NORSRAM_TimingTypeDef
 247   * @param  Device: Pointer to NORSRAM device instance
 248   * @param  Timing: Pointer to NORSRAM Timing structure
 249   * @param  Bank: NORSRAM bank number
 250   * @retval HAL status
 251   */
 252 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 253 {
 254   uint32_t tmpr = 0;
 255
 256   /* Check the parameters */
 257   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 258   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 259   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 260   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 261   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 262   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
 263   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
 264   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 265   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 266
 267   /* Set FMC_NORSRAM device timing parameters */
 268   tmpr = (uint32_t)(Timing->AddressSetupTime                  |\
 269                    ((Timing->AddressHoldTime) << 4)          |\
 270                    ((Timing->DataSetupTime) << 8)            |\
 271                    ((Timing->BusTurnAroundDuration) << 16)   |\
 272                    (((Timing->CLKDivision)-1) << 20)         |\
 273                    (((Timing->DataLatency)-2) << 24)         |\
 274                     (Timing->AccessMode)
 275                     );
 276
 277   Device->BTCR[Bank + 1] = tmpr;
 278
 279   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
 280   if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
 281   {
 282     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
 283     tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
 284     Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
 285   }
 286
 287   return HAL_OK;
 288 }
 289
 290 /**
 291   * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
 292   *         parameters in the FMC_NORSRAM_TimingTypeDef
 293   * @param  Device: Pointer to NORSRAM device instance
 294   * @param  Timing: Pointer to NORSRAM Timing structure
 295   * @param  Bank: NORSRAM bank number
 296   * @retval HAL status
 297   */
 298 HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 299 {
 300   /* Check the parameters */
 301   assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
 302
 303   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 304   if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
 305   {
 306     /* Check the parameters */
 307     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
 308     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 309     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 310     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 311     assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 312     assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
 313     assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
 314     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 315     assert_param(IS_FMC_NORSRAM_BANK(Bank));
 316
 317     Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime                 |\
 318                                    ((Timing->AddressHoldTime) << 4)          |\
 319                                    ((Timing->DataSetupTime) << 8)            |\
 320                                    ((Timing->BusTurnAroundDuration) << 16)   |\
 321                                    (((Timing->CLKDivision)-1) << 20)         |\
 322                                    (((Timing->DataLatency)-2) << 24)         |\
 323                                    (Timing->AccessMode));
 324   }
 325   else
 326   {
 327     Device->BWTR[Bank] = 0x0FFFFFFF;
 328   }
 329
 330   return HAL_OK;
 331 }
 332
 333
 334 /**
 335   * @}
 336   */
 337
 338
 339 /** @defgroup HAL_FMC_NORSRAM_Group3 Control functions
 340  *  @brief   management functions
 341  *
 342 @verbatim
 343   ==============================================================================
 344                       ##### FMC_NORSRAM Control functions #####
 345   ==============================================================================
 346   [..]
 347     This subsection provides a set of functions allowing to control dynamically
 348     the FMC NORSRAM interface.
 349
 350 @endverbatim
 351   * @{
 352   */
 353
 354 /**
 355   * @brief  Enables dynamically FMC_NORSRAM write operation.
 356   * @param  Device: Pointer to NORSRAM device instance
 357   * @param  Bank: NORSRAM bank number
 358   * @retval HAL status
 359   */
 360 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 361 {
 362   /* Check the parameters */
 363   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 364   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 365
 366   /* Enable write operation */
 367   Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
 368
 369   return HAL_OK;
 370 }
 371
 372 /**
 373   * @brief  Disables dynamically FMC_NORSRAM write operation.
 374   * @param  Device: Pointer to NORSRAM device instance
 375   * @param  Bank: NORSRAM bank number
 376   * @retval HAL status
 377   */
 378 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 379 {
 380   /* Check the parameters */
 381   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 382   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 383
 384   /* Disable write operation */
 385   Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
 386
 387   return HAL_OK;
 388 }
 389
 390 /**
 391   * @}
 392   */
 393
 394 /**
 395   * @}
 396   */
 397
 398 /** @defgroup FMC_PCCARD Controller functions
 399   * @brief    PCCARD Controller functions
 400   *
 401   @verbatim
 402   ==============================================================================
 403                     ##### How to use NAND device driver #####
 404   ==============================================================================
 405   [..]
 406     This driver contains a set of APIs to interface with the FMC NAND banks in order
 407     to run the NAND external devices.
 408
 409     (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
 410     (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
 411     (+) FMC NAND bank common space timing configuration using the function
 412         FMC_NAND_CommonSpace_Timing_Init()
 413     (+) FMC NAND bank attribute space timing configuration using the function
 414         FMC_NAND_AttributeSpace_Timing_Init()
 415     (+) FMC NAND bank enable/disable ECC correction feature using the functions
 416         FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
 417     (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
 418
 419 @endverbatim
 420   * @{
 421   */
 422
 423 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
 424  *  @brief    Initialization and Configuration functions
 425  *
 426 @verbatim
 427   ==============================================================================
 428               ##### Initialization and de_initialization functions #####
 429   ==============================================================================
 430   [..]
 431     This section provides functions allowing to:
 432     (+) Initialize and configure the FMC NAND interface
 433     (+) De-initialize the FMC NAND interface
 434     (+) Configure the FMC clock and associated GPIOs
 435
 436 @endverbatim
 437   * @{
 438   */
 439
 440 /**
 441   * @brief  Initializes the FMC_NAND device according to the specified
 442   *         control parameters in the FMC_NAND_HandleTypeDef
 443   * @param  Device: Pointer to NAND device instance
 444   * @param  Init: Pointer to NAND Initialization structure
 445   * @retval HAL status
 446   */
 447 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
 448 {
 449   uint32_t tmppcr  = 0;
 450
 451   /* Check the parameters */
 452   assert_param(IS_FMC_NAND_DEVICE(Device));
 453   assert_param(IS_FMC_NAND_BANK(Init->NandBank));
 454   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
 455   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 456   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
 457   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
 458   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
 459   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
 460
 461   /* Set NAND device control parameters */
 462   tmppcr = (uint32_t)(Init->Waitfeature                |\
 463                       FMC_PCR_MEMORY_TYPE_NAND         |\
 464                       Init->MemoryDataWidth            |\
 465                       Init->EccComputation             |\
 466                       Init->ECCPageSize                |\
 467                       ((Init->TCLRSetupTime) << 9)     |\
 468                       ((Init->TARSetupTime) << 13)
 469                       );
 470
 471   if(Init->NandBank == FMC_NAND_BANK2)
 472   {
 473     /* NAND bank 2 registers configuration */
 474     Device->PCR2  = tmppcr;
 475   }
 476   else
 477   {
 478     /* NAND bank 3 registers configuration */
 479     Device->PCR3  = tmppcr;
 480   }
 481
 482   return HAL_OK;
 483
 484 }
 485
 486 /**
 487   * @brief  Initializes the FMC_NAND Common space Timing according to the specified
 488   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 489   * @param  Device: Pointer to NAND device instance
 490   * @param  Timing: Pointer to NAND timing structure
 491   * @param  Bank: NAND bank number
 492   * @retval HAL status
 493   */
 494 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 495 {
 496   uint32_t tmppmem = 0;
 497
 498   /* Check the parameters */
 499   assert_param(IS_FMC_NAND_DEVICE(Device));
 500   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 501   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 502   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 503   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 504   assert_param(IS_FMC_NAND_BANK(Bank));
 505
 506   /* Set FMC_NAND device timing parameters */
 507   tmppmem = (uint32_t)(Timing->SetupTime                  |\
 508                        ((Timing->WaitSetupTime) << 8)     |\
 509                        ((Timing->HoldSetupTime) << 16)    |\
 510                        ((Timing->HiZSetupTime) << 24)
 511                        );
 512
 513   if(Bank == FMC_NAND_BANK2)
 514   {
 515     /* NAND bank 2 registers configuration */
 516     Device->PMEM2 = tmppmem;
 517   }
 518   else
 519   {
 520     /* NAND bank 3 registers configuration */
 521     Device->PMEM3 = tmppmem;
 522   }
 523
 524   return HAL_OK;
 525 }
 526
 527 /**
 528   * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
 529   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 530   * @param  Device: Pointer to NAND device instance
 531   * @param  Timing: Pointer to NAND timing structure
 532   * @param  Bank: NAND bank number
 533   * @retval HAL status
 534   */
 535 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 536 {
 537   uint32_t tmppatt = 0;
 538
 539   /* Check the parameters */
 540   assert_param(IS_FMC_NAND_DEVICE(Device));
 541   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 542   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 543   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 544   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 545   assert_param(IS_FMC_NAND_BANK(Bank));
 546
 547   /* Set FMC_NAND device timing parameters */
 548   tmppatt = (uint32_t)(Timing->SetupTime                  |\
 549                        ((Timing->WaitSetupTime) << 8)     |\
 550                        ((Timing->HoldSetupTime) << 16)    |\
 551                        ((Timing->HiZSetupTime) << 24)
 552                        );
 553
 554   if(Bank == FMC_NAND_BANK2)
 555   {
 556     /* NAND bank 2 registers configuration */
 557     Device->PATT2 = tmppatt;
 558   }
 559   else
 560   {
 561     /* NAND bank 3 registers configuration */
 562     Device->PATT3 = tmppatt;
 563   }
 564
 565   return HAL_OK;
 566 }
 567
 568
 569 /**
 570   * @brief  DeInitializes the FMC_NAND device
 571   * @param  Device: Pointer to NAND device instance
 572   * @param  Bank: NAND bank number
 573   * @retval HAL status
 574   */
 575 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
 576 {
 577   /* Check the parameters */
 578   assert_param(IS_FMC_NAND_DEVICE(Device));
 579   assert_param(IS_FMC_NAND_BANK(Bank));
 580
 581   /* Disable the NAND Bank */
 582   __FMC_NAND_DISABLE(Device, Bank);
 583
 584   /* De-initialize the NAND Bank */
 585   if(Bank == FMC_NAND_BANK2)
 586   {
 587     /* Set the FMC_NAND_BANK2 registers to their reset values */
 588     Device->PCR2  = 0x00000018;
 589     Device->SR2   = 0x00000040;
 590     Device->PMEM2 = 0xFCFCFCFC;
 591     Device->PATT2 = 0xFCFCFCFC;
 592   }
 593   /* FMC_Bank3_NAND */
 594   else
 595   {
 596     /* Set the FMC_NAND_BANK3 registers to their reset values */
 597     Device->PCR3  = 0x00000018;
 598     Device->SR3   = 0x00000040;
 599     Device->PMEM3 = 0xFCFCFCFC;
 600     Device->PATT3 = 0xFCFCFCFC;
 601   }
 602
 603   return HAL_OK;
 604 }
 605
 606 /**
 607   * @}
 608   */
 609
 610
 611 /** @defgroup HAL_FMC_NAND_Group3 Control functions
 612  *  @brief   management functions
 613  *
 614 @verbatim
 615   ==============================================================================
 616                        ##### FMC_NAND Control functions #####
 617   ==============================================================================
 618   [..]
 619     This subsection provides a set of functions allowing to control dynamically
 620     the FMC NAND interface.
 621
 622 @endverbatim
 623   * @{
 624   */
 625
 626
 627 /**
 628   * @brief  Enables dynamically FMC_NAND ECC feature.
 629   * @param  Device: Pointer to NAND device instance
 630   * @param  Bank: NAND bank number
 631   * @retval HAL status
 632   */
 633 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 634 {
 635   /* Check the parameters */
 636   assert_param(IS_FMC_NAND_DEVICE(Device));
 637   assert_param(IS_FMC_NAND_BANK(Bank));
 638
 639   /* Enable ECC feature */
 640   if(Bank == FMC_NAND_BANK2)
 641   {
 642     Device->PCR2 |= FMC_PCR2_ECCEN;
 643   }
 644   else
 645   {
 646     Device->PCR3 |= FMC_PCR3_ECCEN;
 647   }
 648
 649   return HAL_OK;
 650 }
 651
 652
 653 /**
 654   * @brief  Disables dynamically FMC_NAND ECC feature.
 655   * @param  Device: Pointer to NAND device instance
 656   * @param  Bank: NAND bank number
 657   * @retval HAL status
 658   */
 659 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 660 {
 661   /* Check the parameters */
 662   assert_param(IS_FMC_NAND_DEVICE(Device));
 663   assert_param(IS_FMC_NAND_BANK(Bank));
 664
 665   /* Disable ECC feature */
 666   if(Bank == FMC_NAND_BANK2)
 667   {
 668     Device->PCR2 &= ~FMC_PCR2_ECCEN;
 669   }
 670   else
 671   {
 672     Device->PCR3 &= ~FMC_PCR3_ECCEN;
 673   }
 674
 675   return HAL_OK;
 676 }
 677
 678 /**
 679   * @brief  Disables dynamically FMC_NAND ECC feature.
 680   * @param  Device: Pointer to NAND device instance
 681   * @param  ECCval: Pointer to ECC value
 682   * @param  Bank: NAND bank number
 683   * @param  Timeout: Timeout wait value
 684   * @retval HAL status
 685   */
 686 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 687 {
 688   uint32_t tickstart = 0;
 689
 690   /* Check the parameters */
 691   assert_param(IS_FMC_NAND_DEVICE(Device));
 692   assert_param(IS_FMC_NAND_BANK(Bank));
 693
 694   /* Get tick */
 695   tickstart = HAL_GetTick();
 696
 697   /* Wait untill FIFO is empty */
 698   while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
 699   {
 700     /* Check for the Timeout */
 701     if(Timeout != HAL_MAX_DELAY)
 702     {
 703       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
 704       {
 705         return HAL_TIMEOUT;
 706       }
 707     }
 708   }
 709
 710   if(Bank == FMC_NAND_BANK2)
 711   {
 712     /* Get the ECCR2 register value */
 713     *ECCval = (uint32_t)Device->ECCR2;
 714   }
 715   else
 716   {
 717     /* Get the ECCR3 register value */
 718     *ECCval = (uint32_t)Device->ECCR3;
 719   }
 720
 721   return HAL_OK;
 722 }
 723
 724 /**
 725   * @}
 726   */
 727
 728 /**
 729   * @}
 730   */
 731
 732 /** @defgroup FMC_PCCARD Controller functions
 733   * @brief    PCCARD Controller functions
 734   *
 735   @verbatim
 736   ==============================================================================
 737                     ##### How to use PCCARD device driver #####
 738   ==============================================================================
 739   [..]
 740     This driver contains a set of APIs to interface with the FMC PCCARD bank in order
 741     to run the PCCARD/compact flash external devices.
 742
 743     (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
 744     (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
 745     (+) FMC PCCARD bank common space timing configuration using the function
 746         FMC_PCCARD_CommonSpace_Timing_Init()
 747     (+) FMC PCCARD bank attribute space timing configuration using the function
 748         FMC_PCCARD_AttributeSpace_Timing_Init()
 749     (+) FMC PCCARD bank IO space timing configuration using the function
 750         FMC_PCCARD_IOSpace_Timing_Init()
 751
 752
 753 @endverbatim
 754   * @{
 755   */
 756
 757 /** @defgroup HAL_FMC_PCCARD_Group1 Initialization/de-initialization functions
 758  *  @brief    Initialization and Configuration functions
 759  *
 760 @verbatim
 761   ==============================================================================
 762               ##### Initialization and de_initialization functions #####
 763   ==============================================================================
 764   [..]
 765     This section provides functions allowing to:
 766     (+) Initialize and configure the FMC PCCARD interface
 767     (+) De-initialize the FMC PCCARD interface
 768     (+) Configure the FMC clock and associated GPIOs
 769
 770 @endverbatim
 771   * @{
 772   */
 773
 774 /**
 775   * @brief  Initializes the FMC_PCCARD device according to the specified
 776   *         control parameters in the FMC_PCCARD_HandleTypeDef
 777   * @param  Device: Pointer to PCCARD device instance
 778   * @param  Init: Pointer to PCCARD Initialization structure
 779   * @retval HAL status
 780   */
 781 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
 782 {
 783   /* Check the parameters */
 784   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 785   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
 786   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
 787   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
 788
 789   /* Set FMC_PCCARD device control parameters */
 790   Device->PCR4 = (uint32_t)(Init->Waitfeature               |\
 791                             FMC_NAND_PCC_MEM_BUS_WIDTH_16   |\
 792                             (Init->TCLRSetupTime << 9)      |\
 793                             (Init->TARSetupTime << 13));
 794
 795   return HAL_OK;
 796
 797 }
 798
 799 /**
 800   * @brief  Initializes the FMC_PCCARD Common space Timing according to the specified
 801   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 802   * @param  Device: Pointer to PCCARD device instance
 803   * @param  Timing: Pointer to PCCARD timing structure
 804   * @retval HAL status
 805   */
 806 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
 807 {
 808   /* Check the parameters */
 809   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 810   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 811   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 812   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 813   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 814
 815   /* Set PCCARD timing parameters */
 816   Device->PMEM4 = (uint32_t)((Timing->SetupTime                 |\
 817                              ((Timing->WaitSetupTime) << 8)     |\
 818                               (Timing->HoldSetupTime) << 16)    |\
 819                               ((Timing->HiZSetupTime) << 24)
 820                              );
 821
 822   return HAL_OK;
 823 }
 824
 825 /**
 826   * @brief  Initializes the FMC_PCCARD Attribute space Timing according to the specified
 827   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 828   * @param  Device: Pointer to PCCARD device instance
 829   * @param  Timing: Pointer to PCCARD timing structure
 830   * @retval HAL status
 831   */
 832 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
 833 {
 834   /* Check the parameters */
 835   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 836   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 837   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 838   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 839   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 840
 841   /* Set PCCARD timing parameters */
 842   Device->PATT4 = (uint32_t)((Timing->SetupTime                 |\
 843                              ((Timing->WaitSetupTime) << 8)     |\
 844                               (Timing->HoldSetupTime) << 16)    |\
 845                               ((Timing->HiZSetupTime) << 24)
 846                              );
 847
 848   return HAL_OK;
 849 }
 850
 851 /**
 852   * @brief  Initializes the FMC_PCCARD IO space Timing according to the specified
 853   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 854   * @param  Device: Pointer to PCCARD device instance
 855   * @param  Timing: Pointer to PCCARD timing structure
 856   * @retval HAL status
 857   */
 858 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
 859 {
 860   /* Check the parameters */
 861   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 862   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 863   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 864   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 865   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 866
 867   /* Set FMC_PCCARD device timing parameters */
 868   Device->PIO4 = (uint32_t)((Timing->SetupTime                  |\
 869                              ((Timing->WaitSetupTime) << 8)     |\
 870                               (Timing->HoldSetupTime) << 16)    |\
 871                               ((Timing->HiZSetupTime) << 24)
 872                              );
 873
 874   return HAL_OK;
 875 }
 876
 877 /**
 878   * @brief  DeInitializes the FMC_PCCARD device
 879   * @param  Device: Pointer to PCCARD device instance
 880   * @retval HAL status
 881   */
 882 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
 883 {
 884   /* Check the parameters */
 885   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 886
 887   /* Disable the FMC_PCCARD device */
 888   __FMC_PCCARD_DISABLE(Device);
 889
 890   /* De-initialize the FMC_PCCARD device */
 891   Device->PCR4    = 0x00000018;
 892   Device->SR4     = 0x00000000;
 893   Device->PMEM4   = 0xFCFCFCFC;
 894   Device->PATT4   = 0xFCFCFCFC;
 895   Device->PIO4    = 0xFCFCFCFC;
 896
 897   return HAL_OK;
 898 }
 899
 900 /**
 901   * @}
 902   */
 903
 904
 905 /** @defgroup FMC_SDRAM Controller functions
 906   * @brief    SDRAM Controller functions
 907   *
 908   @verbatim
 909   ==============================================================================
 910                      ##### How to use SDRAM device driver #####
 911   ==============================================================================
 912   [..]
 913     This driver contains a set of APIs to interface with the FMC SDRAM banks in order
 914     to run the SDRAM external devices.
 915
 916     (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
 917     (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
 918     (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
 919     (+) FMC SDRAM bank enable/disable write operation using the functions
 920         FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
 921     (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
 922
 923 @endverbatim
 924   * @{
 925   */
 926
 927 /** @defgroup HAL_FMC_SDRAM_Group1 Initialization/de-initialization functions
 928  *  @brief    Initialization and Configuration functions
 929  *
 930 @verbatim
 931   ==============================================================================
 932               ##### Initialization and de_initialization functions #####
 933   ==============================================================================
 934   [..]
 935     This section provides functions allowing to:
 936     (+) Initialize and configure the FMC SDRAM interface
 937     (+) De-initialize the FMC SDRAM interface
 938     (+) Configure the FMC clock and associated GPIOs
 939
 940 @endverbatim
 941   * @{
 942   */
 943
 944 /**
 945   * @brief  Initializes the FMC_SDRAM device according to the specified
 946   *         control parameters in the FMC_SDRAM_InitTypeDef
 947   * @param  Device: Pointer to SDRAM device instance
 948   * @param  Init: Pointer to SDRAM Initialization structure
 949   * @retval HAL status
 950   */
 951 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
 952 {
 953   uint32_t tmpr1 = 0;
 954   uint32_t tmpr2 = 0;
 955
 956   /* Check the parameters */
 957   assert_param(IS_FMC_SDRAM_DEVICE(Device));
 958   assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
 959   assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
 960   assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
 961   assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
 962   assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
 963   assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
 964   assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
 965   assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
 966   assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
 967   assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
 968
 969   /* Set SDRAM bank configuration parameters */
 970   if (Init->SDBank != FMC_SDRAM_BANK2)
 971   {
 972     Device->SDCR[FMC_SDRAM_BANK1] = (uint32_t)(Init->ColumnBitsNumber   |\
 973                                                Init->RowBitsNumber      |\
 974                                                Init->MemoryDataWidth    |\
 975                                                Init->InternalBankNumber |\
 976                                                Init->CASLatency         |\
 977                                                Init->WriteProtection    |\
 978                                                Init->SDClockPeriod      |\
 979                                                Init->ReadBurst          |\
 980                                                Init->ReadPipeDelay
 981                                                );
 982   }
 983   else /* FMC_Bank2_SDRAM */
 984   {
 985     tmpr1 = (uint32_t)(Init->SDClockPeriod      |\
 986                        Init->ReadBurst          |\
 987                        Init->ReadPipeDelay
 988                        );
 989
 990     tmpr2 = (uint32_t)(Init->ColumnBitsNumber   |\
 991                        Init->RowBitsNumber      |\
 992                        Init->MemoryDataWidth    |\
 993                        Init->InternalBankNumber |\
 994                        Init->CASLatency         |\
 995                        Init->WriteProtection
 996                        );
 997
 998     Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
 999     Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
1000   }
1001
1002   return HAL_OK;
1003 }
1004
1005 /**
1006   * @brief  Initializes the FMC_SDRAM device timing according to the specified
1007   *         parameters in the FMC_SDRAM_TimingTypeDef
1008   * @param  Device: Pointer to SDRAM device instance
1009   * @param  Timing: Pointer to SDRAM Timing structure
1010   * @param  Bank: SDRAM bank number
1011   * @retval HAL status
1012   */
1013 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
1014 {
1015   uint32_t tmpr1 = 0;
1016   uint32_t tmpr2 = 0;
1017
1018   /* Check the parameters */
1019   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1020   assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
1021   assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
1022   assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
1023   assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
1024   assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
1025   assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
1026   assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
1027   assert_param(IS_FMC_SDRAM_BANK(Bank));
1028
1029   /* Set SDRAM device timing parameters */
1030   if (Bank != FMC_SDRAM_BANK2)
1031   {
1032     Device->SDTR[FMC_SDRAM_BANK1] = (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
1033                                                (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
1034                                                (((Timing->SelfRefreshTime)-1) << 8)      |\
1035                                                (((Timing->RowCycleDelay)-1) << 12)       |\
1036                                                (((Timing->WriteRecoveryTime)-1) <<16)    |\
1037                                                (((Timing->RPDelay)-1) << 20)             |\
1038                                                (((Timing->RCDDelay)-1) << 24)
1039                                                );
1040   }
1041   else /* FMC_Bank2_SDRAM */
1042   {
1043
1044     tmpr1 = (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
1045                        (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
1046                        (((Timing->SelfRefreshTime)-1) << 8)      |\
1047                        (((Timing->WriteRecoveryTime)-1) <<16)    |\
1048                        (((Timing->RCDDelay)-1) << 24)
1049                        );
1050
1051     tmpr2  = (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\
1052                         (((Timing->RPDelay)-1) << 20)
1053                         );
1054
1055     Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
1056     Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
1057   }
1058
1059   return HAL_OK;
1060 }
1061
1062 /**
1063   * @brief  DeInitializes the FMC_SDRAM peripheral
1064   * @param  Device: Pointer to SDRAM device instance
1065   * @retval HAL status
1066   */
1067 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1068 {
1069   /* Check the parameters */
1070   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1071   assert_param(IS_FMC_SDRAM_BANK(Bank));
1072
1073   /* De-initialize the SDRAM device */
1074   Device->SDCR[Bank] = 0x000002D0;
1075   Device->SDTR[Bank] = 0x0FFFFFFF;
1076   Device->SDCMR      = 0x00000000;
1077   Device->SDRTR      = 0x00000000;
1078   Device->SDSR       = 0x00000000;
1079
1080   return HAL_OK;
1081 }
1082
1083 /**
1084   * @}
1085   */
1086
1087
1088 /** @defgroup HAL_FMC_SDRAM_Group3 Control functions
1089  *  @brief   management functions
1090  *
1091 @verbatim
1092   ==============================================================================
1093                       ##### FMC_SDRAM Control functions #####
1094   ==============================================================================
1095   [..]
1096     This subsection provides a set of functions allowing to control dynamically
1097     the FMC SDRAM interface.
1098
1099 @endverbatim
1100   * @{
1101   */
1102
1103 /**
1104   * @brief  Enables dynamically FMC_SDRAM write protection.
1105   * @param  Device: Pointer to SDRAM device instance
1106   * @param  Bank: SDRAM bank number
1107   * @retval HAL status
1108   */
1109 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1110 {
1111   /* Check the parameters */
1112   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1113   assert_param(IS_FMC_SDRAM_BANK(Bank));
1114
1115   /* Enable write protection */
1116   Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1117
1118   return HAL_OK;
1119 }
1120
1121 /**
1122   * @brief  Disables dynamically FMC_SDRAM write protection.
1123   * @param  hsdram: FMC_SDRAM handle
1124   * @retval HAL status
1125   */
1126 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1127 {
1128   /* Check the parameters */
1129   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1130   assert_param(IS_FMC_SDRAM_BANK(Bank));
1131
1132   /* Disable write protection */
1133   Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1134
1135   return HAL_OK;
1136 }
1137
1138 /**
1139   * @brief  Send Command to the FMC SDRAM bank
1140   * @param  Device: Pointer to SDRAM device instance
1141   * @param  Command: Pointer to SDRAM command structure
1142   * @param  Timing: Pointer to SDRAM Timing structure
1143   * @param  Timeout: Timeout wait value
1144   * @retval HAL state
1145   */
1146 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1147 {
1148   __IO uint32_t tmpr = 0;
1149   uint32_t tickstart = 0;
1150
1151   /* Check the parameters */
1152   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1153   assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1154   assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1155   assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1156   assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1157
1158   /* Set command register */
1159   tmpr = (uint32_t)((Command->CommandMode)                  |\
1160                     (Command->CommandTarget)                |\
1161                     (((Command->AutoRefreshNumber)-1) << 5) |\
1162                     ((Command->ModeRegisterDefinition) << 9)
1163                     );
1164
1165   Device->SDCMR = tmpr;
1166
1167   /* Get tick */
1168   tickstart = HAL_GetTick();
1169
1170   /* wait until command is send */
1171   while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
1172   {
1173     /* Check for the Timeout */
1174     if(Timeout != HAL_MAX_DELAY)
1175     {
1176       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1177       {
1178         return HAL_TIMEOUT;
1179       }
1180     }
1181
1182     return HAL_ERROR;
1183   }
1184
1185   return HAL_OK;
1186 }
1187
1188 /**
1189   * @brief  Program the SDRAM Memory Refresh rate.
1190   * @param  Device: Pointer to SDRAM device instance
1191   * @param  RefreshRate: The SDRAM refresh rate value.
1192   * @retval HAL state
1193   */
1194 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1195 {
1196   /* Check the parameters */
1197   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1198   assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1199
1200   /* Set the refresh rate in command register */
1201   Device->SDRTR |= (RefreshRate<<1);
1202
1203   return HAL_OK;
1204 }
1205
1206 /**
1207   * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
1208   * @param  Device: Pointer to SDRAM device instance
1209   * @param  AutoRefreshNumber: Specifies the auto Refresh number.
1210   * @retval None
1211   */
1212 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1213 {
1214   /* Check the parameters */
1215   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1216   assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1217
1218   /* Set the Auto-refresh number in command register */
1219   Device->SDCMR |= (AutoRefreshNumber << 5);
1220
1221   return HAL_OK;
1222 }
1223
1224 /**
1225   * @brief  Returns the indicated FMC SDRAM bank mode status.
1226   * @param  Device: Pointer to SDRAM device instance
1227   * @param  Bank: Defines the FMC SDRAM bank. This parameter can be
1228   *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1229   * @retval The FMC SDRAM bank mode status, could be on of the following values:
1230   *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1231   *         FMC_SDRAM_POWER_DOWN_MODE.
1232   */
1233 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1234 {
1235   uint32_t tmpreg = 0;
1236
1237   /* Check the parameters */
1238   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1239   assert_param(IS_FMC_SDRAM_BANK(Bank));
1240
1241   /* Get the corresponding bank mode */
1242   if(Bank == FMC_SDRAM_BANK1)
1243   {
1244     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1245   }
1246   else
1247   {
1248     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
1249   }
1250
1251   /* Return the mode status */
1252   return tmpreg;
1253 }
1254
1255 /**
1256   * @}
1257   */
1258
1259 /**
1260   * @}
1261   */
1262
1263 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1264
1265 #endif /* HAL_FMC_MODULE_ENABLED */
1266
1267 /**
1268   * @}
1269   */
1270
1271 /**
1272   * @}
1273   */
1274
1275 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/