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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F4 / stm32f4xx_ll_fmc.h
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 19-June-2014
7 * @brief Header file of FMC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FMC_H
40 #define __STM32F4xx_LL_FMC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
47
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f4xx_hal_def.h"
50
51 /** @addtogroup STM32F4xx_HAL_Driver
52 * @{
53 */
54
55 /** @addtogroup FMC
56 * @{
57 */
58
59 /* Exported typedef ----------------------------------------------------------*/
60 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
61 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
62 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
63 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
64 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
65
66 #define FMC_NORSRAM_DEVICE FMC_Bank1
67 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
68 #define FMC_NAND_DEVICE FMC_Bank2_3
69 #define FMC_PCCARD_DEVICE FMC_Bank4
70 #define FMC_SDRAM_DEVICE FMC_Bank5_6
71
72 /**
73 * @brief FMC_NORSRAM Configuration Structure definition
74 */
75 typedef struct
76 {
77 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
78 This parameter can be a value of @ref FMC_NORSRAM_Bank */
79
80 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
81 multiplexed on the data bus or not.
82 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
83
84 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
85 the corresponding memory device.
86 This parameter can be a value of @ref FMC_Memory_Type */
87
88 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
89 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
90
91 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
92 valid only with synchronous burst Flash memories.
93 This parameter can be a value of @ref FMC_Burst_Access_Mode */
94
95 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
96 the Flash memory in burst mode.
97 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
98
99 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
100 memory, valid only when accessing Flash memories in burst mode.
101 This parameter can be a value of @ref FMC_Wrap_Mode */
102
103 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
104 clock cycle before the wait state or during the wait state,
105 valid only when accessing memories in burst mode.
106 This parameter can be a value of @ref FMC_Wait_Timing */
107
108 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
109 This parameter can be a value of @ref FMC_Write_Operation */
110
111 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
112 signal, valid for Flash memory access in burst mode.
113 This parameter can be a value of @ref FMC_Wait_Signal */
114
115 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
116 This parameter can be a value of @ref FMC_Extended_Mode */
117
118 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
119 valid only with asynchronous Flash memories.
120 This parameter can be a value of @ref FMC_AsynchronousWait */
121
122 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
123 This parameter can be a value of @ref FMC_Write_Burst */
124
125 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
126 This parameter is only enabled through the FMC_BCR1 register, and don't care
127 through FMC_BCR2..4 registers.
128 This parameter can be a value of @ref FMC_Continous_Clock */
129
130 }FMC_NORSRAM_InitTypeDef;
131
132 /**
133 * @brief FMC_NORSRAM Timing parameters structure definition
134 */
135 typedef struct
136 {
137 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
138 the duration of the address setup time.
139 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
140 @note This parameter is not used with synchronous NOR Flash memories. */
141
142 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
143 the duration of the address hold time.
144 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
145 @note This parameter is not used with synchronous NOR Flash memories. */
146
147 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
148 the duration of the data setup time.
149 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
150 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
151 NOR Flash memories. */
152
153 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
154 the duration of the bus turnaround.
155 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
156 @note This parameter is only used for multiplexed NOR Flash memories. */
157
158 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
159 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
160 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
161 accesses. */
162
163 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
164 to the memory before getting the first data.
165 The parameter value depends on the memory type as shown below:
166 - It must be set to 0 in case of a CRAM
167 - It is don't care in asynchronous NOR, SRAM or ROM accesses
168 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
169 with synchronous burst mode enable */
170
171 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
172 This parameter can be a value of @ref FMC_Access_Mode */
173 }FMC_NORSRAM_TimingTypeDef;
174
175 /**
176 * @brief FMC_NAND Configuration Structure definition
177 */
178 typedef struct
179 {
180 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
181 This parameter can be a value of @ref FMC_NAND_Bank */
182
183 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
184 This parameter can be any value of @ref FMC_Wait_feature */
185
186 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
187 This parameter can be any value of @ref FMC_NAND_Data_Width */
188
189 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
190 This parameter can be any value of @ref FMC_ECC */
191
192 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
193 This parameter can be any value of @ref FMC_ECC_Page_Size */
194
195 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
196 delay between CLE low and RE low.
197 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
198
199 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
200 delay between ALE low and RE low.
201 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
202 }FMC_NAND_InitTypeDef;
203
204 /**
205 * @brief FMC_NAND_PCCARD Timing parameters structure definition
206 */
207 typedef struct
208 {
209 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
210 the command assertion for NAND-Flash read or write access
211 to common/Attribute or I/O memory space (depending on
212 the memory space timing to be configured).
213 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
214
215 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
216 command for NAND-Flash read or write access to
217 common/Attribute or I/O memory space (depending on the
218 memory space timing to be configured).
219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
220
221 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
222 (and data for write access) after the command de-assertion
223 for NAND-Flash read or write access to common/Attribute
224 or I/O memory space (depending on the memory space timing
225 to be configured).
226 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
227
228 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
229 data bus is kept in HiZ after the start of a NAND-Flash
230 write access to common/Attribute or I/O memory space (depending
231 on the memory space timing to be configured).
232 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
233 }FMC_NAND_PCC_TimingTypeDef;
234
235 /**
236 * @brief FMC_NAND Configuration Structure definition
237 */
238 typedef struct
239 {
240 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
241 This parameter can be any value of @ref FMC_Wait_feature */
242
243 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
244 delay between CLE low and RE low.
245 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
246
247 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
248 delay between ALE low and RE low.
249 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
250 }FMC_PCCARD_InitTypeDef;
251
252 /**
253 * @brief FMC_SDRAM Configuration Structure definition
254 */
255 typedef struct
256 {
257 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
258 This parameter can be a value of @ref FMC_SDRAM_Bank */
259
260 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
261 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
262
263 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
264 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
265
266 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
267 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
268
269 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
270 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
271
272 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
273 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
274
275 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
276 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
277
278 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
279 to disable the clock before changing frequency.
280 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
281
282 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
283 commands during the CAS latency and stores data in the Read FIFO.
284 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
285
286 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
287 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
288 }FMC_SDRAM_InitTypeDef;
289
290 /**
291 * @brief FMC_SDRAM Timing parameters structure definition
292 */
293 typedef struct
294 {
295 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
296 an active or Refresh command in number of memory clock cycles.
297 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
298
299 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
300 issuing the Activate command in number of memory clock cycles.
301 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
302
303 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
304 cycles.
305 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
306
307 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
308 and the delay between two consecutive Refresh commands in number of
309 memory clock cycles.
310 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
311
312 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
313 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
314
315 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
316 in number of memory clock cycles.
317 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
318
319 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
320 command in number of memory clock cycles.
321 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
322 }FMC_SDRAM_TimingTypeDef;
323
324 /**
325 * @brief SDRAM command parameters structure definition
326 */
327 typedef struct
328 {
329 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
330 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
331
332 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
333 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
334
335 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
336 in auto refresh mode.
337 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
338 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
339 }FMC_SDRAM_CommandTypeDef;
340
341 /* Exported constants --------------------------------------------------------*/
342
343 /** @defgroup FMC_NOR_SRAM_Controller
344 * @{
345 */
346
347 /** @defgroup FMC_NORSRAM_Bank
348 * @{
349 */
350 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
351 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
352 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
353 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
354
355 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
356 ((BANK) == FMC_NORSRAM_BANK2) || \
357 ((BANK) == FMC_NORSRAM_BANK3) || \
358 ((BANK) == FMC_NORSRAM_BANK4))
359 /**
360 * @}
361 */
362
363 /** @defgroup FMC_Data_Address_Bus_Multiplexing
364 * @{
365 */
366 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
367 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
368
369 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
370 ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
371 /**
372 * @}
373 */
374
375 /** @defgroup FMC_Memory_Type
376 * @{
377 */
378 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
379 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
380 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
381
382 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
383 ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
384 ((MEMORY) == FMC_MEMORY_TYPE_NOR))
385 /**
386 * @}
387 */
388
389 /** @defgroup FMC_NORSRAM_Data_Width
390 * @{
391 */
392 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
393 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
394 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
395
396 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
397 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
398 ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
399 /**
400 * @}
401 */
402
403 /** @defgroup FMC_NORSRAM_Flash_Access
404 * @{
405 */
406 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
407 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
408 /**
409 * @}
410 */
411
412 /** @defgroup FMC_Burst_Access_Mode
413 * @{
414 */
415 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
416 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
417
418 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
419 ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
420 /**
421 * @}
422 */
423
424
425 /** @defgroup FMC_Wait_Signal_Polarity
426 * @{
427 */
428 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
429 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
430
431 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
432 ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
433 /**
434 * @}
435 */
436
437 /** @defgroup FMC_Wrap_Mode
438 * @{
439 */
440 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
441 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
442
443 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
444 ((MODE) == FMC_WRAP_MODE_ENABLE))
445 /**
446 * @}
447 */
448
449 /** @defgroup FMC_Wait_Timing
450 * @{
451 */
452 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
453 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
454
455 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
456 ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
457 /**
458 * @}
459 */
460
461 /** @defgroup FMC_Write_Operation
462 * @{
463 */
464 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
465 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
466
467 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
468 ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
469 /**
470 * @}
471 */
472
473 /** @defgroup FMC_Wait_Signal
474 * @{
475 */
476 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
477 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
478
479 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
480 ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
481 /**
482 * @}
483 */
484
485 /** @defgroup FMC_Extended_Mode
486 * @{
487 */
488 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
489 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
490
491 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
492 ((MODE) == FMC_EXTENDED_MODE_ENABLE))
493 /**
494 * @}
495 */
496
497 /** @defgroup FMC_AsynchronousWait
498 * @{
499 */
500 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
501 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
502
503 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
504 ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
505 /**
506 * @}
507 */
508
509 /** @defgroup FMC_Write_Burst
510 * @{
511 */
512 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
513 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
514
515 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
516 ((BURST) == FMC_WRITE_BURST_ENABLE))
517 /**
518 * @}
519 */
520
521 /** @defgroup FMC_Continous_Clock
522 * @{
523 */
524 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
525 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
526
527 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
528 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
529 /**
530 * @}
531 */
532
533 /** @defgroup FMC_Address_Setup_Time
534 * @{
535 */
536 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
537 /**
538 * @}
539 */
540
541 /** @defgroup FMC_Address_Hold_Time
542 * @{
543 */
544 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
545 /**
546 * @}
547 */
548
549 /** @defgroup FMC_Data_Setup_Time
550 * @{
551 */
552 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
553 /**
554 * @}
555 */
556
557 /** @defgroup FMC_Bus_Turn_around_Duration
558 * @{
559 */
560 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
561 /**
562 * @}
563 */
564
565 /** @defgroup FMC_CLK_Division
566 * @{
567 */
568 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
569 /**
570 * @}
571 */
572
573 /** @defgroup FMC_Data_Latency
574 * @{
575 */
576 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
577 /**
578 * @}
579 */
580
581 /** @defgroup FMC_Access_Mode
582 * @{
583 */
584 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
585 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
586 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
587 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
588
589 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
590 ((MODE) == FMC_ACCESS_MODE_B) || \
591 ((MODE) == FMC_ACCESS_MODE_C) || \
592 ((MODE) == FMC_ACCESS_MODE_D))
593 /**
594 * @}
595 */
596
597 /**
598 * @}
599 */
600
601 /** @defgroup FMC_NAND_Controller
602 * @{
603 */
604
605 /** @defgroup FMC_NAND_Bank
606 * @{
607 */
608 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
609 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
610
611 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
612 ((BANK) == FMC_NAND_BANK3))
613 /**
614 * @}
615 */
616
617 /** @defgroup FMC_Wait_feature
618 * @{
619 */
620 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
621 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
622
623 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
624 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
625 /**
626 * @}
627 */
628
629 /** @defgroup FMC_PCR_Memory_Type
630 * @{
631 */
632 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
633 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
634 /**
635 * @}
636 */
637
638 /** @defgroup FMC_NAND_Data_Width
639 * @{
640 */
641 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
642 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
643
644 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
645 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
646 /**
647 * @}
648 */
649
650 /** @defgroup FMC_ECC
651 * @{
652 */
653 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
654 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
655
656 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
657 ((STATE) == FMC_NAND_ECC_ENABLE))
658 /**
659 * @}
660 */
661
662 /** @defgroup FMC_ECC_Page_Size
663 * @{
664 */
665 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
666 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
667 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
668 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
669 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
670 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
671
672 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
673 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
674 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
675 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
676 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
677 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
678 /**
679 * @}
680 */
681
682 /** @defgroup FMC_TCLR_Setup_Time
683 * @{
684 */
685 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
686 /**
687 * @}
688 */
689
690 /** @defgroup FMC_TAR_Setup_Time
691 * @{
692 */
693 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
694 /**
695 * @}
696 */
697
698 /** @defgroup FMC_Setup_Time
699 * @{
700 */
701 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
702 /**
703 * @}
704 */
705
706 /** @defgroup FMC_Wait_Setup_Time
707 * @{
708 */
709 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
710 /**
711 * @}
712 */
713
714 /** @defgroup FMC_Hold_Setup_Time
715 * @{
716 */
717 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
718 /**
719 * @}
720 */
721
722 /** @defgroup FMC_HiZ_Setup_Time
723 * @{
724 */
725 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
726 /**
727 * @}
728 */
729
730 /**
731 * @}
732 */
733
734 /** @defgroup FMC_SDRAM_Controller
735 * @{
736 */
737
738 /** @defgroup FMC_SDRAM_Bank
739 * @{
740 */
741 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
742 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
743
744 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
745 ((BANK) == FMC_SDRAM_BANK2))
746 /**
747 * @}
748 */
749
750 /** @defgroup FMC_SDRAM_Column_Bits_number
751 * @{
752 */
753 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
754 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
755 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
756 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
757
758 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
759 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
760 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
761 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
762 /**
763 * @}
764 */
765
766 /** @defgroup FMC_SDRAM_Row_Bits_number
767 * @{
768 */
769 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
770 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
771 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
772
773 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
774 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
775 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
776 /**
777 * @}
778 */
779
780 /** @defgroup FMC_SDRAM_Memory_Bus_Width
781 * @{
782 */
783 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
784 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
785 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
786
787 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
788 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
789 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
790 /**
791 * @}
792 */
793
794 /** @defgroup FMC_SDRAM_Internal_Banks_Number
795 * @{
796 */
797 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
798 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
799
800 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
801 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
802 /**
803 * @}
804 */
805
806 /** @defgroup FMC_SDRAM_CAS_Latency
807 * @{
808 */
809 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
810 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
811 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
812
813 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
814 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
815 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
816 /**
817 * @}
818 */
819
820 /** @defgroup FMC_SDRAM_Write_Protection
821 * @{
822 */
823 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
824 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
825
826 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
827 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
828 /**
829 * @}
830 */
831
832 /** @defgroup FMC_SDRAM_Clock_Period
833 * @{
834 */
835 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
836 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
837 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
838
839 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
840 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
841 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
842 /**
843 * @}
844 */
845
846 /** @defgroup FMC_SDRAM_Read_Burst
847 * @{
848 */
849 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
850 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
851
852 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
853 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
854 /**
855 * @}
856 */
857
858 /** @defgroup FMC_SDRAM_Read_Pipe_Delay
859 * @{
860 */
861 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
862 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
863 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
864
865 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
866 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
867 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
868 /**
869 * @}
870 */
871
872 /** @defgroup FMC_SDRAM_LoadToActive_Delay
873 * @{
874 */
875 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
876 /**
877 * @}
878 */
879
880 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
881 * @{
882 */
883 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
884 /**
885 * @}
886 */
887
888 /** @defgroup FMC_SDRAM_SelfRefresh_Time
889 * @{
890 */
891 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
892 /**
893 * @}
894 */
895
896 /** @defgroup FMC_SDRAM_RowCycle_Delay
897 * @{
898 */
899 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
900 /**
901 * @}
902 */
903
904 /** @defgroup FMC_SDRAM_Write_Recovery_Time
905 * @{
906 */
907 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
908 /**
909 * @}
910 */
911
912 /** @defgroup FMC_SDRAM_RP_Delay
913 * @{
914 */
915 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
916 /**
917 * @}
918 */
919
920 /** @defgroup FMC_SDRAM_RCD_Delay
921 * @{
922 */
923 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
924
925 /**
926 * @}
927 */
928
929 /** @defgroup FMC_SDRAM_Command_Mode
930 * @{
931 */
932 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
933 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
934 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
935 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
936 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
937 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
938 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
939
940 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
941 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
942 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
943 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
944 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
945 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
946 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
947 /**
948 * @}
949 */
950
951 /** @defgroup FMC_SDRAM_Command_Target
952 * @{
953 */
954 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
955 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
956 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
957
958 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
959 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
960 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
961 /**
962 * @}
963 */
964
965 /** @defgroup FMC_SDRAM_AutoRefresh_Number
966 * @{
967 */
968 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
969 /**
970 * @}
971 */
972
973 /** @defgroup FMC_SDRAM_ModeRegister_Definition
974 * @{
975 */
976 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
977 /**
978 * @}
979 */
980
981 /** @defgroup FMC_SDRAM_Refresh_rate
982 * @{
983 */
984 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
985 /**
986 * @}
987 */
988
989 /** @defgroup FMC_SDRAM_Mode_Status
990 * @{
991 */
992 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
993 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
994 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
995 /**
996 * @}
997 */
998
999 /** @defgroup FMC_NORSRAM_Device_Instance
1000 * @{
1001 */
1002 #define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
1003 /**
1004 * @}
1005 */
1006
1007 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
1008 * @{
1009 */
1010 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
1011 /**
1012 * @}
1013 */
1014
1015 /** @defgroup FMC_NAND_Device_Instance
1016 * @{
1017 */
1018 #define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup FMC_PCCARD_Device_Instance
1024 * @{
1025 */
1026 #define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
1027 /**
1028 * @}
1029 */
1030
1031 /** @defgroup FMC_SDRAM_Device_Instance
1032 * @{
1033 */
1034 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
1035 /**
1036 * @}
1037 */
1038
1039 /**
1040 * @}
1041 */
1042
1043 /** @defgroup FMC_Interrupt_definition
1044 * @brief FMC Interrupt definition
1045 * @{
1046 */
1047 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
1048 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
1049 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
1050 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
1051
1052 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
1053
1054 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
1055 ((IT) == FMC_IT_LEVEL) || \
1056 ((IT) == FMC_IT_FALLING_EDGE) || \
1057 ((IT) == FMC_IT_REFRESH_ERROR))
1058 /**
1059 * @}
1060 */
1061
1062 /** @defgroup FMC_Flag_definition
1063 * @brief FMC Flag definition
1064 * @{
1065 */
1066 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
1067 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
1068 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
1069 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
1070 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
1071 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
1072 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
1073
1074 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
1075 ((FLAG) == FMC_FLAG_LEVEL) || \
1076 ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
1077 ((FLAG) == FMC_FLAG_FEMPT) || \
1078 ((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) || \
1079 ((FLAG) == FMC_SDRAM_FLAG_BUSY))
1080
1081 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
1082 /**
1083 * @}
1084 */
1085
1086 /* Exported macro ------------------------------------------------------------*/
1087
1088 /** @defgroup FMC_NOR_Macros
1089 * @brief macros to handle NOR device enable/disable and read/write operations
1090 * @{
1091 */
1092
1093 /**
1094 * @brief Enable the NORSRAM device access.
1095 * @param __INSTANCE__: FMC_NORSRAM Instance
1096 * @param __BANK__: FMC_NORSRAM Bank
1097 * @retval None
1098 */
1099 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
1100
1101 /**
1102 * @brief Disable the NORSRAM device access.
1103 * @param __INSTANCE__: FMC_NORSRAM Instance
1104 * @param __BANK__: FMC_NORSRAM Bank
1105 * @retval None
1106 */
1107 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
1108
1109 /**
1110 * @}
1111 */
1112
1113 /** @defgroup FMC_NAND_Macros
1114 * @brief macros to handle NAND device enable/disable
1115 * @{
1116 */
1117
1118 /**
1119 * @brief Enable the NAND device access.
1120 * @param __INSTANCE__: FMC_NAND Instance
1121 * @param __BANK__: FMC_NAND Bank
1122 * @retval None
1123 */
1124 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
1125 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
1126
1127 /**
1128 * @brief Disable the NAND device access.
1129 * @param __INSTANCE__: FMC_NAND Instance
1130 * @param __BANK__: FMC_NAND Bank
1131 * @retval None
1132 */
1133 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
1134 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
1135 /**
1136 * @}
1137 */
1138
1139 /** @defgroup FMC_PCCARD_Macros
1140 * @brief macros to handle SRAM read/write operations
1141 * @{
1142 */
1143
1144 /**
1145 * @brief Enable the PCCARD device access.
1146 * @param __INSTANCE__: FMC_PCCARD Instance
1147 * @retval None
1148 */
1149 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
1150
1151 /**
1152 * @brief Disable the PCCARD device access.
1153 * @param __INSTANCE__: FMC_PCCARD Instance
1154 * @retval None
1155 */
1156 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
1157 /**
1158 * @}
1159 */
1160
1161 /** @defgroup FMC_Interrupt
1162 * @brief macros to handle FMC interrupts
1163 * @{
1164 */
1165
1166 /**
1167 * @brief Enable the NAND device interrupt.
1168 * @param __INSTANCE__: FMC_NAND instance
1169 * @param __BANK__: FMC_NAND Bank
1170 * @param __INTERRUPT__: FMC_NAND interrupt
1171 * This parameter can be any combination of the following values:
1172 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1173 * @arg FMC_IT_LEVEL: Interrupt level.
1174 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1175 * @retval None
1176 */
1177 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
1178 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
1179
1180 /**
1181 * @brief Disable the NAND device interrupt.
1182 * @param __INSTANCE__: FMC_NAND handle
1183 * @param __BANK__: FMC_NAND Bank
1184 * @param __INTERRUPT__: FMC_NAND interrupt
1185 * This parameter can be any combination of the following values:
1186 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1187 * @arg FMC_IT_LEVEL: Interrupt level.
1188 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1189 * @retval None
1190 */
1191 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
1192 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
1193
1194 /**
1195 * @brief Get flag status of the NAND device.
1196 * @param __INSTANCE__: FMC_NAND handle
1197 * @param __BANK__: FMC_NAND Bank
1198 * @param __FLAG__: FMC_NAND flag
1199 * This parameter can be any combination of the following values:
1200 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1201 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1202 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1203 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1204 * @retval The state of FLAG (SET or RESET).
1205 */
1206 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
1207 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
1208 /**
1209 * @brief Clear flag status of the NAND device.
1210 * @param __INSTANCE__: FMC_NAND handle
1211 * @param __BANK__: FMC_NAND Bank
1212 * @param __FLAG__: FMC_NAND flag
1213 * This parameter can be any combination of the following values:
1214 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1215 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1216 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1217 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1218 * @retval None
1219 */
1220 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
1221 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
1222 /**
1223 * @brief Enable the PCCARD device interrupt.
1224 * @param __INSTANCE__: FMC_PCCARD instance
1225 * @param __INTERRUPT__: FMC_PCCARD interrupt
1226 * This parameter can be any combination of the following values:
1227 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1228 * @arg FMC_IT_LEVEL: Interrupt level.
1229 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1230 * @retval None
1231 */
1232 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
1233
1234 /**
1235 * @brief Disable the PCCARD device interrupt.
1236 * @param __INSTANCE__: FMC_PCCARD instance
1237 * @param __INTERRUPT__: FMC_PCCARD interrupt
1238 * This parameter can be any combination of the following values:
1239 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1240 * @arg FMC_IT_LEVEL: Interrupt level.
1241 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1242 * @retval None
1243 */
1244 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1245
1246 /**
1247 * @brief Get flag status of the PCCARD device.
1248 * @param __INSTANCE__: FMC_PCCARD instance
1249 * @param __FLAG__: FMC_PCCARD flag
1250 * This parameter can be any combination of the following values:
1251 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1252 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1253 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1254 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1255 * @retval The state of FLAG (SET or RESET).
1256 */
1257 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1258
1259 /**
1260 * @brief Clear flag status of the PCCARD device.
1261 * @param __INSTANCE__: FMC_PCCARD instance
1262 * @param __FLAG__: FMC_PCCARD flag
1263 * This parameter can be any combination of the following values:
1264 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1265 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1266 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1267 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1268 * @retval None
1269 */
1270 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1271
1272 /**
1273 * @brief Enable the SDRAM device interrupt.
1274 * @param __INSTANCE__: FMC_SDRAM instance
1275 * @param __INTERRUPT__: FMC_SDRAM interrupt
1276 * This parameter can be any combination of the following values:
1277 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1278 * @retval None
1279 */
1280 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1281
1282 /**
1283 * @brief Disable the SDRAM device interrupt.
1284 * @param __INSTANCE__: FMC_SDRAM instance
1285 * @param __INTERRUPT__: FMC_SDRAM interrupt
1286 * This parameter can be any combination of the following values:
1287 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1288 * @retval None
1289 */
1290 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1291
1292 /**
1293 * @brief Get flag status of the SDRAM device.
1294 * @param __INSTANCE__: FMC_SDRAM instance
1295 * @param __FLAG__: FMC_SDRAM flag
1296 * This parameter can be any combination of the following values:
1297 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1298 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1299 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1300 * @retval The state of FLAG (SET or RESET).
1301 */
1302 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1303
1304 /**
1305 * @brief Clear flag status of the SDRAM device.
1306 * @param __INSTANCE__: FMC_SDRAM instance
1307 * @param __FLAG__: FMC_SDRAM flag
1308 * This parameter can be any combination of the following values:
1309 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1310 * @retval None
1311 */
1312 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1313 /**
1314 * @}
1315 */
1316
1317 /* Exported functions --------------------------------------------------------*/
1318
1319 /* FMC_NORSRAM Controller functions *******************************************/
1320 /* Initialization/de-initialization functions */
1321 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1322 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1323 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1324 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1325
1326 /* FMC_NORSRAM Control functions */
1327 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1328 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1329
1330 /* FMC_NAND Controller functions **********************************************/
1331 /* Initialization/de-initialization functions */
1332 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1333 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1334 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1335 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1336
1337 /* FMC_NAND Control functions */
1338 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1339 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1340 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1341
1342 /* FMC_PCCARD Controller functions ********************************************/
1343 /* Initialization/de-initialization functions */
1344 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1345 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1346 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1347 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1348 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1349
1350 /* FMC_SDRAM Controller functions *********************************************/
1351 /* Initialization/de-initialization functions */
1352 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1353 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1354 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1355
1356 /* FMC_SDRAM Control functions */
1357 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1358 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1359 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1360 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1361 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1362 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1363
1364 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1365 /**
1366 * @}
1367 */
1368
1369 /**
1370 * @}
1371 */
1372
1373 #ifdef __cplusplus
1374 }
1375 #endif
1376
1377 #endif /* __STM32F4xx_LL_FMC_H */
1378
1379 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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