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Merge commit 'fdc38ef3f92af7adeeb4de49550d8838c8a39b5c'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L0 / stm32l0xx_hal_tim.c
1 /**
2 ******************************************************************************
3 * @file stm32l0xx_hal_tim.c
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 06-February-2015
7 * @brief TIM HAL module driver.
8 * @brief This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Timer Base Initialization
11 * + Timer Base Start
12 * + Timer Base Start Interruption
13 * + Timer Base Start DMA
14 * + Timer Output Compare/PWM Initialization
15 * + Timer Output Compare/PWM Channel Configuration
16 * + Timer Output Compare/PWM Start
17 * + Timer Output Compare/PWM Start Interruption
18 * + Timer Output Compare/PWM Start DMA
19 * + Timer Input Capture Initialization
20 * + Timer Input Capture Channel Configuration
21 * + Timer Input Capture Start
22 * + Timer Input Capture Start Interruption
23 * + Timer Input Capture Start DMA
24 * + Timer One Pulse Initialization
25 * + Timer One Pulse Channel Configuration
26 * + Timer One Pulse Start
27 * + Timer Encoder Interface Initialization
28 * + Timer Encoder Interface Start
29 * + Timer Encoder Interface Start Interruption
30 * + Timer Encoder Interface Start DMA
31 * + Timer OCRef clear configuration
32 * + Timer External Clock configuration
33 * + Timer Complementary signal bread and dead time configuration
34 * + Timer Master and Slave synchronization configuration
35 @verbatim
36 ==============================================================================
37 ##### TIMER Generic features #####
38 ==============================================================================
39 [..] The Timer features include:
40 (#) 16-bit up, down, up/down auto-reload counter.
41 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
42 frequency either by any factor between 1 and 65536.
43 (#) Up to 4 independent channels for:
44 (++) Input Capture
45 (++) Output Compare
46 (++) PWM generation (Edge and Center-aligned Mode)
47 (++) One-pulse mode output
48 (#) Synchronization circuit to control the timer with external signals and to interconnect
49 several timers together.
50 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
51 purposes
52
53 ##### How to use this driver #####
54 ================================================================================
55 [..]
56 (#) Initialize the TIM low level resources by implementing the following functions
57 depending from feature used :
58 (++) Time Base : HAL_TIM_Base_MspInit()
59 (++) Input Capture : HAL_TIM_IC_MspInit()
60 (++) Output Compare : HAL_TIM_OC_MspInit()
61 (++) PWM generation : HAL_TIM_PWM_MspInit()
62 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
63 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
64
65 (#) Initialize the TIM low level resources :
66 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
67 (##) TIM pins configuration
68 (+++) Enable the clock for the TIM GPIOs using the following function:
69 __HAL_RCC_GPIOx_CLK_ENABLE();
70 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
71
72 (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
73 using the following function:
74 HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
75
76 (#) Configure the TIM in the desired functioning mode using one of the
77 initialization function of this driver:
78 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
79 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
80 Output Compare signal.
81 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
82 PWM signal.
83 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
84 external signal.
85 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode.
86 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
87
88 (#) Activate the TIM peripheral using one of the start functions:
89 HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(),
90 HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(),
91 HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(),
92 HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(),
93 HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(),
94 HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT()
95
96 (#) The DMA Burst is managed with the two following functions:
97 HAL_TIM_DMABurst_WriteStart
98 HAL_TIM_DMABurst_ReadStart
99
100 @endverbatim
101 ******************************************************************************
102 * @attention
103 *
104 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
105 *
106 * Redistribution and use in source and binary forms, with or without modification,
107 * are permitted provided that the following conditions are met:
108 * 1. Redistributions of source code must retain the above copyright notice,
109 * this list of conditions and the following disclaimer.
110 * 2. Redistributions in binary form must reproduce the above copyright notice,
111 * this list of conditions and the following disclaimer in the documentation
112 * and/or other materials provided with the distribution.
113 * 3. Neither the name of STMicroelectronics nor the names of its contributors
114 * may be used to endorse or promote products derived from this software
115 * without specific prior written permission.
116 *
117 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
118 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
119 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
120 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
121 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
122 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
123 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
124 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
125 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
126 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
127 *
128 ******************************************************************************
129 */
130
131 /* Includes ------------------------------------------------------------------*/
132 #include "stm32l0xx_hal.h"
133
134 /** @addtogroup STM32L0xx_HAL_Driver
135 * @{
136 */
137
138 /** @addtogroup TIM
139 * @brief TIM HAL module driver
140 * @{
141 */
142
143 #ifdef HAL_TIM_MODULE_ENABLED
144
145 /* Private typedef -----------------------------------------------------------*/
146 /* Private define ------------------------------------------------------------*/
147 /* Private macro -------------------------------------------------------------*/
148 /* Private variables ---------------------------------------------------------*/
149 /* Private function prototypes -----------------------------------------------*/
150 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
152 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
153 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
154 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
155 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
156 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
157 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
158 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
159 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
161 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
162 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
163 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
166 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,TIM_SlaveConfigTypeDef * sSlaveConfig);
167
168 /*******************************************************************************/
169 /* Exported functions ---------------------------------------------------------*/
170 /*******************************************************************************/
171
172 /** @addtogroup TIM_Exported_Functions
173 * @{
174 */
175
176 /** @addtogroup TIM_Exported_Functions_Group1
177 * @brief Time Base functions
178 *
179 @verbatim
180 ==============================================================================
181 ##### Timer Base functions #####
182 ==============================================================================
183 [..]
184 This section provides functions allowing to:
185 (+) Initialize and configure the TIM base.
186 (+) De-initialize the TIM base.
187 (+) Start the Timer Base.
188 (+) Stop the Timer Base.
189 (+) Start the Timer Base and enable interrupt.
190 (+) Stop the Timer Base and disable interrupt.
191 (+) Start the Timer Base and enable DMA transfer.
192 (+) Stop the Timer Base and disable DMA transfer.
193
194 @endverbatim
195 * @{
196 */
197 /**
198 * @brief Initializes the TIM Time base Unit according to the specified
199 * parameters in the TIM_HandleTypeDef and create the associated handle.
200 * @param htim : TIM handle
201 * @retval HAL status
202 */
203 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
204 {
205 /* Check the TIM handle allocation */
206 if(htim == NULL)
207 {
208 return HAL_ERROR;
209 }
210
211 /* Check the parameters */
212 assert_param(IS_TIM_INSTANCE(htim->Instance));
213 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
214 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
215 assert_param(IS_TIM_PERIOD(htim->Init.Period));
216 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
217
218 if(htim->State == HAL_TIM_STATE_RESET)
219 {
220 /* Init the low level hardware : GPIO, CLOCK, NVIC */
221 HAL_TIM_Base_MspInit(htim);
222 }
223
224 /* Set the TIM state */
225 htim->State= HAL_TIM_STATE_BUSY;
226
227 /* Set the Time Base configuration */
228 TIM_Base_SetConfig(htim->Instance, &htim->Init);
229
230 /* Initialize the TIM state*/
231 htim->State= HAL_TIM_STATE_READY;
232
233 return HAL_OK;
234 }
235
236 /**
237 * @brief DeInitializes the TIM Base peripheral
238 * @param htim : TIM handle
239 * @retval HAL status
240 */
241 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
242 {
243 /* Check the parameters */
244 assert_param(IS_TIM_INSTANCE(htim->Instance));
245
246 htim->State = HAL_TIM_STATE_BUSY;
247
248 /* Disable the TIM Peripheral Clock */
249 __HAL_TIM_DISABLE(htim);
250
251 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
252 HAL_TIM_Base_MspDeInit(htim);
253
254 /* Change TIM state */
255 htim->State = HAL_TIM_STATE_RESET;
256
257 /* Release Lock */
258 __HAL_UNLOCK(htim);
259
260 return HAL_OK;
261 }
262
263 /**
264 * @brief Initializes the TIM Base MSP.
265 * @param htim : TIM handle
266 * @retval None
267 */
268 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
269 {
270 /* NOTE : This function Should not be modified, when the callback is needed,
271 the HAL_TIM_Base_MspInit could be implemented in the user file
272 */
273 }
274
275 /**
276 * @brief DeInitializes TIM Base MSP.
277 * @param htim : TIM handle
278 * @retval None
279 */
280 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
281 {
282 /* NOTE : This function Should not be modified, when the callback is needed,
283 the HAL_TIM_Base_MspDeInit could be implemented in the user file
284 */
285 }
286
287 /**
288 * @brief Starts the TIM Base generation.
289 * @param htim : TIM handle
290 * @retval HAL status
291 */
292 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
293 {
294 /* Check the parameters */
295 assert_param(IS_TIM_INSTANCE(htim->Instance));
296
297 /* Set the TIM state */
298 htim->State= HAL_TIM_STATE_BUSY;
299
300 /* Enable the Peripheral */
301 __HAL_TIM_ENABLE(htim);
302
303 /* Change the TIM state*/
304 htim->State= HAL_TIM_STATE_READY;
305
306 /* Return function status */
307 return HAL_OK;
308 }
309
310 /**
311 * @brief Stops the TIM Base generation.
312 * @param htim : TIM handle
313 * @retval HAL status
314 */
315 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
316 {
317 /* Check the parameters */
318 assert_param(IS_TIM_INSTANCE(htim->Instance));
319
320 /* Set the TIM state */
321 htim->State= HAL_TIM_STATE_BUSY;
322
323 /* Disable the Peripheral */
324 __HAL_TIM_DISABLE(htim);
325
326 /* Change the TIM state*/
327 htim->State= HAL_TIM_STATE_READY;
328
329 /* Return function status */
330 return HAL_OK;
331 }
332
333 /**
334 * @brief Starts the TIM Base generation in interrupt mode.
335 * @param htim : TIM handle
336 * @retval HAL status
337 */
338 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
339 {
340 /* Check the parameters */
341 assert_param(IS_TIM_INSTANCE(htim->Instance));
342
343 /* Enable the TIM Update interrupt */
344 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
345
346 /* Enable the Peripheral */
347 __HAL_TIM_ENABLE(htim);
348
349 /* Return function status */
350 return HAL_OK;
351 }
352
353 /**
354 * @brief Stops the TIM Base generation in interrupt mode.
355 * @param htim : TIM handle
356 * @retval HAL status
357 */
358 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
359 {
360 /* Check the parameters */
361 assert_param(IS_TIM_INSTANCE(htim->Instance));
362 /* Disable the TIM Update interrupt */
363 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
364
365 /* Disable the Peripheral */
366 __HAL_TIM_DISABLE(htim);
367
368 /* Return function status */
369 return HAL_OK;
370 }
371
372 /**
373 * @brief Starts the TIM Base generation in DMA mode.
374 * @param htim : TIM handle
375 * @param pData: The source Buffer address.
376 * @param Length: The length of data to be transferred from memory to peripheral.
377 * @retval HAL status
378 */
379 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
380 {
381 /* Check the parameters */
382 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
383
384 if((htim->State == HAL_TIM_STATE_BUSY))
385 {
386 return HAL_BUSY;
387 }
388 else if((htim->State == HAL_TIM_STATE_READY))
389 {
390 if((pData == 0 ) && (Length > 0))
391 {
392 return HAL_ERROR;
393 }
394 else
395 {
396 htim->State = HAL_TIM_STATE_BUSY;
397 }
398 }
399 /* Set the DMA Period elapsed callback */
400 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
401
402 /* Set the DMA error callback */
403 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
404
405 /* Enable the DMA Stream */
406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
407
408 /* Enable the TIM Update DMA request */
409 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
410
411 /* Enable the Peripheral */
412 __HAL_TIM_ENABLE(htim);
413
414 /* Return function status */
415 return HAL_OK;
416 }
417
418 /**
419 * @brief Stops the TIM Base generation in DMA mode.
420 * @param htim : TIM handle
421 * @retval HAL status
422 */
423 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
424 {
425 /* Check the parameters */
426 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
427
428 /* Disable the TIM Update DMA request */
429 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
430
431 /* Disable the Peripheral */
432 __HAL_TIM_DISABLE(htim);
433
434 /* Change the htim state */
435 htim->State = HAL_TIM_STATE_READY;
436
437 /* Return function status */
438 return HAL_OK;
439 }
440
441 /**
442 * @}
443 */
444
445
446 /** @addtogroup TIM_Exported_Functions_Group2
447 * @brief Time Output Compare functions
448 *
449 @verbatim
450 ==============================================================================
451 ##### Timer Output Compare functions #####
452 ==============================================================================
453 [..]
454 This section provides functions allowing to:
455 (+) Initialize and configure the TIM Output Compare.
456 (+) De-initialize the TIM Output Compare.
457 (+) Start the Timer Output Compare.
458 (+) Stop the Timer Output Compare.
459 (+) Start the Timer Output Compare and enable interrupt.
460 (+) Stop the Timer Output Compare and disable interrupt.
461 (+) Start the Timer Output Compare and enable DMA transfer.
462 (+) Stop the Timer Output Compare and disable DMA transfer.
463
464 @endverbatim
465 * @{
466 */
467 /**
468 * @brief Initializes the TIM Output Compare according to the specified
469 * parameters in the TIM_HandleTypeDef and create the associated handle.
470 * @param htim: TIM Output Compare handle
471 * @retval HAL status
472 */
473 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
474 {
475 /* Check the TIM handle allocation */
476 if(htim == NULL)
477 {
478 return HAL_ERROR;
479 }
480
481 /* Check the parameters */
482 assert_param(IS_TIM_INSTANCE(htim->Instance));
483 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
484 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
485 assert_param(IS_TIM_PERIOD(htim->Init.Period));
486 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
487
488 if(htim->State == HAL_TIM_STATE_RESET)
489 {
490 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/
491 HAL_TIM_OC_MspInit(htim);
492 }
493 /* Set the TIM state */
494 htim->State= HAL_TIM_STATE_BUSY;
495
496 /* Init the base time for the Output Compare */
497 TIM_Base_SetConfig(htim->Instance, &htim->Init);
498
499 /* Initialize the TIM state*/
500 htim->State= HAL_TIM_STATE_READY;
501
502 return HAL_OK;
503 }
504
505 /**
506 * @brief DeInitializes the TIM peripheral
507 * @param htim: TIM Output Compare handle
508 * @retval HAL status
509 */
510 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
511 {
512 /* Check the parameters */
513 assert_param(IS_TIM_INSTANCE(htim->Instance));
514
515 htim->State = HAL_TIM_STATE_BUSY;
516
517 /* Disable the TIM Peripheral Clock */
518 __HAL_TIM_DISABLE(htim);
519
520 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
521 HAL_TIM_OC_MspDeInit(htim);
522
523 /* Change TIM state */
524 htim->State = HAL_TIM_STATE_RESET;
525
526 /* Release Lock */
527 __HAL_UNLOCK(htim);
528
529 return HAL_OK;
530 }
531
532 /**
533 * @brief Initializes the TIM Output Compare MSP.
534 * @param htim : TIM handle
535 * @retval None
536 */
537 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
538 {
539 /* NOTE : This function Should not be modified, when the callback is needed,
540 the HAL_TIM_OC_MspInit could be implemented in the user file
541 */
542 }
543
544 /**
545 * @brief DeInitializes TIM Output Compare MSP.
546 * @param htim : TIM handle
547 * @retval None
548 */
549 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
550 {
551 /* NOTE : This function Should not be modified, when the callback is needed,
552 the HAL_TIM_OC_MspDeInit could be implemented in the user file
553 */
554 }
555
556 /**
557 * @brief Starts the TIM Output Compare signal generation.
558 * @param htim : TIM handle
559 * @param Channel: TIM Channel to be enabled.
560 * This parameter can be one of the following values:
561 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
562 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
563 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
564 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
565 * @retval HAL status
566 */
567 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
568 {
569 /* Check the parameters */
570 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
571
572 /* Enable the Output compare channel */
573 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
574
575 /* Enable the Peripheral */
576 __HAL_TIM_ENABLE(htim);
577
578 /* Return function status */
579 return HAL_OK;
580 }
581
582 /**
583 * @brief Stops the TIM Output Compare signal generation.
584 * @param htim : TIM handle
585 * @param Channel: TIM Channel to be disabled.
586 * This parameter can be one of the following values:
587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
591 * @retval HAL status
592 */
593 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
594 {
595 /* Check the parameters */
596 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
597
598 /* Disable the Output compare channel */
599 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
600
601 /* Disable the Peripheral */
602 __HAL_TIM_DISABLE(htim);
603
604 /* Return function status */
605 return HAL_OK;
606 }
607
608 /**
609 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
610 * @param htim : TIM handle
611 * @param Channel: TIM Channel to be enabled.
612 * This parameter can be one of the following values:
613 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
614 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
615 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
616 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
617 * @retval HAL status
618 */
619 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
620 {
621 /* Check the parameters */
622 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
623
624 switch (Channel)
625 {
626 case TIM_CHANNEL_1:
627 {
628 /* Enable the TIM Capture/Compare 1 interrupt */
629 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
630 }
631 break;
632
633 case TIM_CHANNEL_2:
634 {
635 /* Enable the TIM Capture/Compare 2 interrupt */
636 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
637 }
638 break;
639
640 case TIM_CHANNEL_3:
641 {
642 /* Enable the TIM Capture/Compare 3 interrupt */
643 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
644 }
645 break;
646
647 case TIM_CHANNEL_4:
648 {
649 /* Enable the TIM Capture/Compare 4 interrupt */
650 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
651 }
652 break;
653
654 default:
655 break;
656 }
657
658 /* Enable the Output compare channel */
659 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
660
661 /* Enable the Peripheral */
662 __HAL_TIM_ENABLE(htim);
663
664 /* Return function status */
665 return HAL_OK;
666 }
667
668 /**
669 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
670 * @param htim : TIM handle
671 * @param Channel: TIM Channel to be disabled.
672 * This parameter can be one of the following values:
673 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
674 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
675 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
676 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
677 * @retval HAL status
678 */
679 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
680 {
681 /* Check the parameters */
682 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
683
684 switch (Channel)
685 {
686 case TIM_CHANNEL_1:
687 {
688 /* Disable the TIM Capture/Compare 1 interrupt */
689 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
690 }
691 break;
692
693 case TIM_CHANNEL_2:
694 {
695 /* Disable the TIM Capture/Compare 2 interrupt */
696 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
697 }
698 break;
699
700 case TIM_CHANNEL_3:
701 {
702 /* Disable the TIM Capture/Compare 3 interrupt */
703 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
704 }
705 break;
706
707 case TIM_CHANNEL_4:
708 {
709 /* Disable the TIM Capture/Compare 4 interrupt */
710 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
711 }
712 break;
713
714 default:
715 break;
716 }
717
718 /* Disable the Output compare channel */
719 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
720
721 /* Disable the Peripheral */
722 __HAL_TIM_DISABLE(htim);
723
724 /* Return function status */
725 return HAL_OK;
726 }
727
728 /**
729 * @brief Starts the TIM Output Compare signal generation in DMA mode.
730 * @param htim : TIM handle
731 * @param Channel: TIM Channel to be enabled.
732 * This parameter can be one of the following values:
733 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
734 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
735 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
736 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
737 * @param pData: The source Buffer address.
738 * @param Length: The length of data to be transferred from memory to TIM peripheral
739 * @retval HAL status
740 */
741 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
742 {
743 /* Check the parameters */
744 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
745
746 if((htim->State == HAL_TIM_STATE_BUSY))
747 {
748 return HAL_BUSY;
749 }
750 else if((htim->State == HAL_TIM_STATE_READY))
751 {
752 if(((uint32_t)pData == 0 ) && (Length > 0))
753 {
754 return HAL_ERROR;
755 }
756 else
757 {
758 htim->State = HAL_TIM_STATE_BUSY;
759 }
760 }
761 switch (Channel)
762 {
763 case TIM_CHANNEL_1:
764 {
765 /* Set the DMA Period elapsed callback */
766 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
767
768 /* Set the DMA error callback */
769 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
770
771 /* Enable the DMA Stream */
772 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
773
774 /* Enable the TIM Capture/Compare 1 DMA request */
775 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
776 }
777 break;
778
779 case TIM_CHANNEL_2:
780 {
781 /* Set the DMA Period elapsed callback */
782 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
783
784 /* Set the DMA error callback */
785 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
786
787 /* Enable the DMA Stream */
788 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
789
790 /* Enable the TIM Capture/Compare 2 DMA request */
791 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
792 }
793 break;
794
795 case TIM_CHANNEL_3:
796 {
797 /* Set the DMA Period elapsed callback */
798 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
799
800 /* Set the DMA error callback */
801 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
802
803 /* Enable the DMA Stream */
804 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
805
806 /* Enable the TIM Capture/Compare 3 DMA request */
807 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
808 }
809 break;
810
811 case TIM_CHANNEL_4:
812 {
813 /* Set the DMA Period elapsed callback */
814 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
815
816 /* Set the DMA error callback */
817 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
818
819 /* Enable the DMA Stream */
820 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
821
822 /* Enable the TIM Capture/Compare 4 DMA request */
823 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
824 }
825 break;
826
827 default:
828 break;
829 }
830
831 /* Enable the Output compare channel */
832 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
833
834 /* Enable the Peripheral */
835 __HAL_TIM_ENABLE(htim);
836
837 /* Return function status */
838 return HAL_OK;
839 }
840
841 /**
842 * @brief Stops the TIM Output Compare signal generation in DMA mode.
843 * @param htim : TIM handle
844 * @param Channel: TIM Channel to be disabled.
845 * This parameter can be one of the following values:
846 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
847 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
848 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
849 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
850 * @retval HAL status
851 */
852 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
853 {
854 /* Check the parameters */
855 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
856
857 switch (Channel)
858 {
859 case TIM_CHANNEL_1:
860 {
861 /* Disable the TIM Capture/Compare 1 DMA request */
862 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
863 }
864 break;
865
866 case TIM_CHANNEL_2:
867 {
868 /* Disable the TIM Capture/Compare 2 DMA request */
869 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
870 }
871 break;
872
873 case TIM_CHANNEL_3:
874 {
875 /* Disable the TIM Capture/Compare 3 DMA request */
876 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
877 }
878 break;
879
880 case TIM_CHANNEL_4:
881 {
882 /* Disable the TIM Capture/Compare 4 interrupt */
883 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
884 }
885 break;
886
887 default:
888 break;
889 }
890
891 /* Disable the Output compare channel */
892 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
893
894 /* Disable the Peripheral */
895 __HAL_TIM_DISABLE(htim);
896
897 /* Change the htim state */
898 htim->State = HAL_TIM_STATE_READY;
899
900 /* Return function status */
901 return HAL_OK;
902 }
903
904 /**
905 * @}
906 */
907
908 /** @addtogroup TIM_Exported_Functions_Group3
909 * @brief Time PWM functions
910 *
911 @verbatim
912 ==============================================================================
913 ##### Timer PWM functions #####
914 ==============================================================================
915 [..]
916 This section provides functions allowing to:
917 (+) Initialize and configure the TIM OPWM.
918 (+) De-initialize the TIM PWM.
919 (+) Start the Timer PWM.
920 (+) Stop the Timer PWM.
921 (+) Start the Timer PWM and enable interrupt.
922 (+) Stop the Timer PWM and disable interrupt.
923 (+) Start the Timer PWM and enable DMA transfer.
924 (+) Stop the Timer PWM and disable DMA transfer.
925
926 @endverbatim
927 * @{
928 */
929 /**
930 * @brief Initializes the TIM PWM Time Base according to the specified
931 * parameters in the TIM_HandleTypeDef and create the associated handle.
932 * @param htim : TIM handle
933 * @retval HAL status
934 */
935
936
937 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
938 {
939 /* Check the TIM handle allocation */
940 if(htim == NULL)
941 {
942 return HAL_ERROR;
943 }
944
945 /* Check the parameters */
946 assert_param(IS_TIM_INSTANCE(htim->Instance));
947 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
948 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
949 assert_param(IS_TIM_PERIOD(htim->Init.Period));
950 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
951
952 if(htim->State == HAL_TIM_STATE_RESET)
953 {
954 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
955 HAL_TIM_PWM_MspInit(htim);
956 }
957
958 /* Set the TIM state */
959 htim->State= HAL_TIM_STATE_BUSY;
960
961 /* Init the base time for the PWM */
962 TIM_Base_SetConfig(htim->Instance, &htim->Init);
963
964 /* Initialize the TIM state*/
965 htim->State= HAL_TIM_STATE_READY;
966
967 return HAL_OK;
968 }
969
970 /**
971 * @brief DeInitializes the TIM peripheral
972 * @param htim : TIM handle
973 * @retval HAL status
974 */
975 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
976 {
977 /* Check the parameters */
978 assert_param(IS_TIM_INSTANCE(htim->Instance));
979
980 htim->State = HAL_TIM_STATE_BUSY;
981
982 /* Disable the TIM Peripheral Clock */
983 __HAL_TIM_DISABLE(htim);
984
985 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
986 HAL_TIM_PWM_MspDeInit(htim);
987
988 /* Change TIM state */
989 htim->State = HAL_TIM_STATE_RESET;
990
991 /* Release Lock */
992 __HAL_UNLOCK(htim);
993
994 return HAL_OK;
995 }
996
997 /**
998 * @brief Initializes the TIM PWM MSP.
999 * @param htim : TIM handle
1000 * @retval None
1001 */
1002 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1003 {
1004 /* NOTE : This function Should not be modified, when the callback is needed,
1005 the HAL_TIM_PWM_MspInit could be implemented in the user file
1006 */
1007 }
1008
1009 /**
1010 * @brief DeInitializes TIM PWM MSP.
1011 * @param htim : TIM handle
1012 * @retval None
1013 */
1014 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1015 {
1016 /* NOTE : This function Should not be modified, when the callback is needed,
1017 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1018 */
1019 }
1020
1021 /**
1022 * @brief Starts the PWM signal generation.
1023 * @param htim : TIM handle
1024 * @param Channel: TIM Channels to be enabled.
1025 * This parameter can be one of the following values:
1026 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1027 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1028 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1029 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1030 * @retval HAL status
1031 */
1032 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1033 {
1034 /* Check the parameters */
1035 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1036
1037 /* Enable the Capture compare channel */
1038 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1039
1040 /* Enable the Peripheral */
1041 __HAL_TIM_ENABLE(htim);
1042
1043 /* Return function status */
1044 return HAL_OK;
1045 }
1046
1047 /**
1048 * @brief Stops the PWM signal generation.
1049 * @param htim : TIM handle
1050 * @param Channel: TIM Channels to be disabled.
1051 * This parameter can be one of the following values:
1052 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1053 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1054 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1055 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1056 * @retval HAL status
1057 */
1058 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1059 {
1060 /* Check the parameters */
1061 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1062
1063 /* Disable the Capture compare channel */
1064 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1065
1066 /* Disable the Peripheral */
1067 __HAL_TIM_DISABLE(htim);
1068
1069 /* Change the htim state */
1070 htim->State = HAL_TIM_STATE_READY;
1071
1072 /* Return function status */
1073 return HAL_OK;
1074 }
1075
1076 /**
1077 * @brief Starts the PWM signal generation in interrupt mode.
1078 * @param htim : TIM handle
1079 * @param Channel: TIM Channel to be disabled.
1080 * This parameter can be one of the following values:
1081 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1082 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1083 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1084 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1085 * @retval HAL status
1086 */
1087 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1088 {
1089 /* Check the parameters */
1090 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1091
1092 switch (Channel)
1093 {
1094 case TIM_CHANNEL_1:
1095 {
1096 /* Enable the TIM Capture/Compare 1 interrupt */
1097 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1098 }
1099 break;
1100
1101 case TIM_CHANNEL_2:
1102 {
1103 /* Enable the TIM Capture/Compare 2 interrupt */
1104 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1105 }
1106 break;
1107
1108 case TIM_CHANNEL_3:
1109 {
1110 /* Enable the TIM Capture/Compare 3 interrupt */
1111 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1112 }
1113 break;
1114
1115 case TIM_CHANNEL_4:
1116 {
1117 /* Enable the TIM Capture/Compare 4 interrupt */
1118 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1119 }
1120 break;
1121
1122 default:
1123 break;
1124 }
1125
1126 /* Enable the Capture compare channel */
1127 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1128
1129 /* Enable the Peripheral */
1130 __HAL_TIM_ENABLE(htim);
1131
1132 /* Return function status */
1133 return HAL_OK;
1134 }
1135
1136 /**
1137 * @brief Stops the PWM signal generation in interrupt mode.
1138 * @param htim : TIM handle
1139 * @param Channel: TIM Channels to be disabled.
1140 * This parameter can be one of the following values:
1141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1143 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1144 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1145 * @retval HAL status
1146 */
1147 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1148 {
1149 /* Check the parameters */
1150 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1151
1152 switch (Channel)
1153 {
1154 case TIM_CHANNEL_1:
1155 {
1156 /* Disable the TIM Capture/Compare 1 interrupt */
1157 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1158 }
1159 break;
1160
1161 case TIM_CHANNEL_2:
1162 {
1163 /* Disable the TIM Capture/Compare 2 interrupt */
1164 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1165 }
1166 break;
1167
1168 case TIM_CHANNEL_3:
1169 {
1170 /* Disable the TIM Capture/Compare 3 interrupt */
1171 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1172 }
1173 break;
1174
1175 case TIM_CHANNEL_4:
1176 {
1177 /* Disable the TIM Capture/Compare 4 interrupt */
1178 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1179 }
1180 break;
1181
1182 default:
1183 break;
1184 }
1185
1186 /* Disable the Capture compare channel */
1187 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1188
1189 /* Disable the Peripheral */
1190 __HAL_TIM_DISABLE(htim);
1191
1192 /* Return function status */
1193 return HAL_OK;
1194 }
1195
1196 /**
1197 * @brief Starts the TIM PWM signal generation in DMA mode.
1198 * @param htim : TIM handle
1199 * @param Channel: TIM Channels to be enabled.
1200 * This parameter can be one of the following values:
1201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1205 * @param pData: The source Buffer address. This buffer contains the values
1206 * which will be loaded inside the capture/compare registers.
1207 * @param Length: The length of data to be transferred from memory to TIM peripheral
1208 * @retval HAL status
1209 */
1210 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1211 {
1212 /* Check the parameters */
1213 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1214
1215 if((htim->State == HAL_TIM_STATE_BUSY))
1216 {
1217 return HAL_BUSY;
1218 }
1219 else if((htim->State == HAL_TIM_STATE_READY))
1220 {
1221 if(((uint32_t)pData == 0 ) && (Length > 0))
1222 {
1223 return HAL_ERROR;
1224 }
1225 else
1226 {
1227 htim->State = HAL_TIM_STATE_BUSY;
1228 }
1229 }
1230 switch (Channel)
1231 {
1232 case TIM_CHANNEL_1:
1233 {
1234 /* Set the DMA Period elapsed callback */
1235 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1236
1237 /* Set the DMA error callback */
1238 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1239
1240 /* Enable the DMA Stream */
1241 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1242
1243 /* Enable the TIM Capture/Compare 1 DMA request */
1244 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1245 }
1246 break;
1247
1248 case TIM_CHANNEL_2:
1249 {
1250 /* Set the DMA Period elapsed callback */
1251 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1252
1253 /* Set the DMA error callback */
1254 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1255
1256 /* Enable the DMA Stream */
1257 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1258
1259 /* Enable the TIM Capture/Compare 2 DMA request */
1260 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1261 }
1262 break;
1263
1264 case TIM_CHANNEL_3:
1265 {
1266 /* Set the DMA Period elapsed callback */
1267 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1268
1269 /* Set the DMA error callback */
1270 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1271
1272 /* Enable the DMA Stream */
1273 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1274
1275 /* Enable the TIM Output Capture/Compare 3 request */
1276 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1277 }
1278 break;
1279
1280 case TIM_CHANNEL_4:
1281 {
1282 /* Set the DMA Period elapsed callback */
1283 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1284
1285 /* Set the DMA error callback */
1286 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1287
1288 /* Enable the DMA Stream */
1289 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1290
1291 /* Enable the TIM Capture/Compare 4 DMA request */
1292 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1293 }
1294 break;
1295
1296 default:
1297 break;
1298 }
1299
1300 /* Enable the Capture compare channel */
1301 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1302
1303 /* Enable the Peripheral */
1304 __HAL_TIM_ENABLE(htim);
1305
1306 /* Return function status */
1307 return HAL_OK;
1308 }
1309
1310 /**
1311 * @brief Stops the TIM PWM signal generation in DMA mode.
1312 * @param htim : TIM handle
1313 * @param Channel: TIM Channels to be disabled.
1314 * This parameter can be one of the following values:
1315 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1316 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1317 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1318 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1319 * @retval HAL status
1320 */
1321 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1322 {
1323 /* Check the parameters */
1324 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1325
1326 switch (Channel)
1327 {
1328 case TIM_CHANNEL_1:
1329 {
1330 /* Disable the TIM Capture/Compare 1 DMA request */
1331 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1332 }
1333 break;
1334
1335 case TIM_CHANNEL_2:
1336 {
1337 /* Disable the TIM Capture/Compare 2 DMA request */
1338 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1339 }
1340 break;
1341
1342 case TIM_CHANNEL_3:
1343 {
1344 /* Disable the TIM Capture/Compare 3 DMA request */
1345 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1346 }
1347 break;
1348
1349 case TIM_CHANNEL_4:
1350 {
1351 /* Disable the TIM Capture/Compare 4 interrupt */
1352 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1353 }
1354 break;
1355
1356 default:
1357 break;
1358 }
1359
1360 /* Disable the Capture compare channel */
1361 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1362
1363 /* Disable the Peripheral */
1364 __HAL_TIM_DISABLE(htim);
1365
1366 /* Change the htim state */
1367 htim->State = HAL_TIM_STATE_READY;
1368
1369 /* Return function status */
1370 return HAL_OK;
1371 }
1372
1373 /**
1374 * @}
1375 */
1376
1377 /** @addtogroup TIM_Exported_Functions_Group4
1378 * @brief Time Input Capture functions
1379 *
1380 @verbatim
1381 ==============================================================================
1382 ##### Timer Input Capture functions #####
1383 ==============================================================================
1384 [..]
1385 This section provides functions allowing to:
1386 (+) Initialize and configure the TIM Input Capture.
1387 (+) De-initialize the TIM Input Capture.
1388 (+) Start the Timer Input Capture.
1389 (+) Stop the Timer Input Capture.
1390 (+) Start the Timer Input Capture and enable interrupt.
1391 (+) Stop the Timer Input Capture and disable interrupt.
1392 (+) Start the Timer Input Capture and enable DMA transfer.
1393 (+) Stop the Timer Input Capture and disable DMA transfer.
1394
1395 @endverbatim
1396 * @{
1397 */
1398 /**
1399 * @brief Initializes the TIM Input Capture Time base according to the specified
1400 * parameters in the TIM_HandleTypeDef and create the associated handle.
1401 * @param htim: TIM Input Capture handle
1402 * @retval HAL status
1403 */
1404 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1405 {
1406 /* Check the TIM handle allocation */
1407 if(htim == NULL)
1408 {
1409 return HAL_ERROR;
1410 }
1411
1412 /* Check the parameters */
1413 assert_param(IS_TIM_INSTANCE(htim->Instance));
1414 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1415 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1416 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1417 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
1418
1419 if(htim->State == HAL_TIM_STATE_RESET)
1420 {
1421 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1422 HAL_TIM_IC_MspInit(htim);
1423 }
1424
1425 /* Set the TIM state */
1426 htim->State= HAL_TIM_STATE_BUSY;
1427
1428 /* Init the base time for the input capture */
1429 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1430
1431 /* Initialize the TIM state*/
1432 htim->State= HAL_TIM_STATE_READY;
1433
1434 return HAL_OK;
1435 }
1436
1437 /**
1438 * @brief DeInitializes the TIM peripheral
1439 * @param htim: TIM Input Capture handle
1440 * @retval HAL status
1441 */
1442 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1443 {
1444 /* Check the parameters */
1445 assert_param(IS_TIM_INSTANCE(htim->Instance));
1446
1447 htim->State = HAL_TIM_STATE_BUSY;
1448
1449 /* Disable the TIM Peripheral Clock */
1450 __HAL_TIM_DISABLE(htim);
1451
1452 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1453 HAL_TIM_IC_MspDeInit(htim);
1454
1455 /* Change TIM state */
1456 htim->State = HAL_TIM_STATE_RESET;
1457
1458 /* Release Lock */
1459 __HAL_UNLOCK(htim);
1460
1461 return HAL_OK;
1462 }
1463
1464 /**
1465 * @brief Initializes the TIM INput Capture MSP.
1466 * @param htim : TIM handle
1467 * @retval None
1468 */
1469 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1470 {
1471 /* NOTE : This function Should not be modified, when the callback is needed,
1472 the HAL_TIM_IC_MspInit could be implemented in the user file
1473 */
1474 }
1475
1476 /**
1477 * @brief DeInitializes TIM Input Capture MSP.
1478 * @param htim : TIM handle
1479 * @retval None
1480 */
1481 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1482 {
1483 /* NOTE : This function Should not be modified, when the callback is needed,
1484 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1485 */
1486 }
1487 /**
1488 * @brief Starts the TIM Input Capture measurement.
1489 * @param htim : TIM handle
1490 * @param Channel: TIM Channels to be enabled.
1491 * This parameter can be one of the following values:
1492 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1493 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1494 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1495 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1496 * @retval HAL status
1497 */
1498 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1499 {
1500 /* Check the parameters */
1501 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1502
1503 /* Enable the Input Capture channel */
1504 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1505
1506 /* Enable the Peripheral */
1507 __HAL_TIM_ENABLE(htim);
1508
1509 /* Return function status */
1510 return HAL_OK;
1511 }
1512
1513 /**
1514 * @brief Stops the TIM Input Capture measurement.
1515 * @param htim : TIM handle
1516 * @param Channel: TIM Channels to be disabled.
1517 * This parameter can be one of the following values:
1518 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1519 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1520 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1521 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1522 * @retval HAL status
1523 */
1524 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1525 {
1526 /* Check the parameters */
1527 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1528
1529 /* Disable the Input Capture channel */
1530 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1531
1532 /* Disable the Peripheral */
1533 __HAL_TIM_DISABLE(htim);
1534
1535 /* Return function status */
1536 return HAL_OK;
1537 }
1538
1539 /**
1540 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1541 * @param htim : TIM handle
1542 * @param Channel: TIM Channels to be enabled.
1543 * This parameter can be one of the following values:
1544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1546 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1547 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1548 * @retval HAL status
1549 */
1550 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1551 {
1552 /* Check the parameters */
1553 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1554
1555 switch (Channel)
1556 {
1557 case TIM_CHANNEL_1:
1558 {
1559 /* Enable the TIM Capture/Compare 1 interrupt */
1560 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1561 }
1562 break;
1563
1564 case TIM_CHANNEL_2:
1565 {
1566 /* Enable the TIM Capture/Compare 2 interrupt */
1567 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1568 }
1569 break;
1570
1571 case TIM_CHANNEL_3:
1572 {
1573 /* Enable the TIM Capture/Compare 3 interrupt */
1574 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1575 }
1576 break;
1577
1578 case TIM_CHANNEL_4:
1579 {
1580 /* Enable the TIM Capture/Compare 4 interrupt */
1581 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1582 }
1583 break;
1584
1585 default:
1586 break;
1587 }
1588 /* Enable the Input Capture channel */
1589 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1590
1591 /* Enable the Peripheral */
1592 __HAL_TIM_ENABLE(htim);
1593
1594 /* Return function status */
1595 return HAL_OK;
1596 }
1597
1598 /**
1599 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1600 * @param htim : TIM handle
1601 * @param Channel : TIM Channels to be disabled
1602 * This parameter can be one of the following values:
1603 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1604 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1605 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1606 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1607 * @retval HAL status
1608 */
1609 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1610 {
1611 /* Check the parameters */
1612 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1613
1614 switch (Channel)
1615 {
1616 case TIM_CHANNEL_1:
1617 {
1618 /* Disable the TIM Capture/Compare 1 interrupt */
1619 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1620 }
1621 break;
1622
1623 case TIM_CHANNEL_2:
1624 {
1625 /* Disable the TIM Capture/Compare 2 interrupt */
1626 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1627 }
1628 break;
1629
1630 case TIM_CHANNEL_3:
1631 {
1632 /* Disable the TIM Capture/Compare 3 interrupt */
1633 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1634 }
1635 break;
1636
1637 case TIM_CHANNEL_4:
1638 {
1639 /* Disable the TIM Capture/Compare 4 interrupt */
1640 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1641 }
1642 break;
1643
1644 default:
1645 break;
1646 }
1647
1648 /* Disable the Input Capture channel */
1649 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1650
1651 /* Disable the Peripheral */
1652 __HAL_TIM_DISABLE(htim);
1653
1654 /* Return function status */
1655 return HAL_OK;
1656 }
1657
1658 /**
1659 * @brief Starts the TIM Input Capture measurement on in DMA mode.
1660 * @param htim : TIM handle
1661 * @param Channel : TIM Channels to be enabled
1662 * This parameter can be one of the following values:
1663 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1664 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1665 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1666 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1667 * @param pData: The destination Buffer address.
1668 * @param Length: The length of data to be transferred from TIM peripheral to memory.
1669 * @retval HAL status
1670 */
1671 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1672 {
1673 /* Check the parameters */
1674 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1675 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1676
1677 if((htim->State == HAL_TIM_STATE_BUSY))
1678 {
1679 return HAL_BUSY;
1680 }
1681 else if((htim->State == HAL_TIM_STATE_READY))
1682 {
1683 if((pData == 0 ) && (Length > 0))
1684 {
1685 return HAL_ERROR;
1686 }
1687 else
1688 {
1689 htim->State = HAL_TIM_STATE_BUSY;
1690 }
1691 }
1692
1693 switch (Channel)
1694 {
1695 case TIM_CHANNEL_1:
1696 {
1697 /* Set the DMA Period elapsed callback */
1698 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
1699
1700 /* Set the DMA error callback */
1701 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1702
1703 /* Enable the DMA Stream */
1704 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1705
1706 /* Enable the TIM Capture/Compare 1 DMA request */
1707 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1708 }
1709 break;
1710
1711 case TIM_CHANNEL_2:
1712 {
1713 /* Set the DMA Period elapsed callback */
1714 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
1715
1716 /* Set the DMA error callback */
1717 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1718
1719 /* Enable the DMA Stream */
1720 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1721
1722 /* Enable the TIM Capture/Compare 2 DMA request */
1723 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1724 }
1725 break;
1726
1727 case TIM_CHANNEL_3:
1728 {
1729 /* Set the DMA Period elapsed callback */
1730 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
1731
1732 /* Set the DMA error callback */
1733 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1734
1735 /* Enable the DMA Stream */
1736 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1737
1738 /* Enable the TIM Capture/Compare 3 DMA request */
1739 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1740 }
1741 break;
1742
1743 case TIM_CHANNEL_4:
1744 {
1745 /* Set the DMA Period elapsed callback */
1746 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
1747
1748 /* Set the DMA error callback */
1749 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1750
1751 /* Enable the DMA Stream */
1752 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1753
1754 /* Enable the TIM Capture/Compare 4 DMA request */
1755 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1756 }
1757 break;
1758
1759 default:
1760 break;
1761 }
1762
1763 /* Enable the Input Capture channel */
1764 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1765
1766 /* Enable the Peripheral */
1767 __HAL_TIM_ENABLE(htim);
1768
1769 /* Return function status */
1770 return HAL_OK;
1771 }
1772
1773 /**
1774 * @brief Stops the TIM Input Capture measurement on in DMA mode.
1775 * @param htim : TIM handle
1776 * @param Channel : TIM Channels to be disabled
1777 * This parameter can be one of the following values:
1778 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1779 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1780 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1781 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1782 * @retval HAL status
1783 */
1784 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1785 {
1786 /* Check the parameters */
1787 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1788 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1789
1790 switch (Channel)
1791 {
1792 case TIM_CHANNEL_1:
1793 {
1794 /* Disable the TIM Capture/Compare 1 DMA request */
1795 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1796 }
1797 break;
1798
1799 case TIM_CHANNEL_2:
1800 {
1801 /* Disable the TIM Capture/Compare 2 DMA request */
1802 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1803 }
1804 break;
1805
1806 case TIM_CHANNEL_3:
1807 {
1808 /* Disable the TIM Capture/Compare 3 DMA request */
1809 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1810 }
1811 break;
1812
1813 case TIM_CHANNEL_4:
1814 {
1815 /* Disable the TIM Capture/Compare 4 DMA request */
1816 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1817 }
1818 break;
1819
1820 default:
1821 break;
1822 }
1823
1824 /* Disable the Input Capture channel */
1825 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1826
1827 /* Disable the Peripheral */
1828 __HAL_TIM_DISABLE(htim);
1829
1830 /* Change the htim state */
1831 htim->State = HAL_TIM_STATE_READY;
1832
1833 /* Return function status */
1834 return HAL_OK;
1835 }
1836
1837 /**
1838 * @}
1839 */
1840
1841 /** @addtogroup TIM_Exported_Functions_Group5
1842 * @brief Time One Pulse functions
1843 *
1844 @verbatim
1845 ==============================================================================
1846 ##### Timer One Pulse functions #####
1847 ==============================================================================
1848 [..]
1849 This section provides functions allowing to:
1850 (+) Initialize and configure the TIM One Pulse.
1851 (+) De-initialize the TIM One Pulse.
1852 (+) Start the Timer One Pulse.
1853 (+) Stop the Timer One Pulse.
1854 (+) Start the Timer One Pulse and enable interrupt.
1855 (+) Stop the Timer One Pulse and disable interrupt.
1856 (+) Start the Timer One Pulse and enable DMA transfer.
1857 (+) Stop the Timer One Pulse and disable DMA transfer.
1858
1859 @endverbatim
1860 * @{
1861 */
1862 /**
1863 * @brief Initializes the TIM One Pulse Time Base according to the specified
1864 * parameters in the TIM_HandleTypeDef and create the associated handle.
1865 * @param htim: TIM OnePulse handle
1866 * @param OnePulseMode: Select the One pulse mode.
1867 * This parameter can be one of the following values:
1868 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1869 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
1870 * @retval HAL status
1871 */
1872 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1873 {
1874 /* Check the TIM handle allocation */
1875 if(htim == NULL)
1876 {
1877 return HAL_ERROR;
1878 }
1879
1880 /* Check the parameters */
1881 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1882 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1883 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1884 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1885 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1886 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
1887
1888 if(htim->State == HAL_TIM_STATE_RESET)
1889 {
1890 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1891 HAL_TIM_OnePulse_MspInit(htim);
1892 }
1893
1894 /* Set the TIM state */
1895 htim->State= HAL_TIM_STATE_BUSY;
1896
1897 /* Configure the Time base in the One Pulse Mode */
1898 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1899
1900 /* Reset the OPM Bit */
1901 htim->Instance->CR1 &= ~TIM_CR1_OPM;
1902
1903 /* Configure the OPM Mode */
1904 htim->Instance->CR1 |= OnePulseMode;
1905
1906 /* Initialize the TIM state*/
1907 htim->State= HAL_TIM_STATE_READY;
1908
1909 return HAL_OK;
1910 }
1911
1912 /**
1913 * @brief DeInitializes the TIM One Pulse
1914 * @param htim: TIM One Pulse handle
1915 * @retval HAL status
1916 */
1917 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
1918 {
1919 /* Check the parameters */
1920 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1921
1922 htim->State = HAL_TIM_STATE_BUSY;
1923
1924 /* Disable the TIM Peripheral Clock */
1925 __HAL_TIM_DISABLE(htim);
1926
1927 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
1928 HAL_TIM_OnePulse_MspDeInit(htim);
1929
1930 /* Change TIM state */
1931 htim->State = HAL_TIM_STATE_RESET;
1932
1933 /* Release Lock */
1934 __HAL_UNLOCK(htim);
1935
1936 return HAL_OK;
1937 }
1938
1939 /**
1940 * @brief Initializes the TIM One Pulse MSP.
1941 * @param htim : TIM handle
1942 * @retval None
1943 */
1944 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
1945 {
1946 /* NOTE : This function Should not be modified, when the callback is needed,
1947 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
1948 */
1949 }
1950
1951 /**
1952 * @brief DeInitializes TIM One Pulse MSP.
1953 * @param htim : TIM handle
1954 * @retval None
1955 */
1956 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
1957 {
1958 /* NOTE : This function Should not be modified, when the callback is needed,
1959 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
1960 */
1961 }
1962
1963 /**
1964 * @brief Starts the TIM One Pulse signal generation.
1965 * @param htim : TIM handle
1966 * @param OutputChannel : TIM Channels to be enabled.
1967 * This parameter is not used since both channels TIM_CHANNEL_1 and
1968 * TIM_CHANNEL_2 are automatically selected.
1969 * @retval HAL status
1970 */
1971 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1972 {
1973 /* Enable the Capture compare and the Input Capture channels
1974 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
1975 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
1976 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
1977 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
1978
1979 No need to enable the counter, it's enabled automatically by hardware
1980 (the counter starts in response to a stimulus and generate a pulse */
1981
1982 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
1983 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
1984
1985 /* Return function status */
1986 return HAL_OK;
1987 }
1988
1989 /**
1990 * @brief Stops the TIM One Pulse signal generation.
1991 * @param htim : TIM handle
1992 * @param OutputChannel : TIM Channels to be disable.
1993 * This parameter can be one of the following values:
1994 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1995 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1996 * @retval HAL status
1997 */
1998 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1999 {
2000 /* Disable the Capture compare and the Input Capture channels
2001 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2002 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2003 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2004 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2005
2006 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2007 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2008
2009 /* Disable the Peripheral */
2010 __HAL_TIM_DISABLE(htim);
2011
2012 /* Return function status */
2013 return HAL_OK;
2014 }
2015
2016 /**
2017 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2018 * @param htim : TIM handle
2019 * @param OutputChannel: TIM Channels to be enabled.
2020 * This parameter can be one of the following values:
2021 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2022 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2023 * @retval HAL status
2024 */
2025 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2026 {
2027 /* Enable the Capture compare and the Input Capture channels
2028 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2029 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2030 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2031 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2032
2033 No need to enable the counter, it's enabled automatically by hardware
2034 (the counter starts in response to a stimulus and generate a pulse */
2035
2036 /* Enable the TIM Capture/Compare 1 interrupt */
2037 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2038
2039 /* Enable the TIM Capture/Compare 2 interrupt */
2040 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2041
2042 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2043 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2044
2045 /* Return function status */
2046 return HAL_OK;
2047 }
2048
2049 /**
2050 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2051 * @param htim : TIM handle
2052 * @param OutputChannel: TIM Channels to be enabled.
2053 * This parameter can be one of the following values:
2054 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2055 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2056 * @retval HAL status
2057 */
2058 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2059 {
2060 /* Disable the TIM Capture/Compare 1 interrupt */
2061 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2062
2063 /* Disable the TIM Capture/Compare 2 interrupt */
2064 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2065
2066 /* Disable the Capture compare and the Input Capture channels
2067 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2068 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2069 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2070 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2071 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2072 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2073
2074 /* Disable the Peripheral */
2075 __HAL_TIM_DISABLE(htim);
2076
2077 /* Return function status */
2078 return HAL_OK;
2079 }
2080
2081 /**
2082 * @}
2083 */
2084
2085 /** @addtogroup TIM_Exported_Functions_Group6
2086 * @brief Time Encoder functions
2087 *
2088 @verbatim
2089 ==============================================================================
2090 ##### Timer Encoder functions #####
2091 ==============================================================================
2092 [..]
2093 This section provides functions allowing to:
2094 (+) Initialize and configure the TIM Encoder.
2095 (+) De-initialize the TIM Encoder.
2096 (+) Start the Timer Encoder.
2097 (+) Stop the Timer Encoder.
2098 (+) Start the Timer Encoder and enable interrupt.
2099 (+) Stop the Timer Encoder and disable interrupt.
2100 (+) Start the Timer Encoder and enable DMA transfer.
2101 (+) Stop the Timer Encoder and disable DMA transfer.
2102
2103 @endverbatim
2104 * @{
2105 */
2106 /**
2107 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2108 * @param htim: TIM Encoder Interface handle
2109 * @param sConfig: TIM Encoder Interface configuration structure
2110 * @retval HAL status
2111 */
2112 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2113 {
2114 uint32_t tmpsmcr = 0;
2115 uint32_t tmpccmr1 = 0;
2116 uint32_t tmpccer = 0;
2117
2118 /* Check the TIM handle allocation */
2119 if(htim == NULL)
2120 {
2121 return HAL_ERROR;
2122 }
2123
2124 /* Check the parameters */
2125 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2126 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2127 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2128 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2129 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2130 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2131 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2132 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2133 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2134 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2135 assert_param(IS_TIM_PERIOD(htim->Init.Period));
2136 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
2137
2138 if(htim->State == HAL_TIM_STATE_RESET)
2139 {
2140 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2141 HAL_TIM_Encoder_MspInit(htim);
2142 }
2143
2144 /* Set the TIM state */
2145 htim->State= HAL_TIM_STATE_BUSY;
2146
2147 /* Reset the SMS bits */
2148 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2149
2150 /* Configure the Time base in the Encoder Mode */
2151 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2152
2153 /* Get the TIMx SMCR register value */
2154 tmpsmcr = htim->Instance->SMCR;
2155
2156 /* Get the TIMx CCMR1 register value */
2157 tmpccmr1 = htim->Instance->CCMR1;
2158
2159 /* Get the TIMx CCER register value */
2160 tmpccer = htim->Instance->CCER;
2161
2162 /* Set the encoder Mode */
2163 tmpsmcr |= sConfig->EncoderMode;
2164
2165 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2166 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2167 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
2168
2169 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2170 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2171 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2172 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
2173 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
2174
2175 /* Set the TI1 and the TI2 Polarities */
2176 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2177 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2178 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
2179
2180 /* Write to TIMx SMCR */
2181 htim->Instance->SMCR = tmpsmcr;
2182
2183 /* Write to TIMx CCMR1 */
2184 htim->Instance->CCMR1 = tmpccmr1;
2185
2186 /* Write to TIMx CCER */
2187 htim->Instance->CCER = tmpccer;
2188
2189 /* Initialize the TIM state*/
2190 htim->State= HAL_TIM_STATE_READY;
2191
2192 return HAL_OK;
2193 }
2194
2195 /**
2196 * @brief DeInitializes the TIM Encoder interface
2197 * @param htim: TIM Encoder handle
2198 * @retval HAL status
2199 */
2200 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2201 {
2202 /* Check the parameters */
2203 assert_param(IS_TIM_INSTANCE(htim->Instance));
2204
2205 htim->State = HAL_TIM_STATE_BUSY;
2206
2207 /* Disable the TIM Peripheral Clock */
2208 __HAL_TIM_DISABLE(htim);
2209
2210 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2211 HAL_TIM_Encoder_MspDeInit(htim);
2212
2213 /* Change TIM state */
2214 htim->State = HAL_TIM_STATE_RESET;
2215
2216 /* Release Lock */
2217 __HAL_UNLOCK(htim);
2218
2219 return HAL_OK;
2220 }
2221
2222
2223 /**
2224 * @brief Initializes the TIM Encoder Interface MSP.
2225 * @param htim : TIM handle
2226 * @retval None
2227 */
2228 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2229 {
2230 /* NOTE : This function Should not be modified, when the callback is needed,
2231 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2232 */
2233 }
2234
2235
2236 /**
2237 * @brief DeInitializes TIM Encoder Interface MSP.
2238 * @param htim : TIM handle
2239 * @retval None
2240 */
2241 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2242 {
2243 /* NOTE : This function Should not be modified, when the callback is needed,
2244 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2245 */
2246 }
2247
2248 /**
2249 * @brief Starts the TIM Encoder Interface.
2250 * @param htim : TIM handle
2251 * @param Channel: TIM Channels to be enabled.
2252 * This parameter can be one of the following values:
2253 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2254 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2255 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2256 * @retval HAL status
2257 */
2258 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2259 {
2260 /* Check the parameters */
2261 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2262
2263 /* Enable the encoder interface channels */
2264 switch (Channel)
2265 {
2266 case TIM_CHANNEL_1:
2267 {
2268 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2269 break;
2270 }
2271 case TIM_CHANNEL_2:
2272 {
2273 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2274 break;
2275 }
2276 default :
2277 {
2278 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2279 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2280 break;
2281 }
2282 }
2283 /* Enable the Peripheral */
2284 __HAL_TIM_ENABLE(htim);
2285
2286 /* Return function status */
2287 return HAL_OK;
2288 }
2289
2290 /**
2291 * @brief Stops the TIM Encoder Interface.
2292 * @param htim : TIM handle
2293 * @param Channel: TIM Channels to be disabled.
2294 * This parameter can be one of the following values:
2295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2297 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2298 * @retval HAL status
2299 */
2300 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2301 {
2302 /* Check the parameters */
2303 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2304
2305 /* Disable the Input Capture channels 1 and 2
2306 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2307 switch (Channel)
2308 {
2309 case TIM_CHANNEL_1:
2310 {
2311 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2312 break;
2313 }
2314 case TIM_CHANNEL_2:
2315 {
2316 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2317 break;
2318 }
2319 default :
2320 {
2321 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2322 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2323 break;
2324 }
2325 }
2326 /* Disable the Peripheral */
2327 __HAL_TIM_DISABLE(htim);
2328
2329 /* Return function status */
2330 return HAL_OK;
2331 }
2332
2333 /**
2334 * @brief Starts the TIM Encoder Interface in interrupt mode.
2335 * @param htim : TIM handle
2336 * @param Channel: TIM Channels to be enabled.
2337 * This parameter can be one of the following values:
2338 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2339 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2340 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2341 * @retval HAL status
2342 */
2343 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2344 {
2345 /* Check the parameters */
2346 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2347
2348 /* Enable the encoder interface channels */
2349 /* Enable the capture compare Interrupts 1 and/or 2 */
2350 switch (Channel)
2351 {
2352 case TIM_CHANNEL_1:
2353 {
2354 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2355 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2356 break;
2357 }
2358 case TIM_CHANNEL_2:
2359 {
2360 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2361 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2362 break;
2363 }
2364 default :
2365 {
2366 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2367 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2368 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2369 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2370 break;
2371 }
2372 }
2373
2374 /* Enable the Peripheral */
2375 __HAL_TIM_ENABLE(htim);
2376
2377 /* Return function status */
2378 return HAL_OK;
2379 }
2380
2381 /**
2382 * @brief Stops the TIM Encoder Interface in interrupt mode.
2383 * @param htim : TIM handle
2384 * @param Channel: TIM Channels to be disabled.
2385 * This parameter can be one of the following values:
2386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2388 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2389 * @retval HAL status
2390 */
2391 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2392 {
2393 /* Check the parameters */
2394 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2395
2396 /* Disable the Input Capture channels 1 and 2
2397 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2398 if(Channel == TIM_CHANNEL_1)
2399 {
2400 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2401
2402 /* Disable the capture compare Interrupts 1 */
2403 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2404 }
2405 else if(Channel == TIM_CHANNEL_2)
2406 {
2407 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2408
2409 /* Disable the capture compare Interrupts 2 */
2410 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2411 }
2412 else
2413 {
2414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2416
2417 /* Disable the capture compare Interrupts 1 and 2 */
2418 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2419 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2420 }
2421
2422 /* Disable the Peripheral */
2423 __HAL_TIM_DISABLE(htim);
2424
2425 /* Change the htim state */
2426 htim->State = HAL_TIM_STATE_READY;
2427
2428 /* Return function status */
2429 return HAL_OK;
2430 }
2431
2432 /**
2433 * @brief Starts the TIM Encoder Interface in DMA mode.
2434 * @param htim : TIM handle
2435 * @param Channel: TIM Channels to be enabled.
2436 * This parameter can be one of the following values:
2437 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2438 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2439 * @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected
2440 * @param pData1: The destination Buffer address for IC1.
2441 * @param pData2: The destination Buffer address for IC2.
2442 * @param Length: The length of data to be transferred from TIM peripheral to memory.
2443 * @retval HAL status
2444 */
2445 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2446 {
2447 /* Check the parameters */
2448 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2449
2450 if((htim->State == HAL_TIM_STATE_BUSY))
2451 {
2452 return HAL_BUSY;
2453 }
2454 else if((htim->State == HAL_TIM_STATE_READY))
2455 {
2456 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
2457 {
2458 return HAL_ERROR;
2459 }
2460 else
2461 {
2462 htim->State = HAL_TIM_STATE_BUSY;
2463 }
2464 }
2465
2466 switch (Channel)
2467 {
2468 case TIM_CHANNEL_1:
2469 {
2470 /* Set the DMA Period elapsed callback */
2471 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2472
2473 /* Set the DMA error callback */
2474 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2475
2476 /* Enable the DMA Stream */
2477 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2478
2479 /* Enable the TIM Input Capture DMA request */
2480 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2481
2482 /* Enable the Peripheral */
2483 __HAL_TIM_ENABLE(htim);
2484
2485 /* Enable the Capture compare channel */
2486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2487 }
2488 break;
2489
2490 case TIM_CHANNEL_2:
2491 {
2492 /* Set the DMA Period elapsed callback */
2493 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2494
2495 /* Set the DMA error callback */
2496 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
2497 /* Enable the DMA Stream */
2498 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2499
2500 /* Enable the TIM Input Capture DMA request */
2501 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2502
2503 /* Enable the Peripheral */
2504 __HAL_TIM_ENABLE(htim);
2505
2506 /* Enable the Capture compare channel */
2507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2508 }
2509 break;
2510
2511 case TIM_CHANNEL_ALL:
2512 {
2513 /* Set the DMA Period elapsed callback */
2514 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2515
2516 /* Set the DMA error callback */
2517 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2518
2519 /* Enable the DMA Stream */
2520 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2521
2522 /* Set the DMA Period elapsed callback */
2523 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2524
2525 /* Set the DMA error callback */
2526 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2527
2528 /* Enable the DMA Stream */
2529 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2530
2531 /* Enable the Peripheral */
2532 __HAL_TIM_ENABLE(htim);
2533
2534 /* Enable the Capture compare channel */
2535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2536 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2537
2538 /* Enable the TIM Input Capture DMA request */
2539 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2540 /* Enable the TIM Input Capture DMA request */
2541 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2542 }
2543 break;
2544
2545 default:
2546 break;
2547 }
2548 /* Return function status */
2549 return HAL_OK;
2550 }
2551
2552 /**
2553 * @brief Stops the TIM Encoder Interface in DMA mode.
2554 * @param htim : TIM handle
2555 * @param Channel: TIM Channels to be enabled.
2556 * This parameter can be one of the following values:
2557 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2558 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2559 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2560 * @retval HAL status
2561 */
2562 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2563 {
2564 /* Check the parameters */
2565 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2566
2567 /* Disable the Input Capture channels 1 and 2
2568 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2569 if(Channel == TIM_CHANNEL_1)
2570 {
2571 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2572
2573 /* Disable the capture compare DMA Request 1 */
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2575 }
2576 else if(Channel == TIM_CHANNEL_2)
2577 {
2578 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2579
2580 /* Disable the capture compare DMA Request 2 */
2581 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2582 }
2583 else
2584 {
2585 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2586 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2587
2588 /* Disable the capture compare DMA Request 1 and 2 */
2589 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2590 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2591 }
2592
2593 /* Disable the Peripheral */
2594 __HAL_TIM_DISABLE(htim);
2595
2596 /* Change the htim state */
2597 htim->State = HAL_TIM_STATE_READY;
2598
2599 /* Return function status */
2600 return HAL_OK;
2601 }
2602
2603 /**
2604 * @}
2605 */
2606
2607 /** @addtogroup TIM_Exported_Functions_Group7
2608 * @brief IRQ handler management
2609 *
2610 @verbatim
2611 ==============================================================================
2612 ##### IRQ handler management #####
2613 ==============================================================================
2614 [..]
2615 This section provides Timer IRQ handler function.
2616
2617 @endverbatim
2618 * @{
2619 */
2620 /**
2621 * @brief This function handles TIM interrupts requests.
2622 * @param htim: TIM handle
2623 * @retval None
2624 */
2625 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2626 {
2627 /* Capture compare 1 event */
2628 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2629 {
2630 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
2631 {
2632 {
2633 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2634 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2635
2636 /* Input capture event */
2637 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
2638 {
2639 HAL_TIM_IC_CaptureCallback(htim);
2640 }
2641 /* Output compare event */
2642 else
2643 {
2644 HAL_TIM_OC_DelayElapsedCallback(htim);
2645 HAL_TIM_PWM_PulseFinishedCallback(htim);
2646 }
2647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2648 }
2649 }
2650 }
2651 /* Capture compare 2 event */
2652 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2653 {
2654 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
2655 {
2656 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2657 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2658 /* Input capture event */
2659 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
2660 {
2661 HAL_TIM_IC_CaptureCallback(htim);
2662 }
2663 /* Output compare event */
2664 else
2665 {
2666 HAL_TIM_OC_DelayElapsedCallback(htim);
2667 HAL_TIM_PWM_PulseFinishedCallback(htim);
2668 }
2669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2670 }
2671 }
2672 /* Capture compare 3 event */
2673 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2674 {
2675 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
2676 {
2677 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2678 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2679 /* Input capture event */
2680 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
2681 {
2682 HAL_TIM_IC_CaptureCallback(htim);
2683 }
2684 /* Output compare event */
2685 else
2686 {
2687 HAL_TIM_OC_DelayElapsedCallback(htim);
2688 HAL_TIM_PWM_PulseFinishedCallback(htim);
2689 }
2690 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2691 }
2692 }
2693 /* Capture compare 4 event */
2694 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2695 {
2696 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
2697 {
2698 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2699 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2700 /* Input capture event */
2701 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
2702 {
2703 HAL_TIM_IC_CaptureCallback(htim);
2704 }
2705 /* Output compare event */
2706 else
2707 {
2708 HAL_TIM_OC_DelayElapsedCallback(htim);
2709 HAL_TIM_PWM_PulseFinishedCallback(htim);
2710 }
2711 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2712 }
2713 }
2714 /* TIM Update event */
2715 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2716 {
2717 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
2718 {
2719 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2720 HAL_TIM_PeriodElapsedCallback(htim);
2721 }
2722 }
2723 /* TIM Trigger detection event */
2724 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2725 {
2726 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
2727 {
2728 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2729 HAL_TIM_TriggerCallback(htim);
2730 }
2731 }
2732 }
2733
2734 /**
2735 * @}
2736 */
2737
2738 /** @addtogroup TIM_Exported_Functions_Group8
2739 * @brief Peripheral Control functions
2740 *
2741 @verbatim
2742 ==============================================================================
2743 ##### Peripheral Control functions #####
2744 ==============================================================================
2745 [..]
2746 This section provides functions allowing to:
2747 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2748 (+) Configure External Clock source.
2749 (+) Configure Master and the Slave synchronization.
2750 (+) Configure the DMA Burst Mode.
2751
2752 @endverbatim
2753 * @{
2754 */
2755 /**
2756 * @brief Initializes the TIM Output Compare Channels according to the specified
2757 * parameters in the TIM_OC_InitTypeDef.
2758 * @param htim : TIM handle
2759 * @param sConfig: TIM Output Compare configuration structure
2760 * @param Channel: TIM Channels to be enabled.
2761 * This parameter can be one of the following values:
2762 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2763 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2764 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2765 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2766 * @retval HAL status
2767 */
2768 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2769 {
2770 /* Check the parameters */
2771 assert_param(IS_TIM_CHANNELS(Channel));
2772 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2773 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2774
2775 /* Check input state */
2776 __HAL_LOCK(htim);
2777
2778 htim->State = HAL_TIM_STATE_BUSY;
2779
2780 switch (Channel)
2781 {
2782 case TIM_CHANNEL_1:
2783 {
2784 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2785 /* Configure the TIM Channel 1 in Output Compare */
2786 TIM_OC1_SetConfig(htim->Instance, sConfig);
2787 }
2788 break;
2789
2790 case TIM_CHANNEL_2:
2791 {
2792 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2793 /* Configure the TIM Channel 2 in Output Compare */
2794 TIM_OC2_SetConfig(htim->Instance, sConfig);
2795 }
2796 break;
2797
2798 case TIM_CHANNEL_3:
2799 {
2800 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2801 /* Configure the TIM Channel 3 in Output Compare */
2802 TIM_OC3_SetConfig(htim->Instance, sConfig);
2803 }
2804 break;
2805
2806 case TIM_CHANNEL_4:
2807 {
2808 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2809 /* Configure the TIM Channel 4 in Output Compare */
2810 TIM_OC4_SetConfig(htim->Instance, sConfig);
2811 }
2812 break;
2813
2814 default:
2815 break;
2816 }
2817 htim->State = HAL_TIM_STATE_READY;
2818
2819 __HAL_UNLOCK(htim);
2820
2821 return HAL_OK;
2822 }
2823
2824 /**
2825 * @brief Initializes the TIM Input Capture Channels according to the specified
2826 * parameters in the TIM_IC_InitTypeDef.
2827 * @param htim : TIM handle
2828 * @param sConfig: TIM Input Capture configuration structure
2829 * @param Channel: TIM Channels to be enabled.
2830 * This parameter can be one of the following values:
2831 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2832 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2833 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2834 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2835 * @retval HAL status
2836 */
2837 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
2838 {
2839 /* Check the parameters */
2840 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2841 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
2842 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
2843 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
2844 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
2845
2846 __HAL_LOCK(htim);
2847
2848 htim->State = HAL_TIM_STATE_BUSY;
2849
2850 if (Channel == TIM_CHANNEL_1)
2851 {
2852 /* TI1 Configuration */
2853 TIM_TI1_SetConfig(htim->Instance,
2854 sConfig->ICPolarity,
2855 sConfig->ICSelection,
2856 sConfig->ICFilter);
2857
2858 /* Reset the IC1PSC Bits */
2859 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
2860
2861 /* Set the IC1PSC value */
2862 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
2863 }
2864 else if (Channel == TIM_CHANNEL_2)
2865 {
2866 /* TI2 Configuration */
2867 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2868
2869 TIM_TI2_SetConfig(htim->Instance,
2870 sConfig->ICPolarity,
2871 sConfig->ICSelection,
2872 sConfig->ICFilter);
2873
2874 /* Reset the IC2PSC Bits */
2875 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
2876
2877 /* Set the IC2PSC value */
2878 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
2879 }
2880 else if (Channel == TIM_CHANNEL_3)
2881 {
2882 /* TI3 Configuration */
2883 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2884
2885 TIM_TI3_SetConfig(htim->Instance,
2886 sConfig->ICPolarity,
2887 sConfig->ICSelection,
2888 sConfig->ICFilter);
2889
2890 /* Reset the IC3PSC Bits */
2891 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
2892
2893 /* Set the IC3PSC value */
2894 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
2895 }
2896 else
2897 {
2898 /* TI4 Configuration */
2899 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2900
2901 TIM_TI4_SetConfig(htim->Instance,
2902 sConfig->ICPolarity,
2903 sConfig->ICSelection,
2904 sConfig->ICFilter);
2905
2906 /* Reset the IC4PSC Bits */
2907 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
2908
2909 /* Set the IC4PSC value */
2910 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
2911 }
2912
2913 htim->State = HAL_TIM_STATE_READY;
2914
2915 __HAL_UNLOCK(htim);
2916
2917 return HAL_OK;
2918 }
2919
2920 /**
2921 * @brief Initializes the TIM PWM channels according to the specified
2922 * parameters in the TIM_OC_InitTypeDef.
2923 * @param htim : TIM handle
2924 * @param sConfig: TIM PWM configuration structure
2925 * @param Channel: TIM Channels to be enabled.
2926 * This parameter can be one of the following values:
2927 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2928 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2929 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2930 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2931 * @retval HAL status
2932 */
2933 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2934 {
2935 __HAL_LOCK(htim);
2936
2937 /* Check the parameters */
2938 assert_param(IS_TIM_CHANNELS(Channel));
2939 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
2940 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2941 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
2942
2943 htim->State = HAL_TIM_STATE_BUSY;
2944
2945 switch (Channel)
2946 {
2947 case TIM_CHANNEL_1:
2948 {
2949 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2950 /* Configure the Channel 1 in PWM mode */
2951 TIM_OC1_SetConfig(htim->Instance, sConfig);
2952
2953 /* Set the Preload enable bit for channel1 */
2954 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
2955
2956 /* Configure the Output Fast mode */
2957 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
2958 htim->Instance->CCMR1 |= sConfig->OCFastMode;
2959 }
2960 break;
2961
2962 case TIM_CHANNEL_2:
2963 {
2964 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2965 /* Configure the Channel 2 in PWM mode */
2966 TIM_OC2_SetConfig(htim->Instance, sConfig);
2967
2968 /* Set the Preload enable bit for channel2 */
2969 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
2970
2971 /* Configure the Output Fast mode */
2972 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
2973 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
2974 }
2975 break;
2976
2977 case TIM_CHANNEL_3:
2978 {
2979 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2980 /* Configure the Channel 3 in PWM mode */
2981 TIM_OC3_SetConfig(htim->Instance, sConfig);
2982
2983 /* Set the Preload enable bit for channel3 */
2984 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
2985
2986 /* Configure the Output Fast mode */
2987 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
2988 htim->Instance->CCMR2 |= sConfig->OCFastMode;
2989 }
2990 break;
2991
2992 case TIM_CHANNEL_4:
2993 {
2994 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2995 /* Configure the Channel 4 in PWM mode */
2996 TIM_OC4_SetConfig(htim->Instance, sConfig);
2997
2998 /* Set the Preload enable bit for channel4 */
2999 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3000
3001 /* Configure the Output Fast mode */
3002 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3003 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
3004 }
3005 break;
3006
3007 default:
3008 break;
3009 }
3010
3011 htim->State = HAL_TIM_STATE_READY;
3012
3013 __HAL_UNLOCK(htim);
3014
3015 return HAL_OK;
3016 }
3017
3018 /**
3019 * @brief Initializes the TIM One Pulse Channels according to the specified
3020 * parameters in the TIM_OnePulse_InitTypeDef.
3021 * @param htim : TIM handle
3022 * @param sConfig: TIM One Pulse configuration structure
3023 * @param OutputChannel: TIM Channels to be enabled.
3024 * This parameter can be one of the following values:
3025 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3026 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3027 * @param InputChannel: TIM Channels to be enabled.
3028 * This parameter can be one of the following values:
3029 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3030 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3031 * @retval HAL status
3032 */
3033 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3034 {
3035 TIM_OC_InitTypeDef temp1;
3036
3037 /* Check the parameters */
3038 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3039 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3040
3041 if(OutputChannel != InputChannel)
3042 {
3043 __HAL_LOCK(htim);
3044
3045 htim->State = HAL_TIM_STATE_BUSY;
3046
3047 /* Extract the Ouput compare configuration from sConfig structure */
3048 temp1.OCMode = sConfig->OCMode;
3049 temp1.Pulse = sConfig->Pulse;
3050 temp1.OCPolarity = sConfig->OCPolarity;
3051
3052 switch (OutputChannel)
3053 {
3054 case TIM_CHANNEL_1:
3055 {
3056 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3057
3058 TIM_OC1_SetConfig(htim->Instance, &temp1);
3059 }
3060 break;
3061 case TIM_CHANNEL_2:
3062 {
3063 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3064
3065 TIM_OC2_SetConfig(htim->Instance, &temp1);
3066 }
3067 break;
3068 default:
3069 break;
3070 }
3071 switch (InputChannel)
3072 {
3073 case TIM_CHANNEL_1:
3074 {
3075 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3076
3077 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3078 sConfig->ICSelection, sConfig->ICFilter);
3079
3080 /* Reset the IC1PSC Bits */
3081 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3082
3083 /* Select the Trigger source */
3084 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3085 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3086
3087 /* Select the Slave Mode */
3088 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3089 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3090 }
3091 break;
3092 case TIM_CHANNEL_2:
3093 {
3094 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3095
3096 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3097 sConfig->ICSelection, sConfig->ICFilter);
3098
3099 /* Reset the IC2PSC Bits */
3100 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3101
3102 /* Select the Trigger source */
3103 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3104 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3105
3106 /* Select the Slave Mode */
3107 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3108 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3109 }
3110 break;
3111
3112 default:
3113 break;
3114 }
3115
3116 htim->State = HAL_TIM_STATE_READY;
3117
3118 __HAL_UNLOCK(htim);
3119
3120 return HAL_OK;
3121 }
3122 else
3123 {
3124 return HAL_ERROR;
3125 }
3126 }
3127
3128 /**
3129 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3130 * @param htim : TIM handle
3131 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
3132 * This parameters can be on of the following values:
3133 * @arg TIM_DMABASE_CR1
3134 * @arg TIM_DMABASE_CR2
3135 * @arg TIM_DMABASE_SMCR
3136 * @arg TIM_DMABASE_DIER
3137 * @arg TIM_DMABASE_SR
3138 * @arg TIM_DMABASE_EGR
3139 * @arg TIM_DMABASE_CCMR1
3140 * @arg TIM_DMABASE_CCMR2
3141 * @arg TIM_DMABASE_CCER
3142 * @arg TIM_DMABASE_CNT
3143 * @arg TIM_DMABASE_PSC
3144 * @arg TIM_DMABASE_ARR
3145 * @arg TIM_DMABASE_CCR1
3146 * @arg TIM_DMABASE_CCR2
3147 * @arg TIM_DMABASE_CCR3
3148 * @arg TIM_DMABASE_CCR4
3149 * @arg TIM_DMABASE_DCR
3150 * @param BurstRequestSrc: TIM DMA Request sources.
3151 * This parameters can be on of the following values:
3152 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3153 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3154 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3155 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3156 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3157 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3158 * @param BurstBuffer: The Buffer address.
3159 * @param BurstLength: DMA Burst length. This parameter can be one value
3160 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
3161 * @retval HAL status
3162 */
3163 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3164 uint32_t* BurstBuffer, uint32_t BurstLength)
3165 {
3166 /* Check the parameters */
3167 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3168 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3169 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3170 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3171
3172 if((htim->State == HAL_TIM_STATE_BUSY))
3173 {
3174 return HAL_BUSY;
3175 }
3176 else if((htim->State == HAL_TIM_STATE_READY))
3177 {
3178 if((BurstBuffer == 0 ) && (BurstLength > 0))
3179 {
3180 return HAL_ERROR;
3181 }
3182 else
3183 {
3184 htim->State = HAL_TIM_STATE_BUSY;
3185 }
3186 }
3187 switch(BurstRequestSrc)
3188 {
3189 case TIM_DMA_UPDATE:
3190 {
3191 /* Set the DMA Period elapsed callback */
3192 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3193
3194 /* Set the DMA error callback */
3195 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3196
3197 /* Enable the DMA Stream */
3198 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3199 }
3200 break;
3201 case TIM_DMA_CC1:
3202 {
3203 /* Set the DMA Period elapsed callback */
3204 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3205
3206 /* Set the DMA error callback */
3207 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3208
3209 /* Enable the DMA Stream */
3210 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3211 }
3212 break;
3213 case TIM_DMA_CC2:
3214 {
3215 /* Set the DMA Period elapsed callback */
3216 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3217
3218 /* Set the DMA error callback */
3219 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3220
3221 /* Enable the DMA Stream */
3222 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3223 }
3224 break;
3225 case TIM_DMA_CC3:
3226 {
3227 /* Set the DMA Period elapsed callback */
3228 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3229
3230 /* Set the DMA error callback */
3231 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3232
3233 /* Enable the DMA Stream */
3234 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3235 }
3236 break;
3237 case TIM_DMA_CC4:
3238 {
3239 /* Set the DMA Period elapsed callback */
3240 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
3241
3242 /* Set the DMA error callback */
3243 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3244
3245 /* Enable the DMA Stream */
3246 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3247 }
3248 break;
3249 case TIM_DMA_TRIGGER:
3250 {
3251 /* Set the DMA Period elapsed callback */
3252 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3253
3254 /* Set the DMA error callback */
3255 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3256
3257 /* Enable the DMA Stream */
3258 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3259 }
3260 break;
3261 default:
3262 break;
3263 }
3264 /* configure the DMA Burst Mode */
3265 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3266
3267 /* Enable the TIM DMA Request */
3268 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3269
3270 htim->State = HAL_TIM_STATE_READY;
3271
3272 /* Return function status */
3273 return HAL_OK;
3274 }
3275
3276 /**
3277 * @brief Stops the TIM DMA Burst mode
3278 * @param htim : TIM handle
3279 * @param BurstRequestSrc: TIM DMA Request sources to disable
3280 * @retval HAL status
3281 */
3282 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3283 {
3284 /* Check the parameters */
3285 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3286
3287 /* Abort the DMA transfer (at least disable the DMA channel) */
3288 switch(BurstRequestSrc)
3289 {
3290 case TIM_DMA_UPDATE:
3291 {
3292 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3293 }
3294 break;
3295 case TIM_DMA_CC1:
3296 {
3297 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3298 }
3299 break;
3300 case TIM_DMA_CC2:
3301 {
3302 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3303 }
3304 break;
3305 case TIM_DMA_CC3:
3306 {
3307 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3308 }
3309 break;
3310 case TIM_DMA_CC4:
3311 {
3312 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3313 }
3314 break;
3315 case TIM_DMA_TRIGGER:
3316 {
3317 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3318 }
3319 break;
3320 default:
3321 break;
3322 }
3323 /* Disable the TIM Update DMA request */
3324 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3325
3326 /* Return function status */
3327 return HAL_OK;
3328 }
3329
3330 /**
3331 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3332 * @param htim : TIM handle
3333 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
3334 * This parameters can be on of the following values:
3335 * @arg TIM_DMABASE_CR1
3336 * @arg TIM_DMABASE_CR2
3337 * @arg TIM_DMABASE_SMCR
3338 * @arg TIM_DMABASE_DIER
3339 * @arg TIM_DMABASE_SR
3340 * @arg TIM_DMABASE_EGR
3341 * @arg TIM_DMABASE_CCMR1
3342 * @arg TIM_DMABASE_CCMR2
3343 * @arg TIM_DMABASE_CCER
3344 * @arg TIM_DMABASE_CNT
3345 * @arg TIM_DMABASE_PSC
3346 * @arg TIM_DMABASE_ARR
3347 * @arg TIM_DMABASE_CCR1
3348 * @arg TIM_DMABASE_CCR2
3349 * @arg TIM_DMABASE_CCR3
3350 * @arg TIM_DMABASE_CCR4
3351 * @arg TIM_DMABASE_DCR
3352 * @param BurstRequestSrc: TIM DMA Request sources.
3353 * This parameters can be on of the following values:
3354 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3355 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3356 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3357 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3358 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3359 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3360 * @param BurstBuffer: The Buffer address.
3361 * @param BurstLength: DMA Burst length. This parameter can be one value
3362 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
3363 * @retval HAL status
3364 */
3365 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3366 uint32_t *BurstBuffer, uint32_t BurstLength)
3367 {
3368 /* Check the parameters */
3369 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3370 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3371 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3372 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3373
3374 if((htim->State == HAL_TIM_STATE_BUSY))
3375 {
3376 return HAL_BUSY;
3377 }
3378 else if((htim->State == HAL_TIM_STATE_READY))
3379 {
3380 if((BurstBuffer == 0 ) && (BurstLength > 0))
3381 {
3382 return HAL_ERROR;
3383 }
3384 else
3385 {
3386 htim->State = HAL_TIM_STATE_BUSY;
3387 }
3388 }
3389 switch(BurstRequestSrc)
3390 {
3391 case TIM_DMA_UPDATE:
3392 {
3393 /* Set the DMA Period elapsed callback */
3394 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3395
3396 /* Set the DMA error callback */
3397 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3398
3399 /* Enable the DMA Stream */
3400 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3401 }
3402 break;
3403 case TIM_DMA_CC1:
3404 {
3405 /* Set the DMA Period elapsed callback */
3406 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3407
3408 /* Set the DMA error callback */
3409 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3410
3411 /* Enable the DMA Stream */
3412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3413 }
3414 break;
3415 case TIM_DMA_CC2:
3416 {
3417 /* Set the DMA Period elapsed callback */
3418 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3419
3420 /* Set the DMA error callback */
3421 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3422
3423 /* Enable the DMA Stream */
3424 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3425 }
3426 break;
3427 case TIM_DMA_CC3:
3428 {
3429 /* Set the DMA Period elapsed callback */
3430 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
3431
3432 /* Set the DMA error callback */
3433 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3434
3435 /* Enable the DMA Stream */
3436 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3437 }
3438 break;
3439 case TIM_DMA_CC4:
3440 {
3441 /* Set the DMA Period elapsed callback */
3442 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
3443
3444 /* Set the DMA error callback */
3445 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3446
3447 /* Enable the DMA Stream */
3448 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3449 }
3450 break;
3451 case TIM_DMA_TRIGGER:
3452 {
3453 /* Set the DMA Period elapsed callback */
3454 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3455
3456 /* Set the DMA error callback */
3457 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3458
3459 /* Enable the DMA Stream */
3460 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3461 }
3462 break;
3463 default:
3464 break;
3465 }
3466
3467 /* configure the DMA Burst Mode */
3468 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3469
3470 /* Enable the TIM DMA Request */
3471 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3472
3473 htim->State = HAL_TIM_STATE_READY;
3474
3475 /* Return function status */
3476 return HAL_OK;
3477 }
3478
3479 /**
3480 * @brief Stop the DMA burst reading
3481 * @param htim : TIM handle
3482 * @param BurstRequestSrc: TIM DMA Request sources to disable.
3483 * @retval HAL status
3484 */
3485 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3486 {
3487 /* Check the parameters */
3488 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3489
3490 /* Abort the DMA transfer (at least disable the DMA channel) */
3491 switch(BurstRequestSrc)
3492 {
3493 case TIM_DMA_UPDATE:
3494 {
3495 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3496 }
3497 break;
3498 case TIM_DMA_CC1:
3499 {
3500 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3501 }
3502 break;
3503 case TIM_DMA_CC2:
3504 {
3505 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3506 }
3507 break;
3508 case TIM_DMA_CC3:
3509 {
3510 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3511 }
3512 break;
3513 case TIM_DMA_CC4:
3514 {
3515 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3516 }
3517 break;
3518 case TIM_DMA_TRIGGER:
3519 {
3520 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3521 }
3522 break;
3523 default:
3524 break;
3525 }
3526
3527 /* Disable the TIM Update DMA request */
3528 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3529
3530 /* Return function status */
3531 return HAL_OK;
3532 }
3533
3534 /**
3535 * @brief Generate a software event
3536 * @param htim : TIM handle
3537 * @param EventSource: specifies the event source.
3538 * This parameter can be one of the following values:
3539 * @arg TIM_EventSource_Update: Timer update Event source
3540 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3541 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
3542 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
3543 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
3544 * @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source
3545 * @note TIM6 can only generate an update event.
3546 * @retval HAL status
3547 */
3548
3549 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3550 {
3551 /* Check the parameters */
3552 assert_param(IS_TIM_INSTANCE(htim->Instance));
3553 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3554
3555 /* Process Locked */
3556 __HAL_LOCK(htim);
3557
3558 /* Change the TIM state */
3559 htim->State = HAL_TIM_STATE_BUSY;
3560
3561 /* Set the event sources */
3562 htim->Instance->EGR = EventSource;
3563
3564 /* Change the TIM state */
3565 htim->State = HAL_TIM_STATE_READY;
3566
3567 __HAL_UNLOCK(htim);
3568
3569 /* Return function status */
3570 return HAL_OK;
3571 }
3572
3573 /**
3574 * @brief Configures the OCRef clear feature
3575 * @param htim : TIM handle
3576 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
3577 * contains the OCREF clear feature and parameters for the TIM peripheral.
3578 * @param Channel: specifies the TIM Channel.
3579 * This parameter can be one of the following values:
3580 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3581 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3582 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3583 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3584 * @retval HAL status
3585 */
3586 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3587 {
3588 /* Check the parameters */
3589 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3590 assert_param(IS_TIM_CHANNELS(Channel));
3591 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3592 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3593 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3594 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3595
3596 /* Process Locked */
3597 __HAL_LOCK(htim);
3598
3599 htim->State = HAL_TIM_STATE_BUSY;
3600
3601 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
3602 {
3603 TIM_ETR_SetConfig(htim->Instance,
3604 sClearInputConfig->ClearInputPrescaler,
3605 sClearInputConfig->ClearInputPolarity,
3606 sClearInputConfig->ClearInputFilter);
3607 }
3608
3609 switch (Channel)
3610 {
3611 case TIM_CHANNEL_1:
3612 {
3613 if(sClearInputConfig->ClearInputState != RESET)
3614 {
3615 /* Enable the Ocref clear feature for Channel 1 */
3616 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3617 }
3618 else
3619 {
3620 /* Disable the Ocref clear feature for Channel 1 */
3621 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3622 }
3623 }
3624 break;
3625 case TIM_CHANNEL_2:
3626 {
3627 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3628 if(sClearInputConfig->ClearInputState != RESET)
3629 {
3630 /* Enable the Ocref clear feature for Channel 2 */
3631 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3632 }
3633 else
3634 {
3635 /* Disable the Ocref clear feature for Channel 2 */
3636 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3637 }
3638 }
3639 break;
3640 case TIM_CHANNEL_3:
3641 {
3642 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3643 if(sClearInputConfig->ClearInputState != RESET)
3644 {
3645 /* Enable the Ocref clear feature for Channel 3 */
3646 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3647 }
3648 else
3649 {
3650 /* Disable the Ocref clear feature for Channel 3 */
3651 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3652 }
3653 }
3654 break;
3655 case TIM_CHANNEL_4:
3656 {
3657 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3658 if(sClearInputConfig->ClearInputState != RESET)
3659 {
3660 /* Enable the Ocref clear feature for Channel 4 */
3661 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3662 }
3663 else
3664 {
3665 /* Disable the Ocref clear feature for Channel 4 */
3666 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3667 }
3668 }
3669 break;
3670 default:
3671 break;
3672 }
3673
3674 htim->State = HAL_TIM_STATE_READY;
3675
3676 __HAL_UNLOCK(htim);
3677
3678 return HAL_OK;
3679 }
3680
3681 /**
3682 * @brief Configures the clock source to be used
3683 * @param htim : TIM handle
3684 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
3685 * contains the clock source information for the TIM peripheral.
3686 * @retval HAL status
3687 */
3688 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3689 {
3690 uint32_t tmpsmcr = 0;
3691
3692 /* Process Locked */
3693 __HAL_LOCK(htim);
3694
3695 htim->State = HAL_TIM_STATE_BUSY;
3696
3697 /* Check the parameters */
3698 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3699 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3700 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3701 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3702
3703 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3704 tmpsmcr = htim->Instance->SMCR;
3705 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3706 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3707 htim->Instance->SMCR = tmpsmcr;
3708
3709 switch (sClockSourceConfig->ClockSource)
3710 {
3711 case TIM_CLOCKSOURCE_INTERNAL:
3712 {
3713 assert_param(IS_TIM_INSTANCE(htim->Instance));
3714 /* Disable slave mode to clock the prescaler directly with the internal clock */
3715 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3716 }
3717 break;
3718
3719 case TIM_CLOCKSOURCE_ETRMODE1:
3720 {
3721 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
3722 /* Configure the ETR Clock source */
3723 TIM_ETR_SetConfig(htim->Instance,
3724 sClockSourceConfig->ClockPrescaler,
3725 sClockSourceConfig->ClockPolarity,
3726 sClockSourceConfig->ClockFilter);
3727 /* Get the TIMx SMCR register value */
3728 tmpsmcr = htim->Instance->SMCR;
3729 /* Reset the SMS and TS Bits */
3730 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3731 /* Select the External clock mode1 and the ETRF trigger */
3732 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3733 /* Write to TIMx SMCR */
3734 htim->Instance->SMCR = tmpsmcr;
3735 }
3736 break;
3737
3738 case TIM_CLOCKSOURCE_ETRMODE2:
3739 {
3740 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
3741 /* Configure the ETR Clock source */
3742 TIM_ETR_SetConfig(htim->Instance,
3743 sClockSourceConfig->ClockPrescaler,
3744 sClockSourceConfig->ClockPolarity,
3745 sClockSourceConfig->ClockFilter);
3746 /* Enable the External clock mode2 */
3747 htim->Instance->SMCR |= TIM_SMCR_ECE;
3748 }
3749 break;
3750
3751 case TIM_CLOCKSOURCE_TI1:
3752 {
3753 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3754 TIM_TI1_ConfigInputStage(htim->Instance,
3755 sClockSourceConfig->ClockPolarity,
3756 sClockSourceConfig->ClockFilter);
3757 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
3758 }
3759 break;
3760 case TIM_CLOCKSOURCE_TI2:
3761 {
3762 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3763 TIM_TI2_ConfigInputStage(htim->Instance,
3764 sClockSourceConfig->ClockPolarity,
3765 sClockSourceConfig->ClockFilter);
3766 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
3767 }
3768 break;
3769 case TIM_CLOCKSOURCE_TI1ED:
3770 {
3771 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3772 TIM_TI1_ConfigInputStage(htim->Instance,
3773 sClockSourceConfig->ClockPolarity,
3774 sClockSourceConfig->ClockFilter);
3775 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
3776 }
3777 break;
3778 case TIM_CLOCKSOURCE_ITR0:
3779 {
3780 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3781 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
3782 }
3783 break;
3784 case TIM_CLOCKSOURCE_ITR1:
3785 {
3786 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3787 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
3788 }
3789 break;
3790 case TIM_CLOCKSOURCE_ITR2:
3791 {
3792 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3793 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
3794 }
3795 break;
3796 case TIM_CLOCKSOURCE_ITR3:
3797 {
3798 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3799 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
3800 }
3801 break;
3802
3803 default:
3804 break;
3805 }
3806 htim->State = HAL_TIM_STATE_READY;
3807
3808 __HAL_UNLOCK(htim);
3809
3810 return HAL_OK;
3811 }
3812
3813 /**
3814 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
3815 * or a XOR combination between CH1_input, CH2_input & CH3_input
3816 * @param htim : TIM handle
3817 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
3818 * output of a XOR gate.
3819 * This parameter can be one of the following values:
3820 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
3821 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
3822 * pins are connected to the TI1 input (XOR combination)
3823 * @retval HAL status
3824 */
3825 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
3826 {
3827 uint32_t tmpcr2 = 0;
3828
3829 /* Check the parameters */
3830 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
3831 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
3832
3833 /* Get the TIMx CR2 register value */
3834 tmpcr2 = htim->Instance->CR2;
3835
3836 /* Reset the TI1 selection */
3837 tmpcr2 &= ~TIM_CR2_TI1S;
3838
3839 /* Set the the TI1 selection */
3840 tmpcr2 |= TI1_Selection;
3841
3842 /* Write to TIMxCR2 */
3843 htim->Instance->CR2 = tmpcr2;
3844
3845 return HAL_OK;
3846 }
3847
3848 /**
3849 * @brief Configures the TIM in Slave mode
3850 * @param htim : TIM handle
3851 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
3852 * contains the selected trigger (internal trigger input, filtered
3853 * timer input or external trigger input) and the ) and the Slave
3854 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
3855 * @retval HAL status
3856 */
3857 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
3858 {
3859 /* Check the parameters */
3860 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3861 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
3862 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
3863
3864 __HAL_LOCK(htim);
3865
3866 htim->State = HAL_TIM_STATE_BUSY;
3867
3868 /* Configuration in slave mode */
3869 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
3870
3871 /* Disable Trigger Interrupt */
3872 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
3873
3874 /* Disable Trigger DMA request */
3875 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
3876
3877 /* Set the new state */
3878 htim->State = HAL_TIM_STATE_READY;
3879
3880 __HAL_UNLOCK(htim);
3881
3882 return HAL_OK;
3883 }
3884
3885 /**
3886 * @brief Configures the TIM in Slave mode in interrupt mode
3887 * @param htim : TIM handle.
3888 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
3889 * contains the selected trigger (internal trigger input, filtered
3890 * timer input or external trigger input) and the ) and the Slave
3891 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
3892 * @retval HAL status
3893 */
3894 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
3895 TIM_SlaveConfigTypeDef * sSlaveConfig)
3896 {
3897 /* Check the parameters */
3898 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3899 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
3900 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
3901
3902 __HAL_LOCK(htim);
3903
3904 htim->State = HAL_TIM_STATE_BUSY;
3905
3906 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
3907
3908 /* Enable Trigger Interrupt */
3909 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
3910
3911 /* Disable Trigger DMA request */
3912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
3913
3914 htim->State = HAL_TIM_STATE_READY;
3915
3916 __HAL_UNLOCK(htim);
3917
3918 return HAL_OK;
3919 }
3920
3921 /**
3922 * @brief Read the captured value from Capture Compare unit
3923 * @param htim : TIM handle
3924 * @param Channel: TIM Channels to be enabled.
3925 * This parameter can be one of the following values:
3926 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3927 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3928 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3929 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3930 * @retval Captured value
3931 */
3932 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
3933 {
3934 uint32_t tmpreg = 0;
3935
3936 __HAL_LOCK(htim);
3937
3938 switch (Channel)
3939 {
3940 case TIM_CHANNEL_1:
3941 {
3942 /* Check the parameters */
3943 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3944
3945 /* Return the capture 1 value */
3946 tmpreg = htim->Instance->CCR1;
3947
3948 break;
3949 }
3950 case TIM_CHANNEL_2:
3951 {
3952 /* Check the parameters */
3953 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3954
3955 /* Return the capture 2 value */
3956 tmpreg = htim->Instance->CCR2;
3957
3958 break;
3959 }
3960
3961 case TIM_CHANNEL_3:
3962 {
3963 /* Check the parameters */
3964 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3965
3966 /* Return the capture 3 value */
3967 tmpreg = htim->Instance->CCR3;
3968
3969 break;
3970 }
3971
3972 case TIM_CHANNEL_4:
3973 {
3974 /* Check the parameters */
3975 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3976
3977 /* Return the capture 4 value */
3978 tmpreg = htim->Instance->CCR4;
3979
3980 break;
3981 }
3982
3983 default:
3984 break;
3985 }
3986
3987 __HAL_UNLOCK(htim);
3988 return tmpreg;
3989 }
3990
3991 /**
3992 * @}
3993 */
3994
3995 /** @addtogroup TIM_Exported_Functions_Group9
3996 * @brief TIM Callbacks functions
3997 *
3998 @verbatim
3999 ==============================================================================
4000 ##### TIM Callbacks functions #####
4001 ==============================================================================
4002 [..]
4003 This section provides TIM callback functions:
4004 (+) Timer Period elapsed callback
4005 (+) Timer Output Compare callback
4006 (+) Timer Input capture callback
4007 (+) Timer Trigger callback
4008 (+) Timer Error callback
4009
4010 @endverbatim
4011 * @{
4012 */
4013
4014 /**
4015 * @brief Period elapsed callback in non blocking mode
4016 * @param htim : TIM handle
4017 * @retval None
4018 */
4019 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4020 {
4021 /* NOTE : This function Should not be modified, when the callback is needed,
4022 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4023 */
4024
4025 }
4026 /**
4027 * @brief Output Compare callback in non blocking mode
4028 * @param htim : TIM handle
4029 * @retval None
4030 */
4031 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4032 {
4033 /* NOTE : This function Should not be modified, when the callback is needed,
4034 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4035 */
4036 }
4037 /**
4038 * @brief Input Capture callback in non blocking mode
4039 * @param htim: TIM IC handle
4040 * @retval None
4041 */
4042 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4043 {
4044 /* NOTE : This function Should not be modified, when the callback is needed,
4045 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4046 */
4047 }
4048
4049 /**
4050 * @brief PWM Pulse finished callback in non blocking mode
4051 * @param htim : TIM handle
4052 * @retval None
4053 */
4054 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4055 {
4056 /* NOTE : This function Should not be modified, when the callback is needed,
4057 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4058 */
4059 }
4060
4061 /**
4062 * @brief Hall Trigger detection callback in non blocking mode
4063 * @param htim : TIM handle
4064 * @retval None
4065 */
4066 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4067 {
4068 /* NOTE : This function Should not be modified, when the callback is needed,
4069 the HAL_TIM_TriggerCallback could be implemented in the user file
4070 */
4071 }
4072
4073 /**
4074 * @brief Timer error callback in non blocking mode
4075 * @param htim : TIM handle
4076 * @retval None
4077 */
4078 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4079 {
4080 /* NOTE : This function Should not be modified, when the callback is needed,
4081 the HAL_TIM_ErrorCallback could be implemented in the user file
4082 */
4083 }
4084
4085 /**
4086 * @}
4087 */
4088
4089 /** @addtogroup TIM_Exported_Functions_Group10
4090 * @brief Peripheral State functions
4091 *
4092 @verbatim
4093 ==============================================================================
4094 ##### Peripheral State functions #####
4095 ==============================================================================
4096 [..]
4097 This subsection permits to get in run-time the status of the peripheral
4098 and the data flow.
4099
4100 @endverbatim
4101 * @{
4102 */
4103
4104 /**
4105 * @brief Return the TIM Base state
4106 * @param htim : TIM handle
4107 * @retval HAL state
4108 */
4109 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4110 {
4111 return htim->State;
4112 }
4113
4114 /**
4115 * @brief Return the TIM OC state
4116 * @param htim: TIM Ouput Compare handle
4117 * @retval HAL state
4118 */
4119 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4120 {
4121 return htim->State;
4122 }
4123
4124 /**
4125 * @brief Return the TIM PWM state
4126 * @param htim : TIM handle
4127 * @retval HAL state
4128 */
4129 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4130 {
4131 return htim->State;
4132 }
4133
4134 /**
4135 * @brief Return the TIM Input Capture state
4136 * @param htim : TIM handle
4137 * @retval HAL state
4138 */
4139 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4140 {
4141 return htim->State;
4142 }
4143
4144 /**
4145 * @brief Return the TIM One Pulse Mode state
4146 * @param htim: TIM OPM handle
4147 * @retval HAL state
4148 */
4149 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4150 {
4151 return htim->State;
4152 }
4153
4154 /**
4155 * @brief Return the TIM Encoder Mode state
4156 * @param htim : TIM handle
4157 * @retval HAL state
4158 */
4159 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4160 {
4161 return htim->State;
4162 }
4163
4164
4165
4166 /**
4167 * @brief TIM DMA error callback
4168 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
4169 * the configuration information for the specified DMA module.
4170 * @retval None
4171 */
4172 void TIM_DMAError(DMA_HandleTypeDef *hdma)
4173 {
4174 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4175
4176 htim->State= HAL_TIM_STATE_READY;
4177
4178 HAL_TIM_ErrorCallback(htim);
4179 }
4180
4181 /**
4182 * @brief TIM DMA Delay Pulse complete callback.
4183 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
4184 * the configuration information for the specified DMA module.
4185 * @retval None
4186 */
4187 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4188 {
4189 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4190
4191 htim->State= HAL_TIM_STATE_READY;
4192
4193 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4194 {
4195 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4196 }
4197 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4198 {
4199 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4200 }
4201 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4202 {
4203 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4204 }
4205 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4206 {
4207 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4208 }
4209 HAL_TIM_PWM_PulseFinishedCallback(htim);
4210
4211 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4212 }
4213 /**
4214 * @brief TIM DMA Capture complete callback.
4215 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
4216 * the configuration information for the specified DMA module.
4217 * @retval None
4218 */
4219 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4220 {
4221 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4222
4223 htim->State= HAL_TIM_STATE_READY;
4224
4225 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4226 {
4227 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4228 }
4229 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4230 {
4231 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4232 }
4233 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4234 {
4235 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4236 }
4237 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4238 {
4239 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4240 }
4241
4242 HAL_TIM_IC_CaptureCallback(htim);
4243
4244 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4245 }
4246
4247
4248 /**
4249 * @}
4250 */
4251
4252 /**
4253 * @}
4254 */
4255 /*************************************************************/
4256 /* Private functions */
4257 /*************************************************************/
4258
4259 /** @defgroup TIM_Private_Functions TIM Private Functions
4260 * @{
4261 */
4262 /**
4263 * @brief TIM DMA Period Elapse complete callback.
4264 * @param hdma : pointer to DMA handle.
4265 * @retval None
4266 */
4267 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4268 {
4269 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4270
4271 htim->State= HAL_TIM_STATE_READY;
4272
4273 HAL_TIM_PeriodElapsedCallback(htim);
4274 }
4275
4276
4277 /**
4278 * @brief TIM DMA Trigger callback.
4279 * @param hdma : pointer to DMA handle.
4280 * @retval None
4281 */
4282 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4283 {
4284 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4285
4286 htim->State= HAL_TIM_STATE_READY;
4287
4288 HAL_TIM_TriggerCallback(htim);
4289 }
4290
4291 /**
4292 * @brief Time Base configuration
4293 * @param TIMx : TIM peripheral
4294 * @param Structure : TIM Base configuration structure
4295 * @retval None
4296 */
4297 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4298 {
4299 uint32_t tmpcr1 = 0;
4300 tmpcr1 = TIMx->CR1;
4301
4302 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4303 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
4304 {
4305 /* Select the Counter Mode */
4306 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4307 tmpcr1 |= Structure->CounterMode;
4308 }
4309
4310 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
4311 {
4312 /* Set the clock division */
4313 tmpcr1 &= ~TIM_CR1_CKD;
4314 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4315 }
4316
4317 TIMx->CR1 = tmpcr1;
4318
4319 /* Set the Autoreload value */
4320 TIMx->ARR = (uint32_t)Structure->Period ;
4321
4322 /* Set the Prescaler value */
4323 TIMx->PSC = (uint32_t)Structure->Prescaler;
4324
4325 /* Generate an update event to reload the Prescaler value immediatly */
4326 TIMx->EGR = TIM_EGR_UG;
4327 }
4328
4329 /**
4330 * @brief Time Ouput Compare 1 configuration
4331 * @param TIMx to select the TIM peripheral
4332 * @param OC_Config: The ouput configuration structure
4333 * @retval None
4334 */
4335 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4336 {
4337 uint32_t tmpccmrx = 0;
4338 uint32_t tmpccer = 0;
4339 uint32_t tmpcr2 = 0;
4340
4341 /* Disable the Channel 1: Reset the CC1E Bit */
4342 TIMx->CCER &= ~TIM_CCER_CC1E;
4343
4344 /* Get the TIMx CCER register value */
4345 tmpccer = TIMx->CCER;
4346 /* Get the TIMx CR2 register value */
4347 tmpcr2 = TIMx->CR2;
4348
4349 /* Get the TIMx CCMR1 register value */
4350 tmpccmrx = TIMx->CCMR1;
4351
4352 /* Reset the Output Compare Mode Bits */
4353 tmpccmrx &= ~TIM_CCMR1_OC1M;
4354 tmpccmrx &= ~TIM_CCMR1_CC1S;
4355 /* Select the Output Compare Mode */
4356 tmpccmrx |= OC_Config->OCMode;
4357
4358 /* Reset the Output Polarity level */
4359 tmpccer &= ~TIM_CCER_CC1P;
4360 /* Set the Output Compare Polarity */
4361 tmpccer |= OC_Config->OCPolarity;
4362
4363 /* Write to TIMx CR2 */
4364 TIMx->CR2 = tmpcr2;
4365
4366 /* Write to TIMx CCMR1 */
4367 TIMx->CCMR1 = tmpccmrx;
4368
4369 /* Set the Capture Compare Register value */
4370 TIMx->CCR1 = OC_Config->Pulse;
4371
4372 /* Write to TIMx CCER */
4373 TIMx->CCER = tmpccer;
4374 }
4375
4376 /**
4377 * @brief Time Ouput Compare 2 configuration
4378 * @param TIMx to select the TIM peripheral
4379 * @param OC_Config: The ouput configuration structure
4380 * @retval None
4381 */
4382 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4383 {
4384 uint32_t tmpccmrx = 0;
4385 uint32_t tmpccer = 0;
4386 uint32_t tmpcr2 = 0;
4387
4388 /* Disable the Channel 2: Reset the CC2E Bit */
4389 TIMx->CCER &= ~TIM_CCER_CC2E;
4390
4391 /* Get the TIMx CCER register value */
4392 tmpccer = TIMx->CCER;
4393 /* Get the TIMx CR2 register value */
4394 tmpcr2 = TIMx->CR2;
4395
4396 /* Get the TIMx CCMR1 register value */
4397 tmpccmrx = TIMx->CCMR1;
4398
4399 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4400 tmpccmrx &= ~TIM_CCMR1_OC2M;
4401 tmpccmrx &= ~TIM_CCMR1_CC2S;
4402
4403 /* Select the Output Compare Mode */
4404 tmpccmrx |= (OC_Config->OCMode << 8);
4405
4406 /* Reset the Output Polarity level */
4407 tmpccer &= ~TIM_CCER_CC2P;
4408 /* Set the Output Compare Polarity */
4409 tmpccer |= (OC_Config->OCPolarity << 4);
4410
4411 /* Write to TIMx CR2 */
4412 TIMx->CR2 = tmpcr2;
4413
4414 /* Write to TIMx CCMR1 */
4415 TIMx->CCMR1 = tmpccmrx;
4416
4417 /* Set the Capture Compare Register value */
4418 TIMx->CCR2 = OC_Config->Pulse;
4419
4420 /* Write to TIMx CCER */
4421 TIMx->CCER = tmpccer;
4422 }
4423
4424 /**
4425 * @brief Time Ouput Compare 3 configuration
4426 * @param TIMx to select the TIM peripheral
4427 * @param OC_Config: The ouput configuration structure
4428 * @retval None
4429 */
4430 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4431 {
4432 uint32_t tmpccmrx = 0;
4433 uint32_t tmpccer = 0;
4434 uint32_t tmpcr2 = 0;
4435
4436 /* Disable the Channel 3: Reset the CC2E Bit */
4437 TIMx->CCER &= ~TIM_CCER_CC3E;
4438
4439 /* Get the TIMx CCER register value */
4440 tmpccer = TIMx->CCER;
4441 /* Get the TIMx CR2 register value */
4442 tmpcr2 = TIMx->CR2;
4443
4444 /* Get the TIMx CCMR2 register value */
4445 tmpccmrx = TIMx->CCMR2;
4446
4447 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4448 tmpccmrx &= ~TIM_CCMR2_OC3M;
4449 tmpccmrx &= ~TIM_CCMR2_CC3S;
4450 /* Select the Output Compare Mode */
4451 tmpccmrx |= OC_Config->OCMode;
4452
4453 /* Reset the Output Polarity level */
4454 tmpccer &= ~TIM_CCER_CC3P;
4455 /* Set the Output Compare Polarity */
4456 tmpccer |= (OC_Config->OCPolarity << 8);
4457
4458 /* Write to TIMx CR2 */
4459 TIMx->CR2 = tmpcr2;
4460
4461 /* Write to TIMx CCMR2 */
4462 TIMx->CCMR2 = tmpccmrx;
4463
4464 /* Set the Capture Compare Register value */
4465 TIMx->CCR3 = OC_Config->Pulse;
4466
4467 /* Write to TIMx CCER */
4468 TIMx->CCER = tmpccer;
4469 }
4470
4471 /**
4472 * @brief Time Ouput Compare 4 configuration
4473 * @param TIMx to select the TIM peripheral
4474 * @param OC_Config: The ouput configuration structure
4475 * @retval None
4476 */
4477 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4478 {
4479 uint32_t tmpccmrx = 0;
4480 uint32_t tmpccer = 0;
4481 uint32_t tmpcr2 = 0;
4482
4483 /* Disable the Channel 4: Reset the CC4E Bit */
4484 TIMx->CCER &= ~TIM_CCER_CC4E;
4485
4486 /* Get the TIMx CCER register value */
4487 tmpccer = TIMx->CCER;
4488 /* Get the TIMx CR2 register value */
4489 tmpcr2 = TIMx->CR2;
4490
4491 /* Get the TIMx CCMR2 register value */
4492 tmpccmrx = TIMx->CCMR2;
4493
4494 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4495 tmpccmrx &= ~TIM_CCMR2_OC4M;
4496 tmpccmrx &= ~TIM_CCMR2_CC4S;
4497
4498 /* Select the Output Compare Mode */
4499 tmpccmrx |= (OC_Config->OCMode << 8);
4500
4501 /* Reset the Output Polarity level */
4502 tmpccer &= ~TIM_CCER_CC4P;
4503 /* Set the Output Compare Polarity */
4504 tmpccer |= (OC_Config->OCPolarity << 12);
4505
4506 /* Write to TIMx CR2 */
4507 TIMx->CR2 = tmpcr2;
4508
4509 /* Write to TIMx CCMR2 */
4510 TIMx->CCMR2 = tmpccmrx;
4511
4512 /* Set the Capture Compare Register value */
4513 TIMx->CCR4 = OC_Config->Pulse;
4514
4515 /* Write to TIMx CCER */
4516 TIMx->CCER = tmpccer;
4517 }
4518
4519 /**
4520 * @brief Configure the TI1 as Input.
4521 * @param TIMx to select the TIM peripheral.
4522 * @param TIM_ICPolarity : The Input Polarity.
4523 * This parameter can be one of the following values:
4524 * @arg TIM_ICPolarity_Rising
4525 * @arg TIM_ICPolarity_Falling
4526 * @arg TIM_ICPolarity_BothEdge
4527 * @param TIM_ICSelection: specifies the input to be used.
4528 * This parameter can be one of the following values:
4529 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
4530 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
4531 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
4532 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4533 * This parameter must be a value between 0x00 and 0x0F.
4534 * @retval None
4535 */
4536 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4537 uint32_t TIM_ICFilter)
4538 {
4539 uint32_t tmpccmr1 = 0;
4540 uint32_t tmpccer = 0;
4541
4542 /* Disable the Channel 1: Reset the CC1E Bit */
4543 TIMx->CCER &= ~TIM_CCER_CC1E;
4544 tmpccmr1 = TIMx->CCMR1;
4545 tmpccer = TIMx->CCER;
4546
4547 /* Select the Input */
4548 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4549 {
4550 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4551 tmpccmr1 |= TIM_ICSelection;
4552 }
4553 else
4554 {
4555 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4556 tmpccmr1 |= TIM_CCMR1_CC1S_0;
4557 }
4558
4559 /* Set the filter */
4560 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4561 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
4562
4563 /* Select the Polarity and set the CC1E Bit */
4564 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4565 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
4566
4567 /* Write to TIMx CCMR1 and CCER registers */
4568 TIMx->CCMR1 = tmpccmr1;
4569 TIMx->CCER = tmpccer;
4570 }
4571
4572 /**
4573 * @brief Configure the Polarity and Filter for TI1.
4574 * @param TIMx to select the TIM peripheral.
4575 * @param TIM_ICPolarity : The Input Polarity.
4576 * This parameter can be one of the following values:
4577 * @arg TIM_ICPolarity_Rising
4578 * @arg TIM_ICPolarity_Falling
4579 * @arg TIM_ICPolarity_BothEdge
4580 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4581 * This parameter must be a value between 0x00 and 0x0F.
4582 * @retval None
4583 */
4584 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4585 {
4586 uint32_t tmpccmr1 = 0;
4587 uint32_t tmpccer = 0;
4588
4589 /* Disable the Channel 1: Reset the CC1E Bit */
4590 tmpccer = TIMx->CCER;
4591 TIMx->CCER &= ~TIM_CCER_CC1E;
4592 tmpccmr1 = TIMx->CCMR1;
4593
4594 /* Set the filter */
4595 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4596 tmpccmr1 |= (TIM_ICFilter << 4);
4597
4598 /* Select the Polarity and set the CC1E Bit */
4599 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4600 tmpccer |= TIM_ICPolarity;
4601
4602 /* Write to TIMx CCMR1 and CCER registers */
4603 TIMx->CCMR1 = tmpccmr1;
4604 TIMx->CCER = tmpccer;
4605 }
4606
4607 /**
4608 * @brief Configure the TI2 as Input.
4609 * @param TIMx to select the TIM peripheral
4610 * @param TIM_ICPolarity : The Input Polarity.
4611 * This parameter can be one of the following values:
4612 * @arg TIM_ICPolarity_Rising
4613 * @arg TIM_ICPolarity_Falling
4614 * @arg TIM_ICPolarity_BothEdge
4615 * @param TIM_ICSelection: specifies the input to be used.
4616 * This parameter can be one of the following values:
4617 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
4618 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
4619 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
4620 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4621 * This parameter must be a value between 0x00 and 0x0F.
4622 * @retval None
4623 */
4624 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4625 uint32_t TIM_ICFilter)
4626 {
4627 uint32_t tmpccmr1 = 0;
4628 uint32_t tmpccer = 0;
4629
4630 /* Disable the Channel 2: Reset the CC2E Bit */
4631 TIMx->CCER &= ~TIM_CCER_CC2E;
4632 tmpccmr1 = TIMx->CCMR1;
4633 tmpccer = TIMx->CCER;
4634
4635 /* Select the Input */
4636 tmpccmr1 &= ~TIM_CCMR1_CC2S;
4637 tmpccmr1 |= (TIM_ICSelection << 8);
4638
4639 /* Set the filter */
4640 tmpccmr1 &= ~TIM_CCMR1_IC2F;
4641 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
4642
4643 /* Select the Polarity and set the CC2E Bit */
4644 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4645 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
4646
4647 /* Write to TIMx CCMR1 and CCER registers */
4648 TIMx->CCMR1 = tmpccmr1 ;
4649 TIMx->CCER = tmpccer;
4650 }
4651
4652 /**
4653 * @brief Configure the Polarity and Filter for TI2.
4654 * @param TIMx to select the TIM peripheral.
4655 * @param TIM_ICPolarity : The Input Polarity.
4656 * This parameter can be one of the following values:
4657 * @arg TIM_ICPolarity_Rising
4658 * @arg TIM_ICPolarity_Falling
4659 * @arg TIM_ICPolarity_BothEdge
4660 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4661 * This parameter must be a value between 0x00 and 0x0F.
4662 * @retval None
4663 */
4664 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4665 {
4666 uint32_t tmpccmr1 = 0;
4667 uint32_t tmpccer = 0;
4668
4669 /* Disable the Channel 2: Reset the CC2E Bit */
4670 TIMx->CCER &= ~TIM_CCER_CC2E;
4671 tmpccmr1 = TIMx->CCMR1;
4672 tmpccer = TIMx->CCER;
4673
4674 /* Set the filter */
4675 tmpccmr1 &= ~TIM_CCMR1_IC2F;
4676 tmpccmr1 |= (TIM_ICFilter << 12);
4677
4678 /* Select the Polarity and set the CC2E Bit */
4679 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4680 tmpccer |= (TIM_ICPolarity << 4);
4681
4682 /* Write to TIMx CCMR1 and CCER registers */
4683 TIMx->CCMR1 = tmpccmr1 ;
4684 TIMx->CCER = tmpccer;
4685 }
4686
4687 /**
4688 * @brief Configure the TI3 as Input.
4689 * @param TIMx to select the TIM peripheral
4690 * @param TIM_ICPolarity : The Input Polarity.
4691 * This parameter can be one of the following values:
4692 * @arg TIM_ICPolarity_Rising
4693 * @arg TIM_ICPolarity_Falling
4694 * @arg TIM_ICPolarity_BothEdge
4695 * @param TIM_ICSelection: specifies the input to be used.
4696 * This parameter can be one of the following values:
4697 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
4698 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
4699 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
4700 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4701 * This parameter must be a value between 0x00 and 0x0F.
4702 * @retval None
4703 */
4704 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4705 uint32_t TIM_ICFilter)
4706 {
4707 uint32_t tmpccmr2 = 0;
4708 uint32_t tmpccer = 0;
4709
4710 /* Disable the Channel 3: Reset the CC3E Bit */
4711 TIMx->CCER &= ~TIM_CCER_CC3E;
4712 tmpccmr2 = TIMx->CCMR2;
4713 tmpccer = TIMx->CCER;
4714
4715 /* Select the Input */
4716 tmpccmr2 &= ~TIM_CCMR2_CC3S;
4717 tmpccmr2 |= TIM_ICSelection;
4718
4719 /* Set the filter */
4720 tmpccmr2 &= ~TIM_CCMR2_IC3F;
4721 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
4722
4723 /* Select the Polarity and set the CC3E Bit */
4724 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
4725 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
4726
4727 /* Write to TIMx CCMR2 and CCER registers */
4728 TIMx->CCMR2 = tmpccmr2;
4729 TIMx->CCER = tmpccer;
4730 }
4731
4732 /**
4733 * @brief Configure the TI4 as Input.
4734 * @param TIMx to select the TIM peripheral
4735 * @param TIM_ICPolarity : The Input Polarity.
4736 * This parameter can be one of the following values:
4737 * @arg TIM_ICPolarity_Rising
4738 * @arg TIM_ICPolarity_Falling
4739 * @arg TIM_ICPolarity_BothEdge
4740 * @param TIM_ICSelection: specifies the input to be used.
4741 * This parameter can be one of the following values:
4742 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
4743 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
4744 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
4745 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4746 * This parameter must be a value between 0x00 and 0x0F.
4747 * @retval None
4748 */
4749 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4750 uint32_t TIM_ICFilter)
4751 {
4752 uint32_t tmpccmr2 = 0;
4753 uint32_t tmpccer = 0;
4754
4755 /* Disable the Channel 4: Reset the CC4E Bit */
4756 TIMx->CCER &= ~TIM_CCER_CC4E;
4757 tmpccmr2 = TIMx->CCMR2;
4758 tmpccer = TIMx->CCER;
4759
4760 /* Select the Input */
4761 tmpccmr2 &= ~TIM_CCMR2_CC4S;
4762 tmpccmr2 |= (TIM_ICSelection << 8);
4763
4764 /* Set the filter */
4765 tmpccmr2 &= ~TIM_CCMR2_IC4F;
4766 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
4767
4768 /* Select the Polarity and set the CC4E Bit */
4769 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
4770 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
4771
4772 /* Write to TIMx CCMR2 and CCER registers */
4773 TIMx->CCMR2 = tmpccmr2;
4774 TIMx->CCER = tmpccer ;
4775 }
4776
4777 /**
4778 * @brief Selects the Input Trigger source
4779 * @param TIMx to select the TIM peripheral
4780 * @param InputTriggerSource: The Input Trigger source.
4781 * This parameter can be one of the following values:
4782 * @arg TIM_TS_ITR0: Internal Trigger 0
4783 * @arg TIM_TS_ITR1: Internal Trigger 1
4784 * @arg TIM_TS_ITR2: Internal Trigger 2
4785 * @arg TIM_TS_ITR3: Internal Trigger 3
4786 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
4787 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
4788 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
4789 * @arg TIM_TS_ETRF: External Trigger input
4790 * @retval None
4791 */
4792 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
4793 {
4794 uint32_t tmpsmcr = 0;
4795
4796 /* Get the TIMx SMCR register value */
4797 tmpsmcr = TIMx->SMCR;
4798 /* Reset the TS Bits */
4799 tmpsmcr &= ~TIM_SMCR_TS;
4800 /* Set the Input Trigger source and the slave mode*/
4801 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
4802 /* Write to TIMx SMCR */
4803 TIMx->SMCR = tmpsmcr;
4804 }
4805 /**
4806 * @brief Configures the TIMx External Trigger (ETR).
4807 * @param TIMx to select the TIM peripheral
4808 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
4809 * This parameter can be one of the following values:
4810 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
4811 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
4812 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
4813 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
4814 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
4815 * This parameter can be one of the following values:
4816 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
4817 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
4818 * @param ExtTRGFilter: External Trigger Filter.
4819 * This parameter must be a value between 0x00 and 0x0F
4820 * @retval None
4821 */
4822 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
4823 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
4824 {
4825 uint32_t tmpsmcr = 0;
4826
4827 tmpsmcr = TIMx->SMCR;
4828
4829 /* Reset the ETR Bits */
4830 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4831
4832 /* Set the Prescaler, the Filter value and the Polarity */
4833 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
4834
4835 /* Write to TIMx SMCR */
4836 TIMx->SMCR = tmpsmcr;
4837 }
4838
4839 /**
4840 * @brief Enables or disables the TIM Capture Compare Channel x.
4841 * @param TIMx to select the TIM peripheral
4842 * @param Channel: specifies the TIM Channel
4843 * This parameter can be one of the following values:
4844 * @arg TIM_Channel_1: TIM Channel 1
4845 * @arg TIM_Channel_2: TIM Channel 2
4846 * @arg TIM_Channel_3: TIM Channel 3
4847 * @arg TIM_Channel_4: TIM Channel 4
4848 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
4849 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
4850 * @retval None
4851 */
4852 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
4853 {
4854 uint32_t tmp = 0;
4855
4856 /* Check the parameters */
4857 assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel));
4858
4859 tmp = TIM_CCER_CC1E << Channel;
4860
4861 /* Reset the CCxE Bit */
4862 TIMx->CCER &= ~tmp;
4863
4864 /* Set or reset the CCxE Bit */
4865 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
4866 }
4867 /**
4868 * @brief Set the slave timer configuration.
4869 * @param htim : TIM handle
4870 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4871 * contains the selected trigger (internal trigger input, filtered
4872 * timer input or external trigger input) and the ) and the Slave
4873 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4874 * @retval None
4875 */
4876 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
4877 TIM_SlaveConfigTypeDef * sSlaveConfig)
4878 {
4879 uint32_t tmpsmcr = 0;
4880 uint32_t tmpccmr1 = 0;
4881 uint32_t tmpccer = 0;
4882
4883 /* Get the TIMx SMCR register value */
4884 tmpsmcr = htim->Instance->SMCR;
4885
4886 /* Reset the Trigger Selection Bits */
4887 tmpsmcr &= ~TIM_SMCR_TS;
4888 /* Set the Input Trigger source */
4889 tmpsmcr |= sSlaveConfig->InputTrigger;
4890
4891 /* Reset the slave mode Bits */
4892 tmpsmcr &= ~TIM_SMCR_SMS;
4893 /* Set the slave mode */
4894 tmpsmcr |= sSlaveConfig->SlaveMode;
4895
4896 /* Write to TIMx SMCR */
4897 htim->Instance->SMCR = tmpsmcr;
4898
4899 /* Configure the trigger prescaler, filter, and polarity */
4900 switch (sSlaveConfig->InputTrigger)
4901 {
4902 case TIM_TS_ETRF:
4903 {
4904 /* Check the parameters */
4905 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
4906 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
4907 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4908 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4909 /* Configure the ETR Trigger source */
4910 TIM_ETR_SetConfig(htim->Instance,
4911 sSlaveConfig->TriggerPrescaler,
4912 sSlaveConfig->TriggerPolarity,
4913 sSlaveConfig->TriggerFilter);
4914 }
4915 break;
4916
4917 case TIM_TS_TI1F_ED:
4918 {
4919 /* Check the parameters */
4920 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4921 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4922
4923 /* Disable the Channel 1: Reset the CC1E Bit */
4924 tmpccer = htim->Instance->CCER;
4925 htim->Instance->CCER &= ~TIM_CCER_CC1E;
4926 tmpccmr1 = htim->Instance->CCMR1;
4927
4928 /* Set the filter */
4929 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4930 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
4931
4932 /* Write to TIMx CCMR1 and CCER registers */
4933 htim->Instance->CCMR1 = tmpccmr1;
4934 htim->Instance->CCER = tmpccer;
4935
4936 }
4937 break;
4938
4939 case TIM_TS_TI1FP1:
4940 {
4941 /* Check the parameters */
4942 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4943 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4944 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4945
4946 /* Configure TI1 Filter and Polarity */
4947 TIM_TI1_ConfigInputStage(htim->Instance,
4948 sSlaveConfig->TriggerPolarity,
4949 sSlaveConfig->TriggerFilter);
4950 }
4951 break;
4952
4953 case TIM_TS_TI2FP2:
4954 {
4955 /* Check the parameters */
4956 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4957 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4958 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4959
4960 /* Configure TI2 Filter and Polarity */
4961 TIM_TI2_ConfigInputStage(htim->Instance,
4962 sSlaveConfig->TriggerPolarity,
4963 sSlaveConfig->TriggerFilter);
4964 }
4965 break;
4966
4967 case TIM_TS_ITR0:
4968 {
4969 /* Check the parameter */
4970 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4971 }
4972 break;
4973
4974 case TIM_TS_ITR1:
4975 {
4976 /* Check the parameter */
4977 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4978 }
4979 break;
4980
4981 case TIM_TS_ITR2:
4982 {
4983 /* Check the parameter */
4984 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4985 }
4986 break;
4987
4988 case TIM_TS_ITR3:
4989 {
4990 /* Check the parameter */
4991 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4992 }
4993 break;
4994
4995 default:
4996 break;
4997 }
4998 }
4999
5000 /**
5001 * @}
5002 */
5003
5004 /**
5005 * @}
5006 */
5007
5008 /**
5009 * @}
5010 */
5011
5012 #endif /* HAL_TIM_MODULE_ENABLED */
5013 /**
5014 * @}
5015 */
5016
5017 /**
5018 * @}
5019 */
5020 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
5021
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