1 /* ----------------------------------------------------------------------
2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
4 * $Date: 17. January 2013
7 * Project: CMSIS DSP Library
8 * Title: arm_rfft_q15.c
10 * Description: RFFT & RIFFT Q15 process function
13 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * - Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * - Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in
22 * the documentation and/or other materials provided with the
24 * - Neither the name of ARM LIMITED nor the names of its contributors
25 * may be used to endorse or promote products derived from this
26 * software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
31 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
32 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
34 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 * -------------------------------------------------------------------- */
44 void arm_radix4_butterfly_q15(
48 uint32_t twidCoefModifier
);
50 void arm_radix4_butterfly_inverse_q15(
54 uint32_t twidCoefModifier
);
56 void arm_bitreversal_q15(
59 uint16_t bitRevFactor
,
60 uint16_t * pBitRevTab
);
62 /*--------------------------------------------------------------------
63 * Internal functions prototypes
64 --------------------------------------------------------------------*/
66 void arm_split_rfft_q15(
74 void arm_split_rifft_q15(
88 * @brief Processing function for the Q15 RFFT/RIFFT.
89 * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
90 * @param[in] *pSrc points to the input buffer.
91 * @param[out] *pDst points to the output buffer.
94 * \par Input an output formats:
96 * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
97 * Hence the output format is different for different RFFT sizes.
98 * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
100 * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"
102 * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"
106 const arm_rfft_instance_q15
* S
,
110 const arm_cfft_radix4_instance_q15
*S_CFFT
= S
->pCfft
;
112 /* Calculation of RIFFT of input */
113 if(S
->ifftFlagR
== 1u)
115 /* Real IFFT core process */
116 arm_split_rifft_q15(pSrc
, S
->fftLenBy2
, S
->pTwiddleAReal
,
117 S
->pTwiddleBReal
, pDst
, S
->twidCoefRModifier
);
119 /* Complex readix-4 IFFT process */
120 arm_radix4_butterfly_inverse_q15(pDst
, S_CFFT
->fftLen
,
122 S_CFFT
->twidCoefModifier
);
124 /* Bit reversal process */
125 if(S
->bitReverseFlagR
== 1u)
127 arm_bitreversal_q15(pDst
, S_CFFT
->fftLen
,
128 S_CFFT
->bitRevFactor
, S_CFFT
->pBitRevTable
);
133 /* Calculation of RFFT of input */
135 /* Complex readix-4 FFT process */
136 arm_radix4_butterfly_q15(pSrc
, S_CFFT
->fftLen
,
137 S_CFFT
->pTwiddle
, S_CFFT
->twidCoefModifier
);
139 /* Bit reversal process */
140 if(S
->bitReverseFlagR
== 1u)
142 arm_bitreversal_q15(pSrc
, S_CFFT
->fftLen
,
143 S_CFFT
->bitRevFactor
, S_CFFT
->pBitRevTable
);
146 arm_split_rfft_q15(pSrc
, S
->fftLenBy2
, S
->pTwiddleAReal
,
147 S
->pTwiddleBReal
, pDst
, S
->twidCoefRModifier
);
153 * @} end of RealFFT group
157 * @brief Core Real FFT process
158 * @param *pSrc points to the input buffer.
159 * @param fftLen length of FFT.
160 * @param *pATable points to the A twiddle Coef buffer.
161 * @param *pBTable points to the B twiddle Coef buffer.
162 * @param *pDst points to the output buffer.
163 * @param modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
165 * The function implements a Real FFT
168 void arm_split_rfft_q15(
176 uint32_t i
; /* Loop Counter */
177 q31_t outR
, outI
; /* Temporary variables for output */
178 q15_t
*pCoefA
, *pCoefB
; /* Temporary pointers for twiddle factors */
179 q15_t
*pSrc1
, *pSrc2
;
182 // pSrc[2u * fftLen] = pSrc[0];
183 // pSrc[(2u * fftLen) + 1u] = pSrc[1];
185 pCoefA
= &pATable
[modifier
* 2u];
186 pCoefB
= &pBTable
[modifier
* 2u];
189 pSrc2
= &pSrc
[(2u * fftLen
) - 2u];
191 #ifndef ARM_MATH_CM0_FAMILY
193 /* Run the below code for Cortex-M4 and Cortex-M3 */
200 outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
201 + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
202 pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
205 /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
206 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
207 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
210 #ifndef ARM_MATH_BIG_ENDIAN
212 /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
213 outR
= __SMUSD(*__SIMD32(pSrc1
), *__SIMD32(pCoefA
));
217 /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
218 outR
= -(__SMUSD(*__SIMD32(pSrc1
), *__SIMD32(pCoefA
)));
220 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
222 /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +
223 pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
224 outR
= __SMLAD(*__SIMD32(pSrc2
), *__SIMD32(pCoefB
), outR
) >> 15u;
226 /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
227 pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
229 #ifndef ARM_MATH_BIG_ENDIAN
231 outI
= __SMUSDX(*__SIMD32(pSrc2
)--, *__SIMD32(pCoefB
));
235 outI
= __SMUSDX(*__SIMD32(pCoefB
), *__SIMD32(pSrc2
)--);
237 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
239 /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
240 outI
= __SMLADX(*__SIMD32(pSrc1
)++, *__SIMD32(pCoefA
), outI
);
243 pDst
[2u * i
] = (q15_t
) outR
;
244 pDst
[(2u * i
) + 1u] = outI
>> 15u;
246 /* write complex conjugate output */
247 pDst
[(4u * fftLen
) - (2u * i
)] = (q15_t
) outR
;
248 pDst
[((4u * fftLen
) - (2u * i
)) + 1u] = -(outI
>> 15u);
250 /* update coefficient pointer */
251 pCoefB
= pCoefB
+ (2u * modifier
);
252 pCoefA
= pCoefA
+ (2u * modifier
);
258 pDst
[2u * fftLen
] = pSrc
[0] - pSrc
[1];
259 pDst
[(2u * fftLen
) + 1u] = 0;
261 pDst
[0] = pSrc
[0] + pSrc
[1];
267 /* Run the below code for Cortex-M0 */
274 outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
275 + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
276 pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
279 outR
= *pSrc1
* *pCoefA
;
280 outR
= outR
- (*(pSrc1
+ 1) * *(pCoefA
+ 1));
281 outR
= outR
+ (*pSrc2
* *pCoefB
);
282 outR
= (outR
+ (*(pSrc2
+ 1) * *(pCoefB
+ 1))) >> 15;
285 /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
286 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
287 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
290 outI
= *pSrc2
* *(pCoefB
+ 1);
291 outI
= outI
- (*(pSrc2
+ 1) * *pCoefB
);
292 outI
= outI
+ (*(pSrc1
+ 1) * *pCoefA
);
293 outI
= outI
+ (*pSrc1
* *(pCoefA
+ 1));
295 /* update input pointers */
300 pDst
[2u * i
] = (q15_t
) outR
;
301 pDst
[(2u * i
) + 1u] = outI
>> 15u;
303 /* write complex conjugate output */
304 pDst
[(4u * fftLen
) - (2u * i
)] = (q15_t
) outR
;
305 pDst
[((4u * fftLen
) - (2u * i
)) + 1u] = -(outI
>> 15u);
307 /* update coefficient pointer */
308 pCoefB
= pCoefB
+ (2u * modifier
);
309 pCoefA
= pCoefA
+ (2u * modifier
);
315 pDst
[2u * fftLen
] = pSrc
[0] - pSrc
[1];
316 pDst
[(2u * fftLen
) + 1u] = 0;
318 pDst
[0] = pSrc
[0] + pSrc
[1];
321 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
327 * @brief Core Real IFFT process
328 * @param[in] *pSrc points to the input buffer.
329 * @param[in] fftLen length of FFT.
330 * @param[in] *pATable points to the twiddle Coef A buffer.
331 * @param[in] *pBTable points to the twiddle Coef B buffer.
332 * @param[out] *pDst points to the output buffer.
333 * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
335 * The function implements a Real IFFT
337 void arm_split_rifft_q15(
345 uint32_t i
; /* Loop Counter */
346 q31_t outR
, outI
; /* Temporary variables for output */
347 q15_t
*pCoefA
, *pCoefB
; /* Temporary pointers for twiddle factors */
348 q15_t
*pSrc1
, *pSrc2
;
349 q15_t
*pDst1
= &pDst
[0];
351 pCoefA
= &pATable
[0];
352 pCoefB
= &pBTable
[0];
355 pSrc2
= &pSrc
[2u * fftLen
];
357 #ifndef ARM_MATH_CM0_FAMILY
359 /* Run the below code for Cortex-M4 and Cortex-M3 */
367 outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
368 pIn[2 * n - 2 * i] * pBTable[2 * i] -
369 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
371 outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
372 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
373 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
378 #ifndef ARM_MATH_BIG_ENDIAN
380 /* pIn[2 * n - 2 * i] * pBTable[2 * i] -
381 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
382 outR
= __SMUSD(*__SIMD32(pSrc2
), *__SIMD32(pCoefB
));
386 /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +
387 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
388 outR
= -(__SMUSD(*__SIMD32(pSrc2
), *__SIMD32(pCoefB
)));
390 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
392 /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
393 pIn[2 * n - 2 * i] * pBTable[2 * i] */
394 outR
= __SMLAD(*__SIMD32(pSrc1
), *__SIMD32(pCoefA
), outR
) >> 15u;
397 -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +
398 pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
399 outI
= __SMUADX(*__SIMD32(pSrc2
)--, *__SIMD32(pCoefB
));
401 /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
403 #ifndef ARM_MATH_BIG_ENDIAN
405 outI
= __SMLSDX(*__SIMD32(pCoefA
), *__SIMD32(pSrc1
)++, -outI
);
409 outI
= __SMLSDX(*__SIMD32(pSrc1
)++, *__SIMD32(pCoefA
), -outI
);
411 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
414 #ifndef ARM_MATH_BIG_ENDIAN
416 *__SIMD32(pDst1
)++ = __PKHBT(outR
, (outI
>> 15u), 16);
420 *__SIMD32(pDst1
)++ = __PKHBT((outI
>> 15u), outR
, 16);
422 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
424 /* update coefficient pointer */
425 pCoefB
= pCoefB
+ (2u * modifier
);
426 pCoefA
= pCoefA
+ (2u * modifier
);
435 /* Run the below code for Cortex-M0 */
443 outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
444 pIn[2 * n - 2 * i] * pBTable[2 * i] -
445 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
448 outR
= *pSrc2
* *pCoefB
;
449 outR
= outR
- (*(pSrc2
+ 1) * *(pCoefB
+ 1));
450 outR
= outR
+ (*pSrc1
* *pCoefA
);
451 outR
= (outR
+ (*(pSrc1
+ 1) * *(pCoefA
+ 1))) >> 15;
454 outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
455 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
456 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
459 outI
= *(pSrc1
+ 1) * *pCoefA
;
460 outI
= outI
- (*pSrc1
* *(pCoefA
+ 1));
461 outI
= outI
- (*pSrc2
* *(pCoefB
+ 1));
462 outI
= outI
- (*(pSrc2
+ 1) * *(pCoefB
));
464 /* update input pointers */
469 *pDst1
++ = (q15_t
) outR
;
470 *pDst1
++ = (q15_t
) (outI
>> 15);
472 /* update coefficient pointer */
473 pCoefB
= pCoefB
+ (2u * modifier
);
474 pCoefA
= pCoefA
+ (2u * modifier
);
480 #endif /* #ifndef ARM_MATH_CM0_FAMILY */