tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_tim.c
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   TIM HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities of the Timer (TIM) peripheral:
  10   *           + Time Base Initialization
  11   *           + Time Base Start
  12   *           + Time Base Start Interruption
  13   *           + Time Base Start DMA
  14   *           + Time Output Compare/PWM Initialization
  15   *           + Time Output Compare/PWM Channel Configuration
  16   *           + Time Output Compare/PWM  Start
  17   *           + Time Output Compare/PWM  Start Interruption
  18   *           + Time Output Compare/PWM Start DMA
  19   *           + Time Input Capture Initialization
  20   *           + Time Input Capture Channel Configuration
  21   *           + Time Input Capture Start
  22   *           + Time Input Capture Start Interruption
  23   *           + Time Input Capture Start DMA
  24   *           + Time One Pulse Initialization
  25   *           + Time One Pulse Channel Configuration
  26   *           + Time One Pulse Start
  27   *           + Time Encoder Interface Initialization
  28   *           + Time Encoder Interface Start
  29   *           + Time Encoder Interface Start Interruption
  30   *           + Time Encoder Interface Start DMA
  31   *           + Commutation Event configuration with Interruption and DMA
  32   *           + Time OCRef clear configuration
  33   *           + Time External Clock configuration
  34   *           + Time Master and Slave synchronization configuration
  35   @verbatim
  36   ==============================================================================
  37                       ##### TIMER Generic features #####
  38   ==============================================================================
  39   [..] The Timer features include:
  40        (#) 16-bit up, down, up/down auto-reload counter.
  41        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
  42            counter clock frequency either by any factor between 1 and 65536.
  43        (#) Up to 4 independent channels for:
  44            (++) Input Capture
  45            (++) Output Compare
  46            (++) PWM generation (Edge and Center-aligned Mode)
  47            (++) One-pulse mode output
  48        (#) Synchronization circuit to control the timer with external signals and to interconnect
  49            several timers together.
  50        (#) Supports incremental (quadrature) encoder
  51
  52             ##### How to use this driver #####
  53 ================================================================================
  54     [..]
  55      (#) Initialize the TIM low level resources by implementing the following functions
  56          depending from feature used :
  57            (++) Time Base : HAL_TIM_Base_MspInit()
  58            (++) Input Capture : HAL_TIM_IC_MspInit()
  59            (++) Output Compare : HAL_TIM_OC_MspInit()
  60            (++) PWM generation : HAL_TIM_PWM_MspInit()
  61            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
  62            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
  63
  64      (#) Initialize the TIM low level resources :
  65         (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
  66         (##) TIM pins configuration
  67             (+++) Enable the clock for the TIM GPIOs using the following function:
  68              __GPIOx_CLK_ENABLE();
  69             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
  70
  71      (#) The external Clock can be configured, if needed (the default clock is the
  72          internal clock from the APBx), using the following function:
  73          HAL_TIM_ConfigClockSource, the clock configuration should be done before
  74          any start function.
  75
  76      (#) Configure the TIM in the desired functioning mode using one of the
  77        Initialization function of this driver:
  78        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
  79        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
  80             Output Compare signal.
  81        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
  82             PWM signal.
  83        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
  84             external signal.
  85          (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
  86               in One Pulse Mode.
  87        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
  88
  89      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
  90            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
  91            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
  92            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
  93            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
  94            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
  95            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
  96
  97      (#) The DMA Burst is managed with the two following functions:
  98          HAL_TIM_DMABurst_WriteStart()
  99          HAL_TIM_DMABurst_ReadStart()
 100
 101   @endverbatim
 102   ******************************************************************************
 103   * @attention
 104   *
 105   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
 106   *
 107   * Redistribution and use in source and binary forms, with or without modification,
 108   * are permitted provided that the following conditions are met:
 109   *   1. Redistributions of source code must retain the above copyright notice,
 110   *      this list of conditions and the following disclaimer.
 111   *   2. Redistributions in binary form must reproduce the above copyright notice,
 112   *      this list of conditions and the following disclaimer in the documentation
 113   *      and/or other materials provided with the distribution.
 114   *   3. Neither the name of STMicroelectronics nor the names of its contributors
 115   *      may be used to endorse or promote products derived from this software
 116   *      without specific prior written permission.
 117   *
 118   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 119   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 120   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 121   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 122   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 123   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 124   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 125   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 126   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 127   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 128   *
 129   ******************************************************************************
 130   */
 131
 132 /* Includes ------------------------------------------------------------------*/
 133 #include "stm32l1xx_hal.h"
 134
 135 /** @addtogroup STM32L1xx_HAL_Driver
 136   * @{
 137   */
 138
 139 /** @defgroup TIM TIM
 140   * @brief TIM HAL module driver
 141   * @{
 142   */
 143
 144 #ifdef HAL_TIM_MODULE_ENABLED
 145
 146 /* Private typedef -----------------------------------------------------------*/
 147 /* Private define ------------------------------------------------------------*/
 148 /* Private macro -------------------------------------------------------------*/
 149 /* Private variables ---------------------------------------------------------*/
 150 /* Private function prototypes -----------------------------------------------*/
 151 /** @defgroup TIM_Private_Functions TIM Private Functions
 152   * @{
 153   */
 154 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 155 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 156 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 157
 158 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
 159 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
 160                        uint32_t TIM_ICFilter);
 161 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
 162 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
 163                        uint32_t TIM_ICFilter);
 164 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
 165                        uint32_t TIM_ICFilter);
 166
 167 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
 168                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
 169
 170 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
 171 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
 172 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
 173 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
 174 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
 175 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 176 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
 177 static void TIM_DMAError(DMA_HandleTypeDef *hdma);
 178 static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
 179 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
 180
 181 /**
 182     * @}
 183   */
 184
 185 /* External functions ---------------------------------------------------------*/
 186
 187 /** @defgroup TIM_Exported_Functions TIM Exported Functions
 188   * @{
 189   */
 190
 191 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
 192  *  @brief    Time Base functions
 193  *
 194 @verbatim
 195   ==============================================================================
 196               ##### Time Base functions #####
 197   ==============================================================================
 198   [..]
 199     This section provides functions allowing to:
 200     (+) Initialize and configure the TIM base.
 201     (+) De-initialize the TIM base.
 202     (+) Start the Time Base.
 203     (+) Stop the Time Base.
 204     (+) Start the Time Base and enable interrupt.
 205     (+) Stop the Time Base and disable interrupt.
 206     (+) Start the Time Base and enable DMA transfer.
 207     (+) Stop the Time Base and disable DMA transfer.
 208
 209 @endverbatim
 210   * @{
 211   */
 212 /**
 213   * @brief  Initializes the TIM Time base Unit according to the specified
 214   *         parameters in the TIM_HandleTypeDef and create the associated handle.
 215   * @param  htim: TIM Base handle
 216   * @retval HAL status
 217   */
 218 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
 219 {
 220   /* Check the TIM handle allocation */
 221   if(htim == HAL_NULL)
 222   {
 223     return HAL_ERROR;
 224   }
 225
 226   /* Check the parameters */
 227   assert_param(IS_TIM_INSTANCE(htim->Instance));
 228   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
 229   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
 230
 231   if(htim->State == HAL_TIM_STATE_RESET)
 232   {
 233     /* Init the low level hardware : GPIO, CLOCK, NVIC */
 234     HAL_TIM_Base_MspInit(htim);
 235   }
 236
 237   /* Set the TIM state */
 238   htim->State= HAL_TIM_STATE_BUSY;
 239
 240   /* Set the Time Base configuration */
 241   TIM_Base_SetConfig(htim->Instance, &htim->Init);
 242
 243   /* Initialize the TIM state*/
 244   htim->State= HAL_TIM_STATE_READY;
 245
 246   return HAL_OK;
 247 }
 248
 249 /**
 250   * @brief  DeInitializes the TIM Base peripheral
 251   * @param  htim: TIM Base handle
 252   * @retval HAL status
 253   */
 254 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
 255 {
 256   /* Check the parameters */
 257   assert_param(IS_TIM_INSTANCE(htim->Instance));
 258
 259   htim->State = HAL_TIM_STATE_BUSY;
 260
 261   /* Disable the TIM Peripheral Clock */
 262   __HAL_TIM_DISABLE(htim);
 263
 264   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
 265   HAL_TIM_Base_MspDeInit(htim);
 266
 267   /* Change TIM state */
 268   htim->State = HAL_TIM_STATE_RESET;
 269
 270   /* Release Lock */
 271   __HAL_UNLOCK(htim);
 272
 273   return HAL_OK;
 274 }
 275
 276 /**
 277   * @brief  Initializes the TIM Base MSP.
 278   * @param  htim: TIM handle
 279   * @retval None
 280   */
 281 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
 282 {
 283   /* NOTE : This function Should not be modified, when the callback is needed,
 284             the HAL_TIM_Base_MspInit could be implemented in the user file
 285    */
 286 }
 287
 288 /**
 289   * @brief  DeInitializes TIM Base MSP.
 290   * @param  htim: TIM handle
 291   * @retval None
 292   */
 293 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
 294 {
 295   /* NOTE : This function Should not be modified, when the callback is needed,
 296             the HAL_TIM_Base_MspDeInit could be implemented in the user file
 297    */
 298 }
 299
 300
 301 /**
 302   * @brief  Starts the TIM Base generation.
 303   * @param  htim : TIM handle
 304   * @retval HAL status
 305 */
 306 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
 307 {
 308   /* Check the parameters */
 309   assert_param(IS_TIM_INSTANCE(htim->Instance));
 310
 311   /* Set the TIM state */
 312   htim->State= HAL_TIM_STATE_BUSY;
 313
 314   /* Enable the Peripheral */
 315   __HAL_TIM_ENABLE(htim);
 316
 317   /* Change the TIM state*/
 318   htim->State= HAL_TIM_STATE_READY;
 319
 320   /* Return function status */
 321   return HAL_OK;
 322 }
 323
 324 /**
 325   * @brief  Stops the TIM Base generation.
 326   * @param  htim : TIM handle
 327   * @retval HAL status
 328 */
 329 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
 330 {
 331   /* Check the parameters */
 332   assert_param(IS_TIM_INSTANCE(htim->Instance));
 333
 334   /* Set the TIM state */
 335   htim->State= HAL_TIM_STATE_BUSY;
 336
 337   /* Disable the Peripheral */
 338   __HAL_TIM_DISABLE(htim);
 339
 340   /* Change the TIM state*/
 341   htim->State= HAL_TIM_STATE_READY;
 342
 343   /* Return function status */
 344   return HAL_OK;
 345 }
 346
 347 /**
 348   * @brief  Starts the TIM Base generation in interrupt mode.
 349   * @param  htim : TIM handle
 350   * @retval HAL status
 351 */
 352 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
 353 {
 354   /* Check the parameters */
 355   assert_param(IS_TIM_INSTANCE(htim->Instance));
 356
 357    /* Enable the TIM Update interrupt */
 358    __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 359
 360    /* Enable the Peripheral */
 361   __HAL_TIM_ENABLE(htim);
 362
 363   /* Return function status */
 364   return HAL_OK;
 365 }
 366
 367 /**
 368   * @brief  Stops the TIM Base generation in interrupt mode.
 369   * @param  htim : TIM handle
 370   * @retval HAL status
 371 */
 372 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
 373 {
 374   /* Check the parameters */
 375   assert_param(IS_TIM_INSTANCE(htim->Instance));
 376   /* Disable the TIM Update interrupt */
 377   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
 378
 379   /* Disable the Peripheral */
 380   __HAL_TIM_DISABLE(htim);
 381
 382   /* Return function status */
 383   return HAL_OK;
 384 }
 385
 386 /**
 387   * @brief  Starts the TIM Base generation in DMA mode.
 388   * @param  htim : TIM handle
 389   * @param  pData: The source Buffer address.
 390   * @param  Length: The length of data to be transferred from memory to peripheral.
 391   * @retval HAL status
 392 */
 393 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
 394 {
 395   /* Check the parameters */
 396   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
 397
 398   if((htim->State == HAL_TIM_STATE_BUSY))
 399   {
 400      return HAL_BUSY;
 401   }
 402   else if((htim->State == HAL_TIM_STATE_READY))
 403   {
 404     if((pData == 0 ) && (Length > 0))
 405     {
 406       return HAL_ERROR;
 407     }
 408     else
 409     {
 410       htim->State = HAL_TIM_STATE_BUSY;
 411     }
 412   }
 413   else
 414   {
 415     return HAL_ERROR;
 416   }
 417
 418   /* Set the DMA Period elapsed callback */
 419   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
 420
 421   /* Set the DMA error callback */
 422   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
 423
 424   /* Enable the DMA channel */
 425   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
 426
 427   /* Enable the TIM Update DMA request */
 428   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
 429
 430   /* Enable the Peripheral */
 431   __HAL_TIM_ENABLE(htim);
 432
 433   /* Return function status */
 434   return HAL_OK;
 435 }
 436
 437 /**
 438   * @brief  Stops the TIM Base generation in DMA mode.
 439   * @param  htim : TIM handle
 440   * @retval HAL status
 441 */
 442 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
 443 {
 444   /* Check the parameters */
 445   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
 446
 447   /* Disable the TIM Update DMA request */
 448   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
 449
 450   /* Disable the Peripheral */
 451   __HAL_TIM_DISABLE(htim);
 452
 453   /* Change the htim state */
 454   htim->State = HAL_TIM_STATE_READY;
 455
 456   /* Return function status */
 457   return HAL_OK;
 458 }
 459
 460 /**
 461   * @}
 462   */
 463
 464 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
 465  *  @brief    Time Output Compare functions
 466  *
 467 @verbatim
 468   ==============================================================================
 469                   ##### Time Output Compare functions #####
 470   ==============================================================================
 471   [..]
 472     This section provides functions allowing to:
 473     (+) Initialize and configure the TIM Output Compare.
 474     (+) De-initialize the TIM Output Compare.
 475     (+) Start the Time Output Compare.
 476     (+) Stop the Time Output Compare.
 477     (+) Start the Time Output Compare and enable interrupt.
 478     (+) Stop the Time Output Compare and disable interrupt.
 479     (+) Start the Time Output Compare and enable DMA transfer.
 480     (+) Stop the Time Output Compare and disable DMA transfer.
 481
 482 @endverbatim
 483   * @{
 484   */
 485 /**
 486   * @brief  Initializes the TIM Output Compare according to the specified
 487   *         parameters in the TIM_HandleTypeDef and create the associated handle.
 488   * @param  htim: TIM Output Compare handle
 489   * @retval HAL status
 490   */
 491 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
 492 {
 493   /* Check the TIM handle allocation */
 494   if(htim == HAL_NULL)
 495   {
 496     return HAL_ERROR;
 497   }
 498
 499   /* Check the parameters */
 500   assert_param(IS_TIM_INSTANCE(htim->Instance));
 501   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
 502   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
 503
 504   if(htim->State == HAL_TIM_STATE_RESET)
 505   {
 506     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
 507     HAL_TIM_OC_MspInit(htim);
 508   }
 509
 510   /* Set the TIM state */
 511   htim->State= HAL_TIM_STATE_BUSY;
 512
 513   /* Init the base time for the Output Compare */
 514   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
 515
 516   /* Initialize the TIM state*/
 517   htim->State= HAL_TIM_STATE_READY;
 518
 519   return HAL_OK;
 520 }
 521
 522 /**
 523   * @brief  DeInitializes the TIM peripheral
 524   * @param  htim: TIM Output Compare handle
 525   * @retval HAL status
 526   */
 527 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
 528 {
 529   /* Check the parameters */
 530   assert_param(IS_TIM_INSTANCE(htim->Instance));
 531
 532    htim->State = HAL_TIM_STATE_BUSY;
 533
 534   /* Disable the TIM Peripheral Clock */
 535   __HAL_TIM_DISABLE(htim);
 536
 537   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
 538   HAL_TIM_OC_MspDeInit(htim);
 539
 540   /* Change TIM state */
 541   htim->State = HAL_TIM_STATE_RESET;
 542
 543   /* Release Lock */
 544   __HAL_UNLOCK(htim);
 545
 546   return HAL_OK;
 547 }
 548
 549 /**
 550   * @brief  Initializes the TIM Output Compare MSP.
 551   * @param  htim: TIM handle
 552   * @retval None
 553   */
 554 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
 555 {
 556   /* NOTE : This function Should not be modified, when the callback is needed,
 557             the HAL_TIM_OC_MspInit could be implemented in the user file
 558    */
 559 }
 560
 561 /**
 562   * @brief  DeInitializes TIM Output Compare MSP.
 563   * @param  htim: TIM handle
 564   * @retval None
 565   */
 566 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
 567 {
 568   /* NOTE : This function Should not be modified, when the callback is needed,
 569             the HAL_TIM_OC_MspDeInit could be implemented in the user file
 570    */
 571 }
 572
 573 /**
 574   * @brief  Starts the TIM Output Compare signal generation.
 575   * @param  htim : TIM Output Compare handle
 576   * @param  Channel : TIM Channel to be enabled
 577   *          This parameter can be one of the following values:
 578   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 579   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 580   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 581   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 582   * @retval HAL status
 583 */
 584 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
 585 {
 586   /* Check the parameters */
 587   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
 588
 589   /* Enable the Output compare channel */
 590   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 591
 592   /* Enable the Peripheral */
 593   __HAL_TIM_ENABLE(htim);
 594
 595   /* Return function status */
 596   return HAL_OK;
 597 }
 598
 599 /**
 600   * @brief  Stops the TIM Output Compare signal generation.
 601   * @param  htim : TIM handle
 602   * @param  Channel : TIM Channel to be disabled
 603   *          This parameter can be one of the following values:
 604   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 605   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 606   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 607   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 608   * @retval HAL status
 609 */
 610 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
 611 {
 612   /* Check the parameters */
 613   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
 614
 615   /* Disable the Output compare channel */
 616   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
 617
 618   /* Disable the Peripheral */
 619   __HAL_TIM_DISABLE(htim);
 620
 621   /* Return function status */
 622   return HAL_OK;
 623 }
 624
 625 /**
 626   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
 627   * @param  htim : TIM OC handle
 628   * @param  Channel : TIM Channel to be enabled
 629   *          This parameter can be one of the following values:
 630   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 631   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 632   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 633   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 634   * @retval HAL status
 635 */
 636 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 637 {
 638   /* Check the parameters */
 639   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
 640
 641   switch (Channel)
 642   {
 643     case TIM_CHANNEL_1:
 644     {
 645       /* Enable the TIM Capture/Compare 1 interrupt */
 646       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
 647     }
 648     break;
 649
 650     case TIM_CHANNEL_2:
 651     {
 652       /* Enable the TIM Capture/Compare 2 interrupt */
 653       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
 654     }
 655     break;
 656
 657     case TIM_CHANNEL_3:
 658     {
 659       /* Enable the TIM Capture/Compare 3 interrupt */
 660       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
 661     }
 662     break;
 663
 664     case TIM_CHANNEL_4:
 665     {
 666       /* Enable the TIM Capture/Compare 4 interrupt */
 667       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
 668     }
 669     break;
 670
 671     default:
 672     break;
 673   }
 674
 675   /* Enable the Output compare channel */
 676   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 677
 678   /* Enable the Peripheral */
 679   __HAL_TIM_ENABLE(htim);
 680
 681   /* Return function status */
 682   return HAL_OK;
 683 }
 684
 685 /**
 686   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
 687   * @param  htim : TIM Output Compare handle
 688   * @param  Channel : TIM Channel to be disabled
 689   *          This parameter can be one of the following values:
 690   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 691   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 692   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 693   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 694   * @retval HAL status
 695 */
 696 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 697 {
 698   /* Check the parameters */
 699   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
 700
 701   switch (Channel)
 702   {
 703     case TIM_CHANNEL_1:
 704     {
 705       /* Disable the TIM Capture/Compare 1 interrupt */
 706       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
 707     }
 708     break;
 709
 710     case TIM_CHANNEL_2:
 711     {
 712       /* Disable the TIM Capture/Compare 2 interrupt */
 713       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
 714     }
 715     break;
 716
 717     case TIM_CHANNEL_3:
 718     {
 719       /* Disable the TIM Capture/Compare 3 interrupt */
 720       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
 721     }
 722     break;
 723
 724     case TIM_CHANNEL_4:
 725     {
 726       /* Disable the TIM Capture/Compare 4 interrupt */
 727       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
 728     }
 729     break;
 730
 731     default:
 732     break;
 733   }
 734
 735   /* Disable the Output compare channel */
 736   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
 737
 738   /* Disable the Peripheral */
 739   __HAL_TIM_DISABLE(htim);
 740
 741   /* Return function status */
 742   return HAL_OK;
 743 }
 744
 745 /**
 746   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
 747   * @param  htim : TIM Output Compare handle
 748   * @param  Channel : TIM Channel to be enabled
 749   *          This parameter can be one of the following values:
 750   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 751   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 752   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 753   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 754   * @param  pData: The source Buffer address.
 755   * @param  Length: The length of data to be transferred from memory to TIM peripheral
 756   * @retval HAL status
 757 */
 758 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
 759 {
 760   /* Check the parameters */
 761   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
 762
 763   if((htim->State == HAL_TIM_STATE_BUSY))
 764   {
 765      return HAL_BUSY;
 766   }
 767   else if((htim->State == HAL_TIM_STATE_READY))
 768   {
 769     if(((uint32_t)pData == 0 ) && (Length > 0))
 770     {
 771       return HAL_ERROR;
 772     }
 773     else
 774     {
 775       htim->State = HAL_TIM_STATE_BUSY;
 776     }
 777   }
 778   else
 779   {
 780     return HAL_ERROR;
 781   }
 782
 783   switch (Channel)
 784   {
 785     case TIM_CHANNEL_1:
 786     {
 787       /* Set the DMA Period elapsed callback */
 788       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
 789
 790       /* Set the DMA error callback */
 791       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 792
 793       /* Enable the DMA channel */
 794       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
 795
 796       /* Enable the TIM Capture/Compare 1 DMA request */
 797       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
 798     }
 799     break;
 800
 801     case TIM_CHANNEL_2:
 802     {
 803       /* Set the DMA Period elapsed callback */
 804       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
 805
 806       /* Set the DMA error callback */
 807       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 808
 809       /* Enable the DMA channel */
 810       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
 811
 812       /* Enable the TIM Capture/Compare 2 DMA request */
 813       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
 814     }
 815     break;
 816
 817     case TIM_CHANNEL_3:
 818     {
 819       /* Set the DMA Period elapsed callback */
 820       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
 821
 822       /* Set the DMA error callback */
 823       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
 824
 825       /* Enable the DMA channel */
 826       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
 827
 828       /* Enable the TIM Capture/Compare 3 DMA request */
 829       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
 830     }
 831     break;
 832
 833     case TIM_CHANNEL_4:
 834     {
 835      /* Set the DMA Period elapsed callback */
 836       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
 837
 838       /* Set the DMA error callback */
 839       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
 840
 841       /* Enable the DMA channel */
 842       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
 843
 844       /* Enable the TIM Capture/Compare 4 DMA request */
 845       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
 846     }
 847     break;
 848
 849     default:
 850     break;
 851   }
 852
 853   /* Enable the Output compare channel */
 854   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 855
 856   /* Enable the Peripheral */
 857   __HAL_TIM_ENABLE(htim);
 858
 859   /* Return function status */
 860   return HAL_OK;
 861 }
 862
 863 /**
 864   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
 865   * @param  htim : TIM Output Compare handle
 866   * @param  Channel : TIM Channel to be disabled
 867   *          This parameter can be one of the following values:
 868   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 869   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 870   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 871   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 872   * @retval HAL status
 873 */
 874 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 875 {
 876   /* Check the parameters */
 877   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
 878
 879   switch (Channel)
 880   {
 881     case TIM_CHANNEL_1:
 882     {
 883       /* Disable the TIM Capture/Compare 1 DMA request */
 884       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
 885     }
 886     break;
 887
 888     case TIM_CHANNEL_2:
 889     {
 890       /* Disable the TIM Capture/Compare 2 DMA request */
 891       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
 892     }
 893     break;
 894
 895     case TIM_CHANNEL_3:
 896     {
 897       /* Disable the TIM Capture/Compare 3 DMA request */
 898       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
 899     }
 900     break;
 901
 902     case TIM_CHANNEL_4:
 903     {
 904       /* Disable the TIM Capture/Compare 4 interrupt */
 905       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
 906     }
 907     break;
 908
 909     default:
 910     break;
 911   }
 912
 913   /* Disable the Output compare channel */
 914   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
 915
 916   /* Disable the Peripheral */
 917   __HAL_TIM_DISABLE(htim);
 918
 919   /* Change the htim state */
 920   htim->State = HAL_TIM_STATE_READY;
 921
 922   /* Return function status */
 923   return HAL_OK;
 924 }
 925
 926 /**
 927   * @}
 928   */
 929
 930 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
 931  *  @brief    Time PWM functions
 932  *
 933 @verbatim
 934   ==============================================================================
 935                           ##### Time PWM functions #####
 936   ==============================================================================
 937   [..]
 938     This section provides functions allowing to:
 939     (+) Initialize and configure the TIM OPWM.
 940     (+) De-initialize the TIM PWM.
 941     (+) Start the Time PWM.
 942     (+) Stop the Time PWM.
 943     (+) Start the Time PWM and enable interrupt.
 944     (+) Stop the Time PWM and disable interrupt.
 945     (+) Start the Time PWM and enable DMA transfer.
 946     (+) Stop the Time PWM and disable DMA transfer.
 947
 948 @endverbatim
 949   * @{
 950   */
 951 /**
 952   * @brief  Initializes the TIM PWM Time Base according to the specified
 953   *         parameters in the TIM_HandleTypeDef and create the associated handle.
 954   * @param  htim: TIM handle
 955   * @retval HAL status
 956   */
 957 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
 958 {
 959   /* Check the TIM handle allocation */
 960   if(htim == HAL_NULL)
 961   {
 962     return HAL_ERROR;
 963   }
 964
 965   /* Check the parameters */
 966   assert_param(IS_TIM_INSTANCE(htim->Instance));
 967   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
 968   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
 969
 970   if(htim->State == HAL_TIM_STATE_RESET)
 971   {
 972     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
 973     HAL_TIM_PWM_MspInit(htim);
 974   }
 975
 976   /* Set the TIM state */
 977   htim->State= HAL_TIM_STATE_BUSY;
 978
 979   /* Init the base time for the PWM */
 980   TIM_Base_SetConfig(htim->Instance, &htim->Init);
 981
 982   /* Initialize the TIM state*/
 983   htim->State= HAL_TIM_STATE_READY;
 984
 985   return HAL_OK;
 986 }
 987
 988 /**
 989   * @brief  DeInitializes the TIM peripheral
 990   * @param  htim: TIM handle
 991   * @retval HAL status
 992   */
 993 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
 994 {
 995   /* Check the parameters */
 996   assert_param(IS_TIM_INSTANCE(htim->Instance));
 997
 998   htim->State = HAL_TIM_STATE_BUSY;
 999
1000   /* Disable the TIM Peripheral Clock */
1001   __HAL_TIM_DISABLE(htim);
1002
1003   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1004   HAL_TIM_PWM_MspDeInit(htim);
1005
1006   /* Change TIM state */
1007   htim->State = HAL_TIM_STATE_RESET;
1008
1009   /* Release Lock */
1010   __HAL_UNLOCK(htim);
1011
1012   return HAL_OK;
1013 }
1014
1015 /**
1016   * @brief  Initializes the TIM PWM MSP.
1017   * @param  htim: TIM handle
1018   * @retval None
1019   */
1020 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1021 {
1022   /* NOTE : This function Should not be modified, when the callback is needed,
1023             the HAL_TIM_PWM_MspInit could be implemented in the user file
1024    */
1025 }
1026
1027 /**
1028   * @brief  DeInitializes TIM PWM MSP.
1029   * @param  htim: TIM handle
1030   * @retval None
1031   */
1032 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1033 {
1034   /* NOTE : This function Should not be modified, when the callback is needed,
1035             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1036    */
1037 }
1038
1039 /**
1040   * @brief  Starts the PWM signal generation.
1041   * @param  htim : TIM handle
1042   * @param  Channel : TIM Channels to be enabled
1043   *          This parameter can be one of the following values:
1044   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1045   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1046   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1047   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1048   * @retval HAL status
1049 */
1050 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1051 {
1052   /* Check the parameters */
1053   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1054
1055   /* Enable the Capture compare channel */
1056   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1057
1058   /* Enable the Peripheral */
1059   __HAL_TIM_ENABLE(htim);
1060
1061   /* Return function status */
1062   return HAL_OK;
1063 }
1064
1065 /**
1066   * @brief  Stops the PWM signal generation.
1067   * @param  htim : TIM handle
1068   * @param  Channel : TIM Channels to be disabled
1069   *          This parameter can be one of the following values:
1070   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1071   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1072   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1073   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1074   * @retval HAL status
1075 */
1076 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1077 {
1078   /* Check the parameters */
1079   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1080
1081   /* Disable the Capture compare channel */
1082   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1083
1084   /* Disable the Peripheral */
1085   __HAL_TIM_DISABLE(htim);
1086
1087   /* Change the htim state */
1088   htim->State = HAL_TIM_STATE_READY;
1089
1090   /* Return function status */
1091   return HAL_OK;
1092 }
1093
1094 /**
1095   * @brief  Starts the PWM signal generation in interrupt mode.
1096   * @param  htim : TIM handle
1097   * @param  Channel : TIM Channel to be disabled
1098   *          This parameter can be one of the following values:
1099   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1100   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1101   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1102   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1103   * @retval HAL status
1104 */
1105 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1106 {
1107   /* Check the parameters */
1108   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1109
1110   switch (Channel)
1111   {
1112     case TIM_CHANNEL_1:
1113     {
1114       /* Enable the TIM Capture/Compare 1 interrupt */
1115       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1116     }
1117     break;
1118
1119     case TIM_CHANNEL_2:
1120     {
1121       /* Enable the TIM Capture/Compare 2 interrupt */
1122       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1123     }
1124     break;
1125
1126     case TIM_CHANNEL_3:
1127     {
1128       /* Enable the TIM Capture/Compare 3 interrupt */
1129       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1130     }
1131     break;
1132
1133     case TIM_CHANNEL_4:
1134     {
1135       /* Enable the TIM Capture/Compare 4 interrupt */
1136       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1137     }
1138     break;
1139
1140     default:
1141     break;
1142   }
1143
1144   /* Enable the Capture compare channel */
1145   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1146
1147   /* Enable the Peripheral */
1148   __HAL_TIM_ENABLE(htim);
1149
1150   /* Return function status */
1151   return HAL_OK;
1152 }
1153
1154 /**
1155   * @brief  Stops the PWM signal generation in interrupt mode.
1156   * @param  htim : TIM handle
1157   * @param  Channel : TIM Channels to be disabled
1158   *          This parameter can be one of the following values:
1159   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1160   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1161   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1162   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1163   * @retval HAL status
1164 */
1165 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1166 {
1167   /* Check the parameters */
1168   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1169
1170   switch (Channel)
1171   {
1172     case TIM_CHANNEL_1:
1173     {
1174       /* Disable the TIM Capture/Compare 1 interrupt */
1175       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1176     }
1177     break;
1178
1179     case TIM_CHANNEL_2:
1180     {
1181       /* Disable the TIM Capture/Compare 2 interrupt */
1182       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1183     }
1184     break;
1185
1186     case TIM_CHANNEL_3:
1187     {
1188       /* Disable the TIM Capture/Compare 3 interrupt */
1189       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1190     }
1191     break;
1192
1193     case TIM_CHANNEL_4:
1194     {
1195       /* Disable the TIM Capture/Compare 4 interrupt */
1196       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1197     }
1198     break;
1199
1200     default:
1201     break;
1202   }
1203
1204   /* Disable the Capture compare channel */
1205   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1206
1207
1208   /* Disable the Peripheral */
1209   __HAL_TIM_DISABLE(htim);
1210
1211   /* Return function status */
1212   return HAL_OK;
1213 }
1214
1215 /**
1216   * @brief  Starts the TIM PWM signal generation in DMA mode.
1217   * @param  htim : TIM handle
1218   * @param  Channel : TIM Channels to be enabled
1219   *          This parameter can be one of the following values:
1220   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1221   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1222   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1223   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1224   * @param  pData: The source Buffer address.
1225   * @param  Length: The length of data to be transferred from memory to TIM peripheral
1226   * @retval HAL status
1227 */
1228 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1229 {
1230   /* Check the parameters */
1231   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1232
1233   if((htim->State == HAL_TIM_STATE_BUSY))
1234   {
1235      return HAL_BUSY;
1236   }
1237   else if((htim->State == HAL_TIM_STATE_READY))
1238   {
1239     if(((uint32_t)pData == 0 ) && (Length > 0))
1240     {
1241       return HAL_ERROR;
1242     }
1243     else
1244     {
1245       htim->State = HAL_TIM_STATE_BUSY;
1246     }
1247   }
1248   else
1249   {
1250     return HAL_ERROR;
1251   }
1252
1253   switch (Channel)
1254   {
1255     case TIM_CHANNEL_1:
1256     {
1257       /* Set the DMA Period elapsed callback */
1258       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1259
1260       /* Set the DMA error callback */
1261       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1262
1263       /* Enable the DMA channel */
1264       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1265
1266       /* Enable the TIM Capture/Compare 1 DMA request */
1267       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1268     }
1269     break;
1270
1271     case TIM_CHANNEL_2:
1272     {
1273       /* Set the DMA Period elapsed callback */
1274       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1275
1276       /* Set the DMA error callback */
1277       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1278
1279       /* Enable the DMA channel */
1280       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1281
1282       /* Enable the TIM Capture/Compare 2 DMA request */
1283       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1284     }
1285     break;
1286
1287     case TIM_CHANNEL_3:
1288     {
1289       /* Set the DMA Period elapsed callback */
1290       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1291
1292       /* Set the DMA error callback */
1293       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1294
1295       /* Enable the DMA channel */
1296       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1297
1298       /* Enable the TIM Output Capture/Compare 3 request */
1299       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1300     }
1301     break;
1302
1303     case TIM_CHANNEL_4:
1304     {
1305      /* Set the DMA Period elapsed callback */
1306       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1307
1308       /* Set the DMA error callback */
1309       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1310
1311       /* Enable the DMA channel */
1312       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1313
1314       /* Enable the TIM Capture/Compare 4 DMA request */
1315       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1316     }
1317     break;
1318
1319     default:
1320     break;
1321   }
1322
1323   /* Enable the Capture compare channel */
1324   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1325
1326   /* Enable the Peripheral */
1327   __HAL_TIM_ENABLE(htim);
1328
1329   /* Return function status */
1330   return HAL_OK;
1331 }
1332
1333 /**
1334   * @brief  Stops the TIM PWM signal generation in DMA mode.
1335   * @param  htim : TIM handle
1336   * @param  Channel : TIM Channels to be disabled
1337   *          This parameter can be one of the following values:
1338   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1339   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1340   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1341   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1342   * @retval HAL status
1343 */
1344 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1345 {
1346   /* Check the parameters */
1347   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1348
1349   switch (Channel)
1350   {
1351     case TIM_CHANNEL_1:
1352     {
1353       /* Disable the TIM Capture/Compare 1 DMA request */
1354       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1355     }
1356     break;
1357
1358     case TIM_CHANNEL_2:
1359     {
1360       /* Disable the TIM Capture/Compare 2 DMA request */
1361       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1362     }
1363     break;
1364
1365     case TIM_CHANNEL_3:
1366     {
1367       /* Disable the TIM Capture/Compare 3 DMA request */
1368       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1369     }
1370     break;
1371
1372     case TIM_CHANNEL_4:
1373     {
1374       /* Disable the TIM Capture/Compare 4 interrupt */
1375       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1376     }
1377     break;
1378
1379     default:
1380     break;
1381   }
1382
1383   /* Disable the Capture compare channel */
1384   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1385
1386   /* Disable the Peripheral */
1387   __HAL_TIM_DISABLE(htim);
1388
1389   /* Change the htim state */
1390   htim->State = HAL_TIM_STATE_READY;
1391
1392   /* Return function status */
1393   return HAL_OK;
1394 }
1395
1396 /**
1397   * @}
1398   */
1399
1400 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1401  *  @brief    Time Input Capture functions
1402  *
1403 @verbatim
1404   ==============================================================================
1405               ##### Time Input Capture functions #####
1406   ==============================================================================
1407  [..]
1408    This section provides functions allowing to:
1409    (+) Initialize and configure the TIM Input Capture.
1410    (+) De-initialize the TIM Input Capture.
1411    (+) Start the Time Input Capture.
1412    (+) Stop the Time Input Capture.
1413    (+) Start the Time Input Capture and enable interrupt.
1414    (+) Stop the Time Input Capture and disable interrupt.
1415    (+) Start the Time Input Capture and enable DMA transfer.
1416    (+) Stop the Time Input Capture and disable DMA transfer.
1417
1418 @endverbatim
1419   * @{
1420   */
1421 /**
1422   * @brief  Initializes the TIM Input Capture Time base according to the specified
1423   *         parameters in the TIM_HandleTypeDef and create the associated handle.
1424   * @param  htim: TIM Input Capture handle
1425   * @retval HAL status
1426   */
1427 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1428 {
1429   /* Check the TIM handle allocation */
1430   if(htim == HAL_NULL)
1431   {
1432     return HAL_ERROR;
1433   }
1434
1435   /* Check the parameters */
1436   assert_param(IS_TIM_INSTANCE(htim->Instance));
1437   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1438   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1439
1440   if(htim->State == HAL_TIM_STATE_RESET)
1441   {
1442     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1443     HAL_TIM_IC_MspInit(htim);
1444   }
1445
1446   /* Set the TIM state */
1447   htim->State= HAL_TIM_STATE_BUSY;
1448
1449   /* Init the base time for the input capture */
1450   TIM_Base_SetConfig(htim->Instance, &htim->Init);
1451
1452   /* Initialize the TIM state*/
1453   htim->State= HAL_TIM_STATE_READY;
1454
1455   return HAL_OK;
1456 }
1457
1458 /**
1459   * @brief  DeInitializes the TIM peripheral
1460   * @param  htim: TIM Input Capture handle
1461   * @retval HAL status
1462   */
1463 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1464 {
1465   /* Check the parameters */
1466   assert_param(IS_TIM_INSTANCE(htim->Instance));
1467
1468   htim->State = HAL_TIM_STATE_BUSY;
1469
1470   /* Disable the TIM Peripheral Clock */
1471   __HAL_TIM_DISABLE(htim);
1472
1473   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1474   HAL_TIM_IC_MspDeInit(htim);
1475
1476   /* Change TIM state */
1477   htim->State = HAL_TIM_STATE_RESET;
1478
1479   /* Release Lock */
1480   __HAL_UNLOCK(htim);
1481
1482   return HAL_OK;
1483 }
1484
1485 /**
1486   * @brief  Initializes the TIM INput Capture MSP.
1487   * @param  htim: TIM handle
1488   * @retval None
1489   */
1490 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1491 {
1492   /* NOTE : This function Should not be modified, when the callback is needed,
1493             the HAL_TIM_IC_MspInit could be implemented in the user file
1494    */
1495 }
1496
1497 /**
1498   * @brief  DeInitializes TIM Input Capture MSP.
1499   * @param  htim: TIM handle
1500   * @retval None
1501   */
1502 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1503 {
1504   /* NOTE : This function Should not be modified, when the callback is needed,
1505             the HAL_TIM_IC_MspDeInit could be implemented in the user file
1506    */
1507 }
1508
1509 /**
1510   * @brief  Starts the TIM Input Capture measurement.
1511   * @param  htim : TIM Input Capture handle
1512   * @param  Channel : TIM Channels to be enabled
1513   *          This parameter can be one of the following values:
1514   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1515   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1516   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1517   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1518   * @retval HAL status
1519 */
1520 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1521 {
1522   /* Check the parameters */
1523   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1524
1525   /* Enable the Input Capture channel */
1526   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1527
1528   /* Enable the Peripheral */
1529   __HAL_TIM_ENABLE(htim);
1530
1531   /* Return function status */
1532   return HAL_OK;
1533 }
1534
1535 /**
1536   * @brief  Stops the TIM Input Capture measurement.
1537   * @param  htim : TIM handle
1538   * @param  Channel : TIM Channels to be disabled
1539   *          This parameter can be one of the following values:
1540   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1541   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1542   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1543   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1544   * @retval HAL status
1545 */
1546 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1547 {
1548   /* Check the parameters */
1549   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1550
1551   /* Disable the Input Capture channel */
1552   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1553
1554   /* Disable the Peripheral */
1555   __HAL_TIM_DISABLE(htim);
1556
1557   /* Return function status */
1558   return HAL_OK;
1559 }
1560
1561 /**
1562   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
1563   * @param  htim : TIM Input Capture handle
1564   * @param  Channel : TIM Channels to be enabled
1565   *          This parameter can be one of the following values:
1566   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1567   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1568   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1569   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1570   * @retval HAL status
1571 */
1572 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1573 {
1574   /* Check the parameters */
1575   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1576
1577   switch (Channel)
1578   {
1579     case TIM_CHANNEL_1:
1580     {
1581       /* Enable the TIM Capture/Compare 1 interrupt */
1582       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1583     }
1584     break;
1585
1586     case TIM_CHANNEL_2:
1587     {
1588       /* Enable the TIM Capture/Compare 2 interrupt */
1589       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1590     }
1591     break;
1592
1593     case TIM_CHANNEL_3:
1594     {
1595       /* Enable the TIM Capture/Compare 3 interrupt */
1596       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1597     }
1598     break;
1599
1600     case TIM_CHANNEL_4:
1601     {
1602       /* Enable the TIM Capture/Compare 4 interrupt */
1603       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1604     }
1605     break;
1606
1607     default:
1608     break;
1609   }
1610   /* Enable the Input Capture channel */
1611   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1612
1613   /* Enable the Peripheral */
1614   __HAL_TIM_ENABLE(htim);
1615
1616   /* Return function status */
1617   return HAL_OK;
1618 }
1619
1620 /**
1621   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
1622   * @param  htim : TIM handle
1623   * @param  Channel : TIM Channels to be disabled
1624   *          This parameter can be one of the following values:
1625   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1626   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1627   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1628   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1629   * @retval HAL status
1630 */
1631 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1632 {
1633   /* Check the parameters */
1634   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1635
1636   switch (Channel)
1637   {
1638     case TIM_CHANNEL_1:
1639     {
1640       /* Disable the TIM Capture/Compare 1 interrupt */
1641       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1642     }
1643     break;
1644
1645     case TIM_CHANNEL_2:
1646     {
1647       /* Disable the TIM Capture/Compare 2 interrupt */
1648       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1649     }
1650     break;
1651
1652     case TIM_CHANNEL_3:
1653     {
1654       /* Disable the TIM Capture/Compare 3 interrupt */
1655       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1656     }
1657     break;
1658
1659     case TIM_CHANNEL_4:
1660     {
1661       /* Disable the TIM Capture/Compare 4 interrupt */
1662       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1663     }
1664     break;
1665
1666     default:
1667     break;
1668   }
1669
1670   /* Disable the Input Capture channel */
1671   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1672
1673   /* Disable the Peripheral */
1674   __HAL_TIM_DISABLE(htim);
1675
1676   /* Return function status */
1677   return HAL_OK;
1678 }
1679
1680 /**
1681   * @brief  Starts the TIM Input Capture measurement on in DMA mode.
1682   * @param  htim : TIM Input Capture handle
1683   * @param  Channel : TIM Channels to be enabled
1684   *          This parameter can be one of the following values:
1685   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1686   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1687   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1688   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1689   * @param  pData: The destination Buffer address.
1690   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
1691   * @retval HAL status
1692 */
1693 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1694 {
1695   /* Check the parameters */
1696   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1697   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1698
1699   if((htim->State == HAL_TIM_STATE_BUSY))
1700   {
1701      return HAL_BUSY;
1702   }
1703   else if((htim->State == HAL_TIM_STATE_READY))
1704   {
1705     if((pData == 0 ) && (Length > 0))
1706     {
1707       return HAL_ERROR;
1708     }
1709     else
1710     {
1711       htim->State = HAL_TIM_STATE_BUSY;
1712     }
1713   }
1714   else
1715   {
1716     return HAL_ERROR;
1717   }
1718
1719   switch (Channel)
1720   {
1721     case TIM_CHANNEL_1:
1722     {
1723       /* Set the DMA Period elapsed callback */
1724       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
1725
1726       /* Set the DMA error callback */
1727       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1728
1729       /* Enable the DMA channel */
1730       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1731
1732       /* Enable the TIM Capture/Compare 1 DMA request */
1733       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1734     }
1735     break;
1736
1737     case TIM_CHANNEL_2:
1738     {
1739       /* Set the DMA Period elapsed callback */
1740       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
1741
1742       /* Set the DMA error callback */
1743       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1744
1745       /* Enable the DMA channel */
1746       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1747
1748       /* Enable the TIM Capture/Compare 2  DMA request */
1749       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1750     }
1751     break;
1752
1753     case TIM_CHANNEL_3:
1754     {
1755       /* Set the DMA Period elapsed callback */
1756       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
1757
1758       /* Set the DMA error callback */
1759       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1760
1761       /* Enable the DMA channel */
1762       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1763
1764       /* Enable the TIM Capture/Compare 3  DMA request */
1765       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1766     }
1767     break;
1768
1769     case TIM_CHANNEL_4:
1770     {
1771       /* Set the DMA Period elapsed callback */
1772       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
1773
1774       /* Set the DMA error callback */
1775       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1776
1777       /* Enable the DMA channel */
1778       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1779
1780       /* Enable the TIM Capture/Compare 4  DMA request */
1781       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1782     }
1783     break;
1784
1785     default:
1786     break;
1787   }
1788
1789   /* Enable the Input Capture channel */
1790   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1791
1792   /* Enable the Peripheral */
1793   __HAL_TIM_ENABLE(htim);
1794
1795   /* Return function status */
1796   return HAL_OK;
1797 }
1798
1799 /**
1800   * @brief  Stops the TIM Input Capture measurement on in DMA mode.
1801   * @param  htim : TIM Input Capture handle
1802   * @param  Channel : TIM Channels to be disabled
1803   *          This parameter can be one of the following values:
1804   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1805   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1806   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1807   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1808   * @retval HAL status
1809 */
1810 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1811 {
1812   /* Check the parameters */
1813   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1814   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1815
1816   switch (Channel)
1817   {
1818     case TIM_CHANNEL_1:
1819     {
1820       /* Disable the TIM Capture/Compare 1 DMA request */
1821       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1822     }
1823     break;
1824
1825     case TIM_CHANNEL_2:
1826     {
1827       /* Disable the TIM Capture/Compare 2 DMA request */
1828       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1829     }
1830     break;
1831
1832     case TIM_CHANNEL_3:
1833     {
1834       /* Disable the TIM Capture/Compare 3  DMA request */
1835       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1836     }
1837     break;
1838
1839     case TIM_CHANNEL_4:
1840     {
1841       /* Disable the TIM Capture/Compare 4  DMA request */
1842       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1843     }
1844     break;
1845
1846     default:
1847     break;
1848   }
1849
1850   /* Disable the Input Capture channel */
1851   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1852
1853   /* Disable the Peripheral */
1854   __HAL_TIM_DISABLE(htim);
1855
1856   /* Change the htim state */
1857   htim->State = HAL_TIM_STATE_READY;
1858
1859   /* Return function status */
1860   return HAL_OK;
1861 }
1862 /**
1863   * @}
1864   */
1865
1866 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1867  *  @brief    Time One Pulse functions
1868  *
1869 @verbatim
1870   ==============================================================================
1871                         ##### Time One Pulse functions #####
1872   ==============================================================================
1873   [..]
1874     This section provides functions allowing to:
1875     (+) Initialize and configure the TIM One Pulse.
1876     (+) De-initialize the TIM One Pulse.
1877     (+) Start the Time One Pulse.
1878     (+) Stop the Time One Pulse.
1879     (+) Start the Time One Pulse and enable interrupt.
1880     (+) Stop the Time One Pulse and disable interrupt.
1881     (+) Start the Time One Pulse and enable DMA transfer.
1882     (+) Stop the Time One Pulse and disable DMA transfer.
1883
1884 @endverbatim
1885   * @{
1886   */
1887 /**
1888   * @brief  Initializes the TIM One Pulse Time Base according to the specified
1889   *         parameters in the TIM_HandleTypeDef and create the associated handle.
1890   * @param  htim: TIM OnePulse handle
1891   * @param  OnePulseMode: Select the One pulse mode.
1892   *         This parameter can be one of the following values:
1893   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1894   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
1895   * @retval HAL status
1896   */
1897 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1898 {
1899   /* Check the TIM handle allocation */
1900   if(htim == HAL_NULL)
1901   {
1902     return HAL_ERROR;
1903   }
1904
1905   /* Check the parameters */
1906   assert_param(IS_TIM_INSTANCE(htim->Instance));
1907   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1908   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1909   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1910
1911   if(htim->State == HAL_TIM_STATE_RESET)
1912   {
1913     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1914     HAL_TIM_OnePulse_MspInit(htim);
1915   }
1916
1917   /* Set the TIM state */
1918   htim->State= HAL_TIM_STATE_BUSY;
1919
1920   /* Configure the Time base in the One Pulse Mode */
1921   TIM_Base_SetConfig(htim->Instance, &htim->Init);
1922
1923   /* Reset the OPM Bit */
1924   htim->Instance->CR1 &= ~TIM_CR1_OPM;
1925
1926   /* Configure the OPM Mode */
1927   htim->Instance->CR1 |= OnePulseMode;
1928
1929   /* Initialize the TIM state*/
1930   htim->State= HAL_TIM_STATE_READY;
1931
1932   return HAL_OK;
1933 }
1934
1935 /**
1936   * @brief  DeInitializes the TIM One Pulse
1937   * @param  htim: TIM One Pulse handle
1938   * @retval HAL status
1939   */
1940 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
1941 {
1942   /* Check the parameters */
1943   assert_param(IS_TIM_INSTANCE(htim->Instance));
1944
1945   htim->State = HAL_TIM_STATE_BUSY;
1946
1947   /* Disable the TIM Peripheral Clock */
1948   __HAL_TIM_DISABLE(htim);
1949
1950   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
1951   HAL_TIM_OnePulse_MspDeInit(htim);
1952
1953   /* Change TIM state */
1954   htim->State = HAL_TIM_STATE_RESET;
1955
1956   /* Release Lock */
1957   __HAL_UNLOCK(htim);
1958
1959   return HAL_OK;
1960 }
1961
1962 /**
1963   * @brief  Initializes the TIM One Pulse MSP.
1964   * @param  htim: TIM handle
1965   * @retval None
1966   */
1967 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
1968 {
1969   /* NOTE : This function Should not be modified, when the callback is needed,
1970             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
1971    */
1972 }
1973
1974 /**
1975   * @brief  DeInitializes TIM One Pulse MSP.
1976   * @param  htim: TIM handle
1977   * @retval None
1978   */
1979 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
1980 {
1981   /* NOTE : This function Should not be modified, when the callback is needed,
1982             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
1983    */
1984 }
1985
1986 /**
1987   * @brief  Starts the TIM One Pulse signal generation.
1988   * @param  htim : TIM One Pulse handle
1989   * @param  OutputChannel : TIM Channels to be enabled
1990   *          This parameter can be one of the following values:
1991   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1992   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1993   * @retval HAL status
1994 */
1995 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1996 {
1997   /* Enable the Capture compare and the Input Capture channels
1998     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
1999     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2000     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2001     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2002
2003     No need to enable the counter, it's enabled automatically by hardware
2004     (the counter starts in response to a stimulus and generate a pulse */
2005
2006   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2007   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2008
2009   /* Return function status */
2010   return HAL_OK;
2011 }
2012
2013 /**
2014   * @brief  Stops the TIM One Pulse signal generation.
2015   * @param  htim : TIM One Pulse handle
2016   * @param  OutputChannel : TIM Channels to be disable
2017   *          This parameter can be one of the following values:
2018   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2019   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2020   * @retval HAL status
2021 */
2022 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2023 {
2024   /* Disable the Capture compare and the Input Capture channels
2025   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2026   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2027   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2028   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2029
2030   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2031   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2032
2033   /* Disable the Peripheral */
2034   __HAL_TIM_DISABLE(htim);
2035
2036   /* Return function status */
2037   return HAL_OK;
2038 }
2039
2040 /**
2041   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
2042   * @param  htim : TIM One Pulse handle
2043   * @param  OutputChannel : TIM Channels to be enabled
2044   *          This parameter can be one of the following values:
2045   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2046   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2047   * @retval HAL status
2048 */
2049 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2050 {
2051   /* Enable the Capture compare and the Input Capture channels
2052     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2053     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2054     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2055     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2056
2057     No need to enable the counter, it's enabled automatically by hardware
2058     (the counter starts in response to a stimulus and generate a pulse */
2059
2060   /* Enable the TIM Capture/Compare 1 interrupt */
2061   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2062
2063   /* Enable the TIM Capture/Compare 2 interrupt */
2064   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2065
2066   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2067   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2068
2069   /* Return function status */
2070   return HAL_OK;
2071 }
2072
2073 /**
2074   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
2075   * @param  htim : TIM One Pulse handle
2076   * @param  OutputChannel : TIM Channels to be enabled
2077   *          This parameter can be one of the following values:
2078   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2079   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2080   * @retval HAL status
2081 */
2082 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2083 {
2084   /* Disable the TIM Capture/Compare 1 interrupt */
2085   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2086
2087   /* Disable the TIM Capture/Compare 2 interrupt */
2088   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2089
2090   /* Disable the Capture compare and the Input Capture channels
2091   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2092   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2093   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2094   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2095   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2096   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2097
2098   /* Disable the Peripheral */
2099    __HAL_TIM_DISABLE(htim);
2100
2101   /* Return function status */
2102   return HAL_OK;
2103 }
2104
2105 /**
2106   * @}
2107   */
2108
2109 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2110  *  @brief    Time Encoder functions
2111  *
2112 @verbatim
2113   ==============================================================================
2114                           ##### Time Encoder functions #####
2115   ==============================================================================
2116   [..]
2117     This section provides functions allowing to:
2118     (+) Initialize and configure the TIM Encoder.
2119     (+) De-initialize the TIM Encoder.
2120     (+) Start the Time Encoder.
2121     (+) Stop the Time Encoder.
2122     (+) Start the Time Encoder and enable interrupt.
2123     (+) Stop the Time Encoder and disable interrupt.
2124     (+) Start the Time Encoder and enable DMA transfer.
2125     (+) Stop the Time Encoder and disable DMA transfer.
2126
2127 @endverbatim
2128   * @{
2129   */
2130 /**
2131   * @brief  Initializes the TIM Encoder Interface and create the associated handle.
2132   * @param  htim: TIM Encoder Interface handle
2133   * @param  sConfig: TIM Encoder Interface configuration structure
2134   * @retval HAL status
2135   */
2136 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
2137 {
2138   uint32_t tmpsmcr = 0;
2139   uint32_t tmpccmr1 = 0;
2140   uint32_t tmpccer = 0;
2141
2142   /* Check the TIM handle allocation */
2143   if(htim == HAL_NULL)
2144   {
2145     return HAL_ERROR;
2146   }
2147
2148   /* Check the parameters */
2149   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2150   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2151   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2152   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2153   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2154   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2155   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2156   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2157   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2158   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2159
2160   if(htim->State == HAL_TIM_STATE_RESET)
2161   {
2162     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2163     HAL_TIM_Encoder_MspInit(htim);
2164   }
2165
2166   /* Set the TIM state */
2167   htim->State= HAL_TIM_STATE_BUSY;
2168
2169   /* Reset the SMS bits */
2170   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2171
2172   /* Configure the Time base in the Encoder Mode */
2173   TIM_Base_SetConfig(htim->Instance, &htim->Init);
2174
2175   /* Get the TIMx SMCR register value */
2176   tmpsmcr = htim->Instance->SMCR;
2177
2178   /* Get the TIMx CCMR1 register value */
2179   tmpccmr1 = htim->Instance->CCMR1;
2180
2181   /* Get the TIMx CCER register value */
2182   tmpccer = htim->Instance->CCER;
2183
2184   /* Set the encoder Mode */
2185   tmpsmcr |= sConfig->EncoderMode;
2186
2187   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2188   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2189   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
2190
2191   /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2192   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2193   tmpccmr1 &= (~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F));
2194   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
2195   tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
2196
2197   /* Set the TI1 and the TI2 Polarities */
2198   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2199   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2200   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
2201
2202   /* Write to TIMx SMCR */
2203   htim->Instance->SMCR = tmpsmcr;
2204
2205   /* Write to TIMx CCMR1 */
2206   htim->Instance->CCMR1 = tmpccmr1;
2207
2208   /* Write to TIMx CCER */
2209   htim->Instance->CCER = tmpccer;
2210
2211   /* Initialize the TIM state*/
2212   htim->State= HAL_TIM_STATE_READY;
2213
2214   return HAL_OK;
2215 }
2216
2217
2218 /**
2219   * @brief  DeInitializes the TIM Encoder interface
2220   * @param  htim: TIM Encoder handle
2221   * @retval HAL status
2222   */
2223 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2224 {
2225   /* Check the parameters */
2226   assert_param(IS_TIM_INSTANCE(htim->Instance));
2227
2228   htim->State = HAL_TIM_STATE_BUSY;
2229
2230   /* Disable the TIM Peripheral Clock */
2231   __HAL_TIM_DISABLE(htim);
2232
2233   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2234   HAL_TIM_Encoder_MspDeInit(htim);
2235
2236   /* Change TIM state */
2237   htim->State = HAL_TIM_STATE_RESET;
2238
2239   /* Release Lock */
2240   __HAL_UNLOCK(htim);
2241
2242   return HAL_OK;
2243 }
2244
2245 /**
2246   * @brief  Initializes the TIM Encoder Interface MSP.
2247   * @param  htim: TIM handle
2248   * @retval None
2249   */
2250 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2251 {
2252   /* NOTE : This function Should not be modified, when the callback is needed,
2253             the HAL_TIM_Encoder_MspInit could be implemented in the user file
2254    */
2255 }
2256
2257 /**
2258   * @brief  DeInitializes TIM Encoder Interface MSP.
2259   * @param  htim: TIM handle
2260   * @retval None
2261   */
2262 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2263 {
2264   /* NOTE : This function Should not be modified, when the callback is needed,
2265             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2266    */
2267 }
2268
2269 /**
2270   * @brief  Starts the TIM Encoder Interface.
2271   * @param  htim : TIM Encoder Interface handle
2272   * @param  Channel : TIM Channels to be enabled
2273   *          This parameter can be one of the following values:
2274   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2275   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2276   * @retval HAL status
2277 */
2278 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2279 {
2280   /* Check the parameters */
2281   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2282
2283   /* Enable the encoder interface channels */
2284   switch (Channel)
2285   {
2286     case TIM_CHANNEL_1:
2287   {
2288     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2289       break;
2290   }
2291     case TIM_CHANNEL_2:
2292   {
2293     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2294       break;
2295   }
2296     default :
2297   {
2298      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2299      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2300      break;
2301     }
2302   }
2303   /* Enable the Peripheral */
2304   __HAL_TIM_ENABLE(htim);
2305
2306   /* Return function status */
2307   return HAL_OK;
2308 }
2309
2310 /**
2311   * @brief  Stops the TIM Encoder Interface.
2312   * @param  htim : TIM Encoder Interface handle
2313   * @param  Channel : TIM Channels to be disabled
2314   *          This parameter can be one of the following values:
2315   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2316   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2317   * @retval HAL status
2318 */
2319 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2320 {
2321   /* Check the parameters */
2322     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2323
2324    /* Disable the Input Capture channels 1 and 2
2325     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2326   switch (Channel)
2327   {
2328     case TIM_CHANNEL_1:
2329   {
2330      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2331       break;
2332   }
2333     case TIM_CHANNEL_2:
2334   {
2335     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2336       break;
2337   }
2338     default :
2339   {
2340     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2341     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2342      break;
2343     }
2344   }
2345
2346   /* Disable the Peripheral */
2347   __HAL_TIM_DISABLE(htim);
2348
2349   /* Return function status */
2350   return HAL_OK;
2351 }
2352
2353 /**
2354   * @brief  Starts the TIM Encoder Interface in interrupt mode.
2355   * @param  htim : TIM Encoder Interface handle
2356   * @param  Channel : TIM Channels to be enabled
2357   *          This parameter can be one of the following values:
2358   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2359   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2360   * @retval HAL status
2361 */
2362 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2363 {
2364   /* Check the parameters */
2365   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2366
2367   /* Enable the encoder interface channels */
2368   /* Enable the capture compare Interrupts 1 and/or 2 */
2369   switch (Channel)
2370   {
2371     case TIM_CHANNEL_1:
2372   {
2373     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2374     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2375       break;
2376   }
2377     case TIM_CHANNEL_2:
2378   {
2379     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2380     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2381       break;
2382   }
2383     default :
2384   {
2385      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2386      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2387      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2388      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2389      break;
2390     }
2391   }
2392
2393   /* Enable the Peripheral */
2394   __HAL_TIM_ENABLE(htim);
2395
2396   /* Return function status */
2397   return HAL_OK;
2398 }
2399
2400 /**
2401   * @brief  Stops the TIM Encoder Interface in interrupt mode.
2402   * @param  htim : TIM Encoder Interface handle
2403   * @param  Channel : TIM Channels to be disabled
2404   *          This parameter can be one of the following values:
2405   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2406   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2407   * @retval HAL status
2408 */
2409 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2410 {
2411   /* Check the parameters */
2412   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2413
2414   /* Disable the Input Capture channels 1 and 2
2415     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2416   if(Channel == TIM_CHANNEL_1)
2417   {
2418     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2419
2420     /* Disable the capture compare Interrupts 1 */
2421   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2422   }
2423   else if(Channel == TIM_CHANNEL_2)
2424   {
2425     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2426
2427     /* Disable the capture compare Interrupts 2 */
2428   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2429   }
2430   else
2431   {
2432     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2433     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2434
2435     /* Disable the capture compare Interrupts 1 and 2 */
2436     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2437     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2438   }
2439
2440   /* Disable the Peripheral */
2441   __HAL_TIM_DISABLE(htim);
2442
2443   /* Change the htim state */
2444   htim->State = HAL_TIM_STATE_READY;
2445
2446   /* Return function status */
2447   return HAL_OK;
2448 }
2449
2450 /**
2451   * @brief  Starts the TIM Encoder Interface in DMA mode.
2452   * @param  htim : TIM Encoder Interface handle
2453   * @param  Channel : TIM Channels to be enabled
2454   *          This parameter can be one of the following values:
2455   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2456   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2457   * @param  pData1: The destination Buffer address for IC1.
2458   * @param  pData2: The destination Buffer address for IC2.
2459   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
2460   * @retval HAL status
2461 */
2462 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2463 {
2464   /* Check the parameters */
2465   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2466
2467   if((htim->State == HAL_TIM_STATE_BUSY))
2468   {
2469      return HAL_BUSY;
2470   }
2471   else if((htim->State == HAL_TIM_STATE_READY))
2472   {
2473     if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
2474     {
2475       return HAL_ERROR;
2476     }
2477     else
2478     {
2479       htim->State = HAL_TIM_STATE_BUSY;
2480     }
2481   }
2482   else
2483   {
2484     return HAL_ERROR;
2485   }
2486
2487   switch (Channel)
2488   {
2489     case TIM_CHANNEL_1:
2490     {
2491       /* Set the DMA Period elapsed callback */
2492       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2493
2494       /* Set the DMA error callback */
2495       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2496
2497       /* Enable the DMA channel */
2498       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2499
2500       /* Enable the TIM Input Capture DMA request */
2501       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2502
2503       /* Enable the Peripheral */
2504       __HAL_TIM_ENABLE(htim);
2505
2506       /* Enable the Capture compare channel */
2507       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2508     }
2509     break;
2510
2511     case TIM_CHANNEL_2:
2512     {
2513       /* Set the DMA Period elapsed callback */
2514       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2515
2516       /* Set the DMA error callback */
2517       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
2518       /* Enable the DMA channel */
2519       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2520
2521       /* Enable the TIM Input Capture  DMA request */
2522       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2523
2524       /* Enable the Peripheral */
2525       __HAL_TIM_ENABLE(htim);
2526
2527       /* Enable the Capture compare channel */
2528       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2529     }
2530     break;
2531
2532     case TIM_CHANNEL_ALL:
2533     {
2534       /* Set the DMA Period elapsed callback */
2535       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2536
2537       /* Set the DMA error callback */
2538       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2539
2540       /* Enable the DMA channel */
2541       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2542
2543       /* Set the DMA Period elapsed callback */
2544       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2545
2546       /* Set the DMA error callback */
2547       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2548
2549       /* Enable the DMA channel */
2550       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2551
2552      /* Enable the Peripheral */
2553       __HAL_TIM_ENABLE(htim);
2554
2555       /* Enable the Capture compare channel */
2556       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2557       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2558
2559       /* Enable the TIM Input Capture  DMA request */
2560       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2561       /* Enable the TIM Input Capture  DMA request */
2562       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2563     }
2564     break;
2565
2566     default:
2567     break;
2568   }
2569   /* Return function status */
2570   return HAL_OK;
2571 }
2572
2573 /**
2574   * @brief  Stops the TIM Encoder Interface in DMA mode.
2575   * @param  htim : TIM Encoder Interface handle
2576   * @param  Channel : TIM Channels to be enabled
2577   *          This parameter can be one of the following values:
2578   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2579   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2580   * @retval HAL status
2581 */
2582 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2583 {
2584   /* Check the parameters */
2585   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2586
2587   /* Disable the Input Capture channels 1 and 2
2588     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2589   if(Channel == TIM_CHANNEL_1)
2590   {
2591     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2592
2593     /* Disable the capture compare DMA Request 1 */
2594     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2595   }
2596   else if(Channel == TIM_CHANNEL_2)
2597   {
2598     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2599
2600     /* Disable the capture compare DMA Request 2 */
2601     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2602   }
2603   else
2604   {
2605     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2606     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2607
2608     /* Disable the capture compare DMA Request 1 and 2 */
2609     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2610     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2611   }
2612
2613   /* Disable the Peripheral */
2614   __HAL_TIM_DISABLE(htim);
2615
2616   /* Change the htim state */
2617   htim->State = HAL_TIM_STATE_READY;
2618
2619   /* Return function status */
2620   return HAL_OK;
2621 }
2622
2623 /**
2624   * @}
2625   */
2626 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2627  *  @brief    IRQ handler management
2628  *
2629 @verbatim
2630   ==============================================================================
2631                         ##### IRQ handler management #####
2632   ==============================================================================
2633   [..]
2634     This section provides Timer IRQ handler function.
2635
2636 @endverbatim
2637   * @{
2638   */
2639 /**
2640   * @brief  This function handles TIM interrupts requests.
2641   * @param  htim: TIM  handle
2642   * @retval None
2643   */
2644 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2645 {
2646   /* Capture compare 1 event */
2647   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2648   {
2649     if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
2650     {
2651       {
2652         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2653         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2654
2655         /* Input capture event */
2656         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
2657         {
2658           HAL_TIM_IC_CaptureCallback(htim);
2659         }
2660         /* Output compare event */
2661         else
2662         {
2663           HAL_TIM_OC_DelayElapsedCallback(htim);
2664           HAL_TIM_PWM_PulseFinishedCallback(htim);
2665         }
2666         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2667       }
2668     }
2669   }
2670   /* Capture compare 2 event */
2671   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2672   {
2673     if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
2674     {
2675       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2676       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2677       /* Input capture event */
2678       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
2679       {
2680         HAL_TIM_IC_CaptureCallback(htim);
2681       }
2682       /* Output compare event */
2683       else
2684       {
2685         HAL_TIM_OC_DelayElapsedCallback(htim);
2686         HAL_TIM_PWM_PulseFinishedCallback(htim);
2687       }
2688       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2689     }
2690   }
2691   /* Capture compare 3 event */
2692   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2693   {
2694     if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
2695     {
2696       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2697       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2698       /* Input capture event */
2699       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
2700       {
2701         HAL_TIM_IC_CaptureCallback(htim);
2702       }
2703       /* Output compare event */
2704       else
2705       {
2706         HAL_TIM_OC_DelayElapsedCallback(htim);
2707         HAL_TIM_PWM_PulseFinishedCallback(htim);
2708       }
2709       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2710     }
2711   }
2712   /* Capture compare 4 event */
2713   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2714   {
2715     if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
2716     {
2717       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2718       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2719       /* Input capture event */
2720       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
2721       {
2722         HAL_TIM_IC_CaptureCallback(htim);
2723       }
2724       /* Output compare event */
2725       else
2726       {
2727         HAL_TIM_OC_DelayElapsedCallback(htim);
2728         HAL_TIM_PWM_PulseFinishedCallback(htim);
2729       }
2730       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2731     }
2732   }
2733   /* TIM Update event */
2734   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2735   {
2736     if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
2737     {
2738       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2739       HAL_TIM_PeriodElapsedCallback(htim);
2740     }
2741   }
2742   /* TIM Trigger detection event */
2743   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2744   {
2745     if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
2746     {
2747       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2748       HAL_TIM_TriggerCallback(htim);
2749     }
2750   }
2751 }
2752
2753 /**
2754   * @}
2755   */
2756
2757 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2758  *  @brief      Peripheral Control functions
2759  *
2760 @verbatim
2761   ==============================================================================
2762                    ##### Peripheral Control functions #####
2763   ==============================================================================
2764  [..]
2765    This section provides functions allowing to:
2766       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2767       (+) Configure External Clock source.
2768       (+) Configure Complementary channels, break features and dead time.
2769       (+) Configure Master and the Slave synchronization.
2770       (+) Configure the DMA Burst Mode.
2771
2772 @endverbatim
2773   * @{
2774   */
2775
2776 /**
2777   * @brief  Initializes the TIM Output Compare Channels according to the specified
2778   *         parameters in the TIM_OC_InitTypeDef.
2779   * @param  htim: TIM Output Compare handle
2780   * @param  sConfig: TIM Output Compare configuration structure
2781   * @param  Channel : TIM Channels to be enabled
2782   *          This parameter can be one of the following values:
2783   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2784   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2785   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2786   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2787   * @retval HAL status
2788   */
2789 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2790 {
2791   /* Check the parameters */
2792   assert_param(IS_TIM_CHANNELS(Channel));
2793   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2794   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2795   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
2796
2797   /* Check input state */
2798   __HAL_LOCK(htim);
2799
2800   htim->State = HAL_TIM_STATE_BUSY;
2801
2802   switch (Channel)
2803   {
2804     case TIM_CHANNEL_1:
2805     {
2806       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2807       /* Configure the TIM Channel 1 in Output Compare */
2808       TIM_OC1_SetConfig(htim->Instance, sConfig);
2809     }
2810     break;
2811
2812     case TIM_CHANNEL_2:
2813     {
2814       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2815       /* Configure the TIM Channel 2 in Output Compare */
2816       TIM_OC2_SetConfig(htim->Instance, sConfig);
2817     }
2818     break;
2819
2820     case TIM_CHANNEL_3:
2821     {
2822        assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2823       /* Configure the TIM Channel 3 in Output Compare */
2824       TIM_OC3_SetConfig(htim->Instance, sConfig);
2825     }
2826     break;
2827
2828     case TIM_CHANNEL_4:
2829     {
2830       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2831        /* Configure the TIM Channel 4 in Output Compare */
2832        TIM_OC4_SetConfig(htim->Instance, sConfig);
2833     }
2834     break;
2835
2836     default:
2837     break;
2838   }
2839   htim->State = HAL_TIM_STATE_READY;
2840
2841   __HAL_UNLOCK(htim);
2842
2843   return HAL_OK;
2844 }
2845
2846 /**
2847   * @brief  Initializes the TIM Input Capture Channels according to the specified
2848   *         parameters in the TIM_IC_InitTypeDef.
2849   * @param  htim: TIM IC handle
2850   * @param  sConfig: TIM Input Capture configuration structure
2851   * @param  Channel : TIM Channels to be enabled
2852   *          This parameter can be one of the following values:
2853   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2854   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2855   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2856   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2857   * @retval HAL status
2858   */
2859 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
2860 {
2861   /* Check the parameters */
2862   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2863   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
2864   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
2865   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
2866   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
2867
2868   __HAL_LOCK(htim);
2869
2870   htim->State = HAL_TIM_STATE_BUSY;
2871
2872   if (Channel == TIM_CHANNEL_1)
2873   {
2874     /* TI1 Configuration */
2875     TIM_TI1_SetConfig(htim->Instance,
2876                sConfig->ICPolarity,
2877                sConfig->ICSelection,
2878                sConfig->ICFilter);
2879
2880     /* Reset the IC1PSC Bits */
2881     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
2882
2883     /* Set the IC1PSC value */
2884     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
2885   }
2886   else if (Channel == TIM_CHANNEL_2)
2887   {
2888     /* TI2 Configuration */
2889     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2890
2891     TIM_TI2_SetConfig(htim->Instance,
2892                       sConfig->ICPolarity,
2893                       sConfig->ICSelection,
2894                       sConfig->ICFilter);
2895
2896     /* Reset the IC2PSC Bits */
2897     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
2898
2899     /* Set the IC2PSC value */
2900     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
2901   }
2902   else if (Channel == TIM_CHANNEL_3)
2903   {
2904     /* TI3 Configuration */
2905     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2906
2907     TIM_TI3_SetConfig(htim->Instance,
2908                sConfig->ICPolarity,
2909                sConfig->ICSelection,
2910                sConfig->ICFilter);
2911
2912     /* Reset the IC3PSC Bits */
2913     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
2914
2915     /* Set the IC3PSC value */
2916     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
2917   }
2918   else
2919   {
2920     /* TI4 Configuration */
2921     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2922
2923     TIM_TI4_SetConfig(htim->Instance,
2924                sConfig->ICPolarity,
2925                sConfig->ICSelection,
2926                sConfig->ICFilter);
2927
2928     /* Reset the IC4PSC Bits */
2929     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
2930
2931     /* Set the IC4PSC value */
2932     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
2933   }
2934
2935   htim->State = HAL_TIM_STATE_READY;
2936
2937   __HAL_UNLOCK(htim);
2938
2939   return HAL_OK;
2940 }
2941
2942 /**
2943   * @brief  Initializes the TIM PWM  channels according to the specified
2944   *         parameters in the TIM_OC_InitTypeDef.
2945   * @param  htim: TIM handle
2946   * @param  sConfig: TIM PWM configuration structure
2947   * @param  Channel : TIM Channels to be enabled
2948   *          This parameter can be one of the following values:
2949   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2950   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2951   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2952   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2953   * @retval HAL status
2954   */
2955 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2956 {
2957   /* Check the parameters */
2958   assert_param(IS_TIM_CHANNELS(Channel));
2959   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
2960   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2961
2962   __HAL_LOCK(htim);
2963
2964   htim->State = HAL_TIM_STATE_BUSY;
2965
2966   switch (Channel)
2967   {
2968     case TIM_CHANNEL_1:
2969     {
2970       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2971       /* Configure the Channel 1 in PWM mode */
2972       TIM_OC1_SetConfig(htim->Instance, sConfig);
2973
2974       /* Set the Preload enable bit for channel1 */
2975       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
2976
2977       /* Configure the Output Fast mode */
2978       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
2979       htim->Instance->CCMR1 |= sConfig->OCFastMode;
2980     }
2981     break;
2982
2983     case TIM_CHANNEL_2:
2984     {
2985       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2986       /* Configure the Channel 2 in PWM mode */
2987       TIM_OC2_SetConfig(htim->Instance, sConfig);
2988
2989       /* Set the Preload enable bit for channel2 */
2990       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
2991
2992       /* Configure the Output Fast mode */
2993       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
2994       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
2995     }
2996     break;
2997
2998     case TIM_CHANNEL_3:
2999     {
3000       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3001       /* Configure the Channel 3 in PWM mode */
3002       TIM_OC3_SetConfig(htim->Instance, sConfig);
3003
3004       /* Set the Preload enable bit for channel3 */
3005       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3006
3007      /* Configure the Output Fast mode */
3008       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3009       htim->Instance->CCMR2 |= sConfig->OCFastMode;
3010     }
3011     break;
3012
3013     case TIM_CHANNEL_4:
3014     {
3015       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3016       /* Configure the Channel 4 in PWM mode */
3017       TIM_OC4_SetConfig(htim->Instance, sConfig);
3018
3019       /* Set the Preload enable bit for channel4 */
3020       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3021
3022      /* Configure the Output Fast mode */
3023       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3024       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
3025     }
3026     break;
3027
3028     default:
3029     break;
3030   }
3031
3032   htim->State = HAL_TIM_STATE_READY;
3033
3034   __HAL_UNLOCK(htim);
3035
3036   return HAL_OK;
3037 }
3038
3039 /**
3040   * @brief  Initializes the TIM One Pulse Channels according to the specified
3041   *         parameters in the TIM_OnePulse_InitTypeDef.
3042   * @param  htim: TIM One Pulse handle
3043   * @param  sConfig: TIM One Pulse configuration structure
3044   * @param  OutputChannel : TIM Channels to be enabled
3045   *          This parameter can be one of the following values:
3046   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3047   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3048   * @param  InputChannel : TIM Channels to be enabled
3049   *          This parameter can be one of the following values:
3050   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3051   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3052   * @retval HAL status
3053   */
3054 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
3055 {
3056   TIM_OC_InitTypeDef temp1;
3057
3058   /* Check the parameters */
3059   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3060   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3061
3062   if(OutputChannel != InputChannel)
3063   {
3064   __HAL_LOCK(htim);
3065
3066   htim->State = HAL_TIM_STATE_BUSY;
3067
3068   /* Extract the Ouput compare configuration from sConfig structure */
3069   temp1.OCMode = sConfig->OCMode;
3070   temp1.Pulse = sConfig->Pulse;
3071   temp1.OCPolarity = sConfig->OCPolarity;
3072   temp1.OCIdleState = sConfig->OCIdleState;
3073
3074     switch (OutputChannel)
3075   {
3076     case TIM_CHANNEL_1:
3077     {
3078         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3079
3080       TIM_OC1_SetConfig(htim->Instance, &temp1);
3081     }
3082     break;
3083     case TIM_CHANNEL_2:
3084     {
3085         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3086
3087       TIM_OC2_SetConfig(htim->Instance, &temp1);
3088     }
3089     break;
3090     default:
3091     break;
3092   }
3093   switch (InputChannel)
3094   {
3095     case TIM_CHANNEL_1:
3096     {
3097       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3098
3099       TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3100                         sConfig->ICSelection, sConfig->ICFilter);
3101
3102       /* Reset the IC1PSC Bits */
3103       htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3104
3105       /* Select the Trigger source */
3106       htim->Instance->SMCR &= ~TIM_SMCR_TS;
3107       htim->Instance->SMCR |= TIM_TS_TI1FP1;
3108
3109       /* Select the Slave Mode */
3110       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3111       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3112     }
3113     break;
3114     case TIM_CHANNEL_2:
3115     {
3116       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3117
3118       TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3119                  sConfig->ICSelection, sConfig->ICFilter);
3120
3121       /* Reset the IC2PSC Bits */
3122       htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3123
3124       /* Select the Trigger source */
3125       htim->Instance->SMCR &= ~TIM_SMCR_TS;
3126       htim->Instance->SMCR |= TIM_TS_TI2FP2;
3127
3128       /* Select the Slave Mode */
3129       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3130       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3131     }
3132     break;
3133
3134     default:
3135     break;
3136   }
3137
3138   htim->State = HAL_TIM_STATE_READY;
3139
3140   __HAL_UNLOCK(htim);
3141
3142   return HAL_OK;
3143 }
3144   else
3145   {
3146     return HAL_ERROR;
3147   }
3148 }
3149
3150 /**
3151   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3152   * @param  htim: TIM handle
3153   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
3154   *         This parameters can be on of the following values:
3155   *            @arg TIM_DMABase_CR1
3156   *            @arg TIM_DMABase_CR2
3157   *            @arg TIM_DMABase_SMCR
3158   *            @arg TIM_DMABase_DIER
3159   *            @arg TIM_DMABase_SR
3160   *            @arg TIM_DMABase_EGR
3161   *            @arg TIM_DMABase_CCMR1
3162   *            @arg TIM_DMABase_CCMR2
3163   *            @arg TIM_DMABase_CCER
3164   *            @arg TIM_DMABase_CNT
3165   *            @arg TIM_DMABase_PSC
3166   *            @arg TIM_DMABase_ARR
3167   *            @arg TIM_DMABase_CCR1
3168   *            @arg TIM_DMABase_CCR2
3169   *            @arg TIM_DMABase_CCR3
3170   *            @arg TIM_DMABase_CCR4
3171   *            @arg TIM_DMABase_DCR
3172   * @param  BurstRequestSrc: TIM DMA Request sources
3173   *         This parameters can be on of the following values:
3174   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
3175   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3176   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3177   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3178   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3179   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3180   * @param  BurstBuffer: The Buffer address.
3181   * @param  BurstLength: DMA Burst length. This parameter can be one value
3182   *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3183   * @retval HAL status
3184   */
3185 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3186                                               uint32_t* BurstBuffer, uint32_t  BurstLength)
3187 {
3188   /* Check the parameters */
3189   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3190   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3191   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3192   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3193
3194   if((htim->State == HAL_TIM_STATE_BUSY))
3195   {
3196      return HAL_BUSY;
3197   }
3198   else if((htim->State == HAL_TIM_STATE_READY))
3199   {
3200     if((BurstBuffer == 0 ) && (BurstLength > 0))
3201     {
3202       return HAL_ERROR;
3203     }
3204     else
3205     {
3206       htim->State = HAL_TIM_STATE_BUSY;
3207     }
3208   }
3209   else
3210   {
3211     return HAL_ERROR;
3212   }
3213
3214   switch(BurstRequestSrc)
3215   {
3216     case TIM_DMA_UPDATE:
3217     {
3218       /* Set the DMA Period elapsed callback */
3219       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3220
3221       /* Set the DMA error callback */
3222       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3223
3224       /* Enable the DMA channel */
3225       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3226     }
3227     break;
3228     case TIM_DMA_CC1:
3229     {
3230       /* Set the DMA Period elapsed callback */
3231       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
3232
3233       /* Set the DMA error callback */
3234       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3235
3236       /* Enable the DMA channel */
3237       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3238     }
3239     break;
3240     case TIM_DMA_CC2:
3241     {
3242       /* Set the DMA Period elapsed callback */
3243       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
3244
3245       /* Set the DMA error callback */
3246       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3247
3248       /* Enable the DMA channel */
3249       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3250     }
3251     break;
3252     case TIM_DMA_CC3:
3253     {
3254       /* Set the DMA Period elapsed callback */
3255       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
3256
3257       /* Set the DMA error callback */
3258       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3259
3260       /* Enable the DMA channel */
3261       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3262     }
3263     break;
3264     case TIM_DMA_CC4:
3265     {
3266       /* Set the DMA Period elapsed callback */
3267       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
3268
3269       /* Set the DMA error callback */
3270       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3271
3272       /* Enable the DMA channel */
3273       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3274     }
3275     break;
3276     case TIM_DMA_TRIGGER:
3277     {
3278       /* Set the DMA Period elapsed callback */
3279       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3280
3281       /* Set the DMA error callback */
3282       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3283
3284       /* Enable the DMA channel */
3285       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3286     }
3287     break;
3288     default:
3289     break;
3290   }
3291    /* configure the DMA Burst Mode */
3292    htim->Instance->DCR = BurstBaseAddress | BurstLength;
3293
3294    /* Enable the TIM DMA Request */
3295    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3296
3297    htim->State = HAL_TIM_STATE_READY;
3298
3299   /* Return function status */
3300   return HAL_OK;
3301 }
3302
3303 /**
3304   * @brief  Stops the TIM DMA Burst mode
3305   * @param  htim: TIM handle
3306   * @param  BurstRequestSrc: TIM DMA Request sources to disable
3307   * @retval HAL status
3308   */
3309 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3310 {
3311   /* Check the parameters */
3312   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3313
3314   /* Abort the DMA transfer (at least disable the DMA channel) */
3315   switch(BurstRequestSrc)
3316   {
3317     case TIM_DMA_UPDATE:
3318     {
3319       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3320     }
3321     break;
3322     case TIM_DMA_CC1:
3323     {
3324       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3325     }
3326     break;
3327     case TIM_DMA_CC2:
3328     {
3329       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3330     }
3331     break;
3332     case TIM_DMA_CC3:
3333     {
3334       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3335     }
3336     break;
3337     case TIM_DMA_CC4:
3338     {
3339       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3340     }
3341     break;
3342     case TIM_DMA_TRIGGER:
3343     {
3344       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3345     }
3346     break;
3347     default:
3348     break;
3349   }
3350
3351   /* Disable the TIM Update DMA request */
3352   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3353
3354   /* Return function status */
3355   return HAL_OK;
3356 }
3357
3358 /**
3359   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3360   * @param  htim: TIM handle
3361   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
3362   *         This parameters can be on of the following values:
3363   *            @arg TIM_DMABase_CR1
3364   *            @arg TIM_DMABase_CR2
3365   *            @arg TIM_DMABase_SMCR
3366   *            @arg TIM_DMABase_DIER
3367   *            @arg TIM_DMABase_SR
3368   *            @arg TIM_DMABase_EGR
3369   *            @arg TIM_DMABase_CCMR1
3370   *            @arg TIM_DMABase_CCMR2
3371   *            @arg TIM_DMABase_CCER
3372   *            @arg TIM_DMABase_CNT
3373   *            @arg TIM_DMABase_PSC
3374   *            @arg TIM_DMABase_ARR
3375   *            @arg TIM_DMABase_RCR
3376   *            @arg TIM_DMABase_CCR1
3377   *            @arg TIM_DMABase_CCR2
3378   *            @arg TIM_DMABase_CCR3
3379   *            @arg TIM_DMABase_CCR4
3380   *            @arg TIM_DMABase_BDTR
3381   *            @arg TIM_DMABase_DCR
3382   * @param  BurstRequestSrc: TIM DMA Request sources
3383   *         This parameters can be on of the following values:
3384   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
3385   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3386   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3387   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3388   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3389   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3390   * @param  BurstBuffer: The Buffer address.
3391   * @param  BurstLength: DMA Burst length. This parameter can be one value
3392   *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3393   * @retval HAL status
3394   */
3395 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3396                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
3397 {
3398   /* Check the parameters */
3399   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3400   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3401   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3402   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3403
3404   if((htim->State == HAL_TIM_STATE_BUSY))
3405   {
3406      return HAL_BUSY;
3407   }
3408   else if((htim->State == HAL_TIM_STATE_READY))
3409   {
3410     if((BurstBuffer == 0 ) && (BurstLength > 0))
3411     {
3412       return HAL_ERROR;
3413     }
3414     else
3415     {
3416       htim->State = HAL_TIM_STATE_BUSY;
3417     }
3418   }
3419   else
3420   {
3421     return HAL_ERROR;
3422   }
3423
3424   switch(BurstRequestSrc)
3425   {
3426     case TIM_DMA_UPDATE:
3427     {
3428       /* Set the DMA Period elapsed callback */
3429       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3430
3431       /* Set the DMA error callback */
3432       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3433
3434       /* Enable the DMA channel */
3435        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3436     }
3437     break;
3438     case TIM_DMA_CC1:
3439     {
3440       /* Set the DMA Period elapsed callback */
3441       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
3442
3443       /* Set the DMA error callback */
3444       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3445
3446       /* Enable the DMA channel */
3447       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3448     }
3449     break;
3450     case TIM_DMA_CC2:
3451     {
3452       /* Set the DMA Period elapsed callback */
3453       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
3454
3455       /* Set the DMA error callback */
3456       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3457
3458       /* Enable the DMA channel */
3459       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3460     }
3461     break;
3462     case TIM_DMA_CC3:
3463     {
3464       /* Set the DMA Period elapsed callback */
3465       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
3466
3467       /* Set the DMA error callback */
3468       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3469
3470       /* Enable the DMA channel */
3471       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3472     }
3473     break;
3474     case TIM_DMA_CC4:
3475     {
3476       /* Set the DMA Period elapsed callback */
3477       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
3478
3479       /* Set the DMA error callback */
3480       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3481
3482       /* Enable the DMA channel */
3483       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3484     }
3485     break;
3486     case TIM_DMA_TRIGGER:
3487     {
3488       /* Set the DMA Period elapsed callback */
3489       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3490
3491       /* Set the DMA error callback */
3492       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3493
3494       /* Enable the DMA channel */
3495       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3496     }
3497     break;
3498     default:
3499     break;
3500   }
3501
3502   /* configure the DMA Burst Mode */
3503   htim->Instance->DCR = BurstBaseAddress | BurstLength;
3504
3505   /* Enable the TIM DMA Request */
3506   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3507
3508   htim->State = HAL_TIM_STATE_READY;
3509
3510   /* Return function status */
3511   return HAL_OK;
3512 }
3513
3514 /**
3515   * @brief  Stop the DMA burst reading
3516   * @param  htim: TIM handle
3517   * @param  BurstRequestSrc: TIM DMA Request sources to disable.
3518   * @retval HAL status
3519   */
3520 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3521 {
3522   /* Check the parameters */
3523   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3524
3525   /* Abort the DMA transfer (at least disable the DMA channel) */
3526   switch(BurstRequestSrc)
3527   {
3528     case TIM_DMA_UPDATE:
3529     {
3530       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3531     }
3532     break;
3533     case TIM_DMA_CC1:
3534     {
3535       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3536     }
3537     break;
3538     case TIM_DMA_CC2:
3539     {
3540       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3541     }
3542     break;
3543     case TIM_DMA_CC3:
3544     {
3545       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3546     }
3547     break;
3548     case TIM_DMA_CC4:
3549     {
3550       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3551     }
3552     break;
3553     case TIM_DMA_TRIGGER:
3554     {
3555       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3556     }
3557     break;
3558     default:
3559     break;
3560   }
3561
3562   /* Disable the TIM Update DMA request */
3563   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3564
3565   /* Return function status */
3566   return HAL_OK;
3567 }
3568
3569 /**
3570   * @brief  Generate a software event
3571   * @param  htim: TIM handle
3572   * @param  EventSource: specifies the event source.
3573   *          This parameter can be one of the following values:
3574   *            @arg TIM_EventSource_Update: Timer update Event source
3575   *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
3576   *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
3577   *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
3578   *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
3579   *            @arg TIM_EventSource_COM: Timer COM event source
3580   *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
3581   *            @arg TIM_EventSource_Break: Timer Break event source
3582   * @note   TBC can only generate an update event.
3583   * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC.
3584   * @retval HAL status
3585   */
3586
3587 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3588 {
3589   /* Check the parameters */
3590   assert_param(IS_TIM_INSTANCE(htim->Instance));
3591   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3592
3593   /* Process Locked */
3594   __HAL_LOCK(htim);
3595
3596   /* Change the TIM state */
3597   htim->State = HAL_TIM_STATE_BUSY;
3598
3599   /* Set the event sources */
3600   htim->Instance->EGR = EventSource;
3601
3602   /* Change the TIM state */
3603   htim->State = HAL_TIM_STATE_READY;
3604
3605   __HAL_UNLOCK(htim);
3606
3607   /* Return function status */
3608   return HAL_OK;
3609 }
3610
3611 /**
3612   * @brief  Configures the OCRef clear feature
3613   * @param  htim: TIM handle
3614   * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
3615   *         contains the OCREF clear feature and parameters for the TIM peripheral.
3616   * @param  Channel: specifies the TIM Channel
3617   *          This parameter can be one of the following values:
3618   *            @arg TIM_CHANNEL_1: TIM Channel 1
3619   *            @arg TIM_CHANNEL_2: TIM Channel 2
3620   *            @arg TIM_CHANNEL_3: TIM Channel 3
3621   *            @arg TIM_CHANNEL_4: TIM Channel 4
3622   * @retval HAL status
3623   */
3624 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3625 {
3626
3627   /* Check the parameters */
3628   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
3629   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3630   assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3631   assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3632   assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3633
3634   /* Process Locked */
3635   __HAL_LOCK(htim);
3636
3637   htim->State = HAL_TIM_STATE_BUSY;
3638
3639   switch (sClearInputConfig->ClearInputSource)
3640   {
3641     case TIM_CLEARINPUTSOURCE_NONE:
3642     {
3643       /* Clear the OCREF clear selection bit */
3644       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
3645
3646       /* Clear the ETR Bits */
3647       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
3648
3649     }
3650     break;
3651
3652     case TIM_CLEARINPUTSOURCE_OCREFCLR:
3653     {
3654       /* Clear the OCREF clear selection bit */
3655       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
3656     }
3657     break;
3658
3659     case TIM_CLEARINPUTSOURCE_ETR:
3660     {
3661       TIM_ETR_SetConfig(htim->Instance,
3662                         sClearInputConfig->ClearInputPrescaler,
3663                         sClearInputConfig->ClearInputPolarity,
3664                         sClearInputConfig->ClearInputFilter);
3665
3666       /* Set the OCREF clear selection bit */
3667       SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
3668     }
3669     break;
3670
3671   default:
3672     break;
3673
3674   }
3675
3676   switch (Channel)
3677   {
3678     case TIM_CHANNEL_1:
3679       {
3680         if(sClearInputConfig->ClearInputState != RESET)
3681         {
3682           /* Enable the Ocref clear feature for Channel 1 */
3683           htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3684         }
3685         else
3686         {
3687           /* Disable the Ocref clear feature for Channel 1 */
3688           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3689         }
3690       }
3691       break;
3692     case TIM_CHANNEL_2:
3693       {
3694         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3695         if(sClearInputConfig->ClearInputState != RESET)
3696         {
3697           /* Enable the Ocref clear feature for Channel 2 */
3698           htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3699         }
3700         else
3701         {
3702           /* Disable the Ocref clear feature for Channel 2 */
3703           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3704         }
3705       }
3706     break;
3707     case TIM_CHANNEL_3:
3708       {
3709         assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3710         if(sClearInputConfig->ClearInputState != RESET)
3711         {
3712           /* Enable the Ocref clear feature for Channel 3 */
3713           htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3714         }
3715         else
3716         {
3717           /* Disable the Ocref clear feature for Channel 3 */
3718           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3719         }
3720       }
3721     break;
3722     case TIM_CHANNEL_4:
3723       {
3724         assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3725         if(sClearInputConfig->ClearInputState != RESET)
3726         {
3727           /* Enable the Ocref clear feature for Channel 4 */
3728           htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3729         }
3730         else
3731         {
3732           /* Disable the Ocref clear feature for Channel 4 */
3733           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3734         }
3735       }
3736     break;
3737     default:
3738     break;
3739   }
3740
3741   htim->State = HAL_TIM_STATE_READY;
3742
3743   __HAL_UNLOCK(htim);
3744
3745   return HAL_OK;
3746 }
3747
3748 /**
3749   * @brief   Configures the clock source to be used
3750   * @param  htim: TIM handle
3751   * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
3752   *         contains the clock source information for the TIM peripheral.
3753   * @retval HAL status
3754   */
3755 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3756 {
3757   uint32_t tmpsmcr = 0;
3758
3759   /* Check the parameters */
3760   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3761   assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3762   assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3763   assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3764
3765   /* Process Locked */
3766   __HAL_LOCK(htim);
3767
3768   htim->State = HAL_TIM_STATE_BUSY;
3769
3770   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3771   tmpsmcr = htim->Instance->SMCR;
3772   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3773   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3774   htim->Instance->SMCR = tmpsmcr;
3775
3776   switch (sClockSourceConfig->ClockSource)
3777   {
3778   case TIM_CLOCKSOURCE_INTERNAL:
3779     {
3780       assert_param(IS_TIM_INSTANCE(htim->Instance));
3781       /* Disable slave mode to clock the prescaler directly with the internal clock */
3782       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3783     }
3784     break;
3785
3786   case TIM_CLOCKSOURCE_ETRMODE1:
3787     {
3788       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
3789       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
3790
3791       /* Configure the ETR Clock source */
3792       TIM_ETR_SetConfig(htim->Instance,
3793                         sClockSourceConfig->ClockPrescaler,
3794                         sClockSourceConfig->ClockPolarity,
3795                         sClockSourceConfig->ClockFilter);
3796       /* Get the TIMx SMCR register value */
3797       tmpsmcr = htim->Instance->SMCR;
3798       /* Reset the SMS and TS Bits */
3799       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3800       /* Select the External clock mode1 and the ETRF trigger */
3801       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3802       /* Write to TIMx SMCR */
3803       htim->Instance->SMCR = tmpsmcr;
3804     }
3805     break;
3806
3807   case TIM_CLOCKSOURCE_ETRMODE2:
3808     {
3809       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
3810       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
3811
3812       /* Configure the ETR Clock source */
3813       TIM_ETR_SetConfig(htim->Instance,
3814                         sClockSourceConfig->ClockPrescaler,
3815                         sClockSourceConfig->ClockPolarity,
3816                         sClockSourceConfig->ClockFilter);
3817       /* Enable the External clock mode2 */
3818       htim->Instance->SMCR |= TIM_SMCR_ECE;
3819     }
3820     break;
3821
3822   case TIM_CLOCKSOURCE_TI1:
3823     {
3824       /* Check whether or not the timer instance supports external clock mode 1 */
3825       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3826
3827       TIM_TI1_ConfigInputStage(htim->Instance,
3828                                sClockSourceConfig->ClockPolarity,
3829                                sClockSourceConfig->ClockFilter);
3830       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
3831     }
3832     break;
3833   case TIM_CLOCKSOURCE_TI2:
3834     {
3835       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
3836       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3837
3838       TIM_TI2_ConfigInputStage(htim->Instance,
3839                                sClockSourceConfig->ClockPolarity,
3840                                sClockSourceConfig->ClockFilter);
3841       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
3842     }
3843     break;
3844   case TIM_CLOCKSOURCE_TI1ED:
3845     {
3846       /* Check whether or not the timer instance supports external clock mode 1 */
3847       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3848
3849       TIM_TI1_ConfigInputStage(htim->Instance,
3850                                sClockSourceConfig->ClockPolarity,
3851                                sClockSourceConfig->ClockFilter);
3852       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
3853     }
3854     break;
3855   case TIM_CLOCKSOURCE_ITR0:
3856     {
3857       /* Check whether or not the timer instance supports external clock mode 1 */
3858       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3859
3860       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
3861     }
3862     break;
3863   case TIM_CLOCKSOURCE_ITR1:
3864     {
3865       /* Check whether or not the timer instance supports external clock mode 1 */
3866       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3867
3868       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
3869     }
3870     break;
3871   case TIM_CLOCKSOURCE_ITR2:
3872     {
3873       /* Check whether or not the timer instance supports external clock mode 1 */
3874       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3875
3876       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
3877     }
3878     break;
3879   case TIM_CLOCKSOURCE_ITR3:
3880     {
3881       /* Check whether or not the timer instance supports external clock mode 1 */
3882       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3883
3884       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
3885     }
3886     break;
3887
3888   default:
3889     break;
3890   }
3891   htim->State = HAL_TIM_STATE_READY;
3892
3893   __HAL_UNLOCK(htim);
3894
3895   return HAL_OK;
3896 }
3897
3898 /**
3899   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
3900   *         or a XOR combination between CH1_input, CH2_input & CH3_input
3901   * @param  htim: TIM handle.
3902   * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
3903   *         output of a XOR gate.
3904   *          This parameter can be one of the following values:
3905   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
3906   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
3907   *            pins are connected to the TI1 input (XOR combination)
3908   * @retval HAL status
3909   */
3910 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
3911 {
3912   uint32_t tmpcr2 = 0;
3913
3914   /* Check the parameters */
3915   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
3916   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
3917
3918   /* Get the TIMx CR2 register value */
3919   tmpcr2 = htim->Instance->CR2;
3920
3921   /* Reset the TI1 selection */
3922   tmpcr2 &= ~TIM_CR2_TI1S;
3923
3924   /* Set the the TI1 selection */
3925   tmpcr2 |= TI1_Selection;
3926
3927   /* Write to TIMxCR2 */
3928   htim->Instance->CR2 = tmpcr2;
3929
3930   return HAL_OK;
3931 }
3932
3933 /**
3934   * @brief  Configures the TIM in Slave mode
3935   * @param  htim: TIM handle.
3936   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
3937   *         contains the selected trigger (internal trigger input, filtered
3938   *         timer input or external trigger input) and the ) and the Slave
3939   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
3940   * @retval HAL status
3941   */
3942 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
3943 {
3944   uint32_t tmpsmcr = 0;
3945   uint32_t tmpccmr1 = 0;
3946   uint32_t tmpccer = 0;
3947
3948   /* Check the parameters */
3949   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3950   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
3951   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
3952
3953   __HAL_LOCK(htim);
3954
3955   htim->State = HAL_TIM_STATE_BUSY;
3956
3957   /* Get the TIMx SMCR register value */
3958   tmpsmcr = htim->Instance->SMCR;
3959
3960   /* Reset the Trigger Selection Bits */
3961   tmpsmcr &= ~TIM_SMCR_TS;
3962   /* Set the Input Trigger source */
3963   tmpsmcr |= sSlaveConfig->InputTrigger;
3964
3965   /* Reset the slave mode Bits */
3966   tmpsmcr &= ~TIM_SMCR_SMS;
3967   /* Set the slave mode */
3968   tmpsmcr |= sSlaveConfig->SlaveMode;
3969
3970   /* Write to TIMx SMCR */
3971   htim->Instance->SMCR = tmpsmcr;
3972
3973   /* Configure the trigger prescaler, filter, and polarity */
3974   switch (sSlaveConfig->InputTrigger)
3975   {
3976   case TIM_TS_ETRF:
3977     {
3978       /* Check the parameters */
3979       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
3980       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
3981       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
3982       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
3983       /* Configure the ETR Trigger source */
3984       TIM_ETR_SetConfig(htim->Instance,
3985                         sSlaveConfig->TriggerPrescaler,
3986                         sSlaveConfig->TriggerPolarity,
3987                         sSlaveConfig->TriggerFilter);
3988     }
3989     break;
3990
3991   case TIM_TS_TI1F_ED:
3992     {
3993       /* Check the parameters */
3994       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3995       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
3996       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
3997
3998       /* Disable the Channel 1: Reset the CC1E Bit */
3999       tmpccer = htim->Instance->CCER;
4000       htim->Instance->CCER &= ~TIM_CCER_CC1E;
4001       tmpccmr1 = htim->Instance->CCMR1;
4002
4003       /* Set the filter */
4004       tmpccmr1 &= ~TIM_CCMR1_IC1F;
4005       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
4006
4007       /* Write to TIMx CCMR1 and CCER registers */
4008       htim->Instance->CCMR1 = tmpccmr1;
4009       htim->Instance->CCER = tmpccer;
4010
4011     }
4012     break;
4013
4014   case TIM_TS_TI1FP1:
4015     {
4016       /* Check the parameters */
4017       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4018       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4019       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4020
4021       /* Configure TI1 Filter and Polarity */
4022       TIM_TI1_ConfigInputStage(htim->Instance,
4023                                sSlaveConfig->TriggerPolarity,
4024                                sSlaveConfig->TriggerFilter);
4025     }
4026     break;
4027
4028   case TIM_TS_TI2FP2:
4029     {
4030       /* Check the parameters */
4031       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4032       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4033       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4034
4035       /* Configure TI2 Filter and Polarity */
4036       TIM_TI2_ConfigInputStage(htim->Instance,
4037                                 sSlaveConfig->TriggerPolarity,
4038                                 sSlaveConfig->TriggerFilter);
4039     }
4040     break;
4041
4042   case TIM_TS_ITR0:
4043     {
4044       /* Check the parameter */
4045       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4046     }
4047     break;
4048
4049   case TIM_TS_ITR1:
4050     {
4051       /* Check the parameter */
4052       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4053     }
4054     break;
4055
4056   case TIM_TS_ITR2:
4057     {
4058       /* Check the parameter */
4059       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4060     }
4061     break;
4062
4063   case TIM_TS_ITR3:
4064     {
4065       /* Check the parameter */
4066       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4067     }
4068     break;
4069
4070   default:
4071     break;
4072   }
4073
4074   htim->State = HAL_TIM_STATE_READY;
4075
4076   __HAL_UNLOCK(htim);
4077
4078   return HAL_OK;
4079 }
4080
4081 /**
4082   * @brief  Read the captured value from Capture Compare unit
4083   * @param  htim: TIM handle.
4084   * @param  Channel : TIM Channels to be enabled
4085   *          This parameter can be one of the following values:
4086   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4087   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4088   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
4089   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
4090   * @retval Captured value
4091   */
4092 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4093 {
4094   uint32_t tmpreg = 0;
4095
4096   __HAL_LOCK(htim);
4097
4098   switch (Channel)
4099   {
4100   case TIM_CHANNEL_1:
4101     {
4102       /* Check the parameters */
4103       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4104
4105       /* Return the capture 1 value */
4106       tmpreg =  htim->Instance->CCR1;
4107
4108       break;
4109     }
4110   case TIM_CHANNEL_2:
4111     {
4112       /* Check the parameters */
4113       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4114
4115       /* Return the capture 2 value */
4116       tmpreg =   htim->Instance->CCR2;
4117
4118       break;
4119     }
4120
4121   case TIM_CHANNEL_3:
4122     {
4123       /* Check the parameters */
4124       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4125
4126       /* Return the capture 3 value */
4127       tmpreg =   htim->Instance->CCR3;
4128
4129       break;
4130     }
4131
4132   case TIM_CHANNEL_4:
4133     {
4134       /* Check the parameters */
4135       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4136
4137       /* Return the capture 4 value */
4138       tmpreg =   htim->Instance->CCR4;
4139
4140       break;
4141     }
4142
4143   default:
4144     break;
4145   }
4146
4147   __HAL_UNLOCK(htim);
4148   return tmpreg;
4149 }
4150
4151 /**
4152   * @}
4153   */
4154
4155 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4156  *  @brief    TIM Callbacks functions
4157  *
4158 @verbatim
4159   ==============================================================================
4160                         ##### TIM Callbacks functions #####
4161   ==============================================================================
4162  [..]
4163    This section provides TIM callback functions:
4164    (+) Timer Period elapsed callback
4165    (+) Timer Output Compare callback
4166    (+) Timer Input capture callback
4167    (+) Timer Trigger callback
4168    (+) Timer Error callback
4169
4170 @endverbatim
4171   * @{
4172   */
4173
4174 /**
4175   * @brief  Period elapsed callback in non blocking mode
4176   * @param  htim : TIM handle
4177   * @retval None
4178   */
4179 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4180 {
4181   /* NOTE : This function Should not be modified, when the callback is needed,
4182             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4183    */
4184
4185 }
4186 /**
4187   * @brief  Output Compare callback in non blocking mode
4188   * @param  htim : TIM OC handle
4189   * @retval None
4190   */
4191 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4192 {
4193   /* NOTE : This function Should not be modified, when the callback is needed,
4194             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4195    */
4196 }
4197 /**
4198   * @brief  Input Capture callback in non blocking mode
4199   * @param  htim : TIM IC handle
4200   * @retval None
4201   */
4202 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4203 {
4204   /* NOTE : This function Should not be modified, when the callback is needed,
4205             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4206    */
4207 }
4208
4209 /**
4210   * @brief  PWM Pulse finished callback in non blocking mode
4211   * @param  htim : TIM handle
4212   * @retval None
4213   */
4214 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4215 {
4216   /* NOTE : This function Should not be modified, when the callback is needed,
4217             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4218    */
4219 }
4220
4221 /**
4222   * @brief  Hall Trigger detection callback in non blocking mode
4223   * @param  htim : TIM handle
4224   * @retval None
4225   */
4226 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4227 {
4228   /* NOTE : This function Should not be modified, when the callback is needed,
4229             the HAL_TIM_TriggerCallback could be implemented in the user file
4230    */
4231 }
4232
4233 /**
4234   * @brief  Timer error callback in non blocking mode
4235   * @param  htim : TIM handle
4236   * @retval None
4237   */
4238 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4239 {
4240   /* NOTE : This function Should not be modified, when the callback is needed,
4241             the HAL_TIM_ErrorCallback could be implemented in the user file
4242    */
4243 }
4244
4245 /**
4246   * @}
4247   */
4248
4249 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4250  *  @brief   Peripheral State functions
4251  *
4252 @verbatim
4253   ==============================================================================
4254                         ##### Peripheral State functions #####
4255   ==============================================================================
4256     [..]
4257     This subsection permit to get in run-time the status of the peripheral
4258     and the data flow.
4259
4260 @endverbatim
4261   * @{
4262   */
4263
4264 /**
4265   * @brief  Return the TIM Base state
4266   * @param  htim: TIM Base handle
4267   * @retval HAL state
4268   */
4269 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4270 {
4271   return htim->State;
4272 }
4273
4274 /**
4275   * @brief  Return the TIM OC state
4276   * @param  htim: TIM Ouput Compare handle
4277   * @retval HAL state
4278   */
4279 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4280 {
4281   return htim->State;
4282 }
4283
4284 /**
4285   * @brief  Return the TIM PWM state
4286   * @param  htim: TIM handle
4287   * @retval HAL state
4288   */
4289 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4290 {
4291   return htim->State;
4292 }
4293
4294 /**
4295   * @brief  Return the TIM Input Capture state
4296   * @param  htim: TIM IC handle
4297   * @retval HAL state
4298   */
4299 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4300 {
4301   return htim->State;
4302 }
4303
4304 /**
4305   * @brief  Return the TIM One Pulse Mode state
4306   * @param  htim: TIM OPM handle
4307   * @retval HAL state
4308   */
4309 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4310 {
4311   return htim->State;
4312 }
4313
4314 /**
4315   * @brief  Return the TIM Encoder Mode state
4316   * @param  htim: TIM Encoder handle
4317   * @retval HAL state
4318   */
4319 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4320 {
4321   return htim->State;
4322 }
4323
4324 /**
4325   * @}
4326   */
4327
4328 /**
4329   * @}
4330   */
4331
4332
4333 /** @addtogroup TIM_Private_Functions
4334   * @{
4335   */
4336
4337
4338 /**
4339   * @brief  TIM DMA error callback
4340   * @param  hdma : pointer to DMA handle.
4341   * @retval None
4342   */
4343 static void TIM_DMAError(DMA_HandleTypeDef *hdma)
4344 {
4345   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4346
4347   htim->State= HAL_TIM_STATE_READY;
4348
4349   HAL_TIM_ErrorCallback(htim);
4350 }
4351
4352 /**
4353   * @brief  TIM DMA Delay Pulse complete callback.
4354   * @param  hdma : pointer to DMA handle.
4355   * @retval None
4356   */
4357 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4358 {
4359   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4360
4361   htim->State= HAL_TIM_STATE_READY;
4362
4363   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4364   {
4365     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4366   }
4367   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4368   {
4369     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4370   }
4371   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4372   {
4373     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4374   }
4375   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4376   {
4377     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4378   }
4379
4380   HAL_TIM_PWM_PulseFinishedCallback(htim);
4381
4382   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4383 }
4384
4385 /**
4386   * @brief  TIM DMA Capture complete callback.
4387   * @param  hdma : pointer to DMA handle.
4388   * @retval None
4389   */
4390 static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4391 {
4392   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4393
4394   htim->State= HAL_TIM_STATE_READY;
4395
4396   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4397   {
4398     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4399   }
4400   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4401   {
4402     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4403   }
4404   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4405   {
4406     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4407   }
4408   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4409   {
4410     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4411   }
4412
4413   HAL_TIM_IC_CaptureCallback(htim);
4414
4415   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4416 }
4417
4418 /**
4419   * @brief  TIM DMA Period Elapse complete callback.
4420   * @param  hdma : pointer to DMA handle.
4421   * @retval None
4422   */
4423 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4424 {
4425   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4426
4427   htim->State= HAL_TIM_STATE_READY;
4428
4429   HAL_TIM_PeriodElapsedCallback(htim);
4430 }
4431
4432 /**
4433   * @brief  TIM DMA Trigger callback.
4434   * @param  hdma : pointer to DMA handle.
4435   * @retval None
4436   */
4437 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4438 {
4439   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4440
4441   htim->State= HAL_TIM_STATE_READY;
4442
4443   HAL_TIM_TriggerCallback(htim);
4444 }
4445
4446 /**
4447   * @brief  Time Base configuration
4448   * @param  TIMx: TIM periheral
4449   * @param  Structure: TIM Base configuration structure
4450   * @retval None
4451   */
4452 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4453 {
4454   uint32_t tmpcr1 = 0;
4455   tmpcr1 = TIMx->CR1;
4456
4457   /* Set TIM Time Base Unit parameters ---------------------------------------*/
4458   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
4459   {
4460     /* Select the Counter Mode */
4461     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4462     tmpcr1 |= Structure->CounterMode;
4463   }
4464
4465   if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
4466   {
4467     /* Set the clock division */
4468     tmpcr1 &= ~TIM_CR1_CKD;
4469     tmpcr1 |= (uint32_t)Structure->ClockDivision;
4470   }
4471
4472   TIMx->CR1 = tmpcr1;
4473
4474   /* Set the Autoreload value */
4475   TIMx->ARR = (uint32_t)Structure->Period ;
4476
4477   /* Set the Prescaler value */
4478   TIMx->PSC = (uint32_t)Structure->Prescaler;
4479
4480   /* Generate an update event to reload the Prescaler
4481      and the repetition counter(only for TIM1 and TIM8) value immediatly */
4482   TIMx->EGR = TIM_EGR_UG;
4483 }
4484
4485 /**
4486   * @brief  Time Ouput Compare 1 configuration
4487   * @param  TIMx to select the TIM peripheral
4488   * @param  OC_Config: The ouput configuration structure
4489   * @retval None
4490   */
4491 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4492 {
4493   uint32_t tmpccmrx = 0;
4494   uint32_t tmpccer = 0;
4495   uint32_t tmpcr2 = 0;
4496
4497    /* Disable the Channel 1: Reset the CC1E Bit */
4498   TIMx->CCER &= ~TIM_CCER_CC1E;
4499
4500   /* Get the TIMx CCER register value */
4501   tmpccer = TIMx->CCER;
4502   /* Get the TIMx CR2 register value */
4503   tmpcr2 =  TIMx->CR2;
4504
4505   /* Get the TIMx CCMR1 register value */
4506   tmpccmrx = TIMx->CCMR1;
4507
4508   /* Reset the Output Compare Mode Bits */
4509   tmpccmrx &= ~TIM_CCMR1_OC1M;
4510   tmpccmrx &= ~TIM_CCMR1_CC1S;
4511   /* Select the Output Compare Mode */
4512   tmpccmrx |= OC_Config->OCMode;
4513
4514   /* Reset the Output Polarity level */
4515   tmpccer &= ~TIM_CCER_CC1P;
4516   /* Set the Output Compare Polarity */
4517   tmpccer |= OC_Config->OCPolarity;
4518
4519   /* Write to TIMx CR2 */
4520   TIMx->CR2 = tmpcr2;
4521
4522   /* Write to TIMx CCMR1 */
4523   TIMx->CCMR1 = tmpccmrx;
4524
4525   /* Set the Capture Compare Register value */
4526   TIMx->CCR1 = OC_Config->Pulse;
4527
4528   /* Write to TIMx CCER */
4529   TIMx->CCER = tmpccer;
4530 }
4531
4532 /**
4533   * @brief  Time Ouput Compare 2 configuration
4534   * @param  TIMx to select the TIM peripheral
4535   * @param  OC_Config: The ouput configuration structure
4536   * @retval None
4537   */
4538 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4539 {
4540   uint32_t tmpccmrx = 0;
4541   uint32_t tmpccer = 0;
4542   uint32_t tmpcr2 = 0;
4543
4544   /* Disable the Channel 2: Reset the CC2E Bit */
4545   TIMx->CCER &= ~TIM_CCER_CC2E;
4546
4547   /* Get the TIMx CCER register value */
4548   tmpccer = TIMx->CCER;
4549   /* Get the TIMx CR2 register value */
4550   tmpcr2 =  TIMx->CR2;
4551
4552   /* Get the TIMx CCMR1 register value */
4553   tmpccmrx = TIMx->CCMR1;
4554
4555   /* Reset the Output Compare mode and Capture/Compare selection Bits */
4556   tmpccmrx &= ~TIM_CCMR1_OC2M;
4557   tmpccmrx &= ~TIM_CCMR1_CC2S;
4558
4559   /* Select the Output Compare Mode */
4560   tmpccmrx |= (OC_Config->OCMode << 8);
4561
4562   /* Reset the Output Polarity level */
4563   tmpccer &= ~TIM_CCER_CC2P;
4564   /* Set the Output Compare Polarity */
4565   tmpccer |= (OC_Config->OCPolarity << 4);
4566
4567   /* Write to TIMx CR2 */
4568   TIMx->CR2 = tmpcr2;
4569
4570   /* Write to TIMx CCMR1 */
4571   TIMx->CCMR1 = tmpccmrx;
4572
4573   /* Set the Capture Compare Register value */
4574   TIMx->CCR2 = OC_Config->Pulse;
4575
4576   /* Write to TIMx CCER */
4577   TIMx->CCER = tmpccer;
4578 }
4579
4580 /**
4581   * @brief  Time Ouput Compare 3 configuration
4582   * @param  TIMx to select the TIM peripheral
4583   * @param  OC_Config: The ouput configuration structure
4584   * @retval None
4585   */
4586 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4587 {
4588   uint32_t tmpccmrx = 0;
4589   uint32_t tmpccer = 0;
4590   uint32_t tmpcr2 = 0;
4591
4592   /* Disable the Channel 3: Reset the CC2E Bit */
4593   TIMx->CCER &= ~TIM_CCER_CC3E;
4594
4595   /* Get the TIMx CCER register value */
4596   tmpccer = TIMx->CCER;
4597   /* Get the TIMx CR2 register value */
4598   tmpcr2 =  TIMx->CR2;
4599
4600   /* Get the TIMx CCMR2 register value */
4601   tmpccmrx = TIMx->CCMR2;
4602
4603   /* Reset the Output Compare mode and Capture/Compare selection Bits */
4604   tmpccmrx &= ~TIM_CCMR2_OC3M;
4605   tmpccmrx &= ~TIM_CCMR2_CC3S;
4606   /* Select the Output Compare Mode */
4607   tmpccmrx |= OC_Config->OCMode;
4608
4609   /* Reset the Output Polarity level */
4610   tmpccer &= ~TIM_CCER_CC3P;
4611   /* Set the Output Compare Polarity */
4612   tmpccer |= (OC_Config->OCPolarity << 8);
4613
4614   /* Write to TIMx CR2 */
4615   TIMx->CR2 = tmpcr2;
4616
4617   /* Write to TIMx CCMR2 */
4618   TIMx->CCMR2 = tmpccmrx;
4619
4620   /* Set the Capture Compare Register value */
4621   TIMx->CCR3 = OC_Config->Pulse;
4622
4623   /* Write to TIMx CCER */
4624   TIMx->CCER = tmpccer;
4625 }
4626
4627 /**
4628   * @brief  Time Ouput Compare 4 configuration
4629   * @param  TIMx to select the TIM peripheral
4630   * @param  OC_Config: The ouput configuration structure
4631   * @retval None
4632   */
4633 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4634 {
4635   uint32_t tmpccmrx = 0;
4636   uint32_t tmpccer = 0;
4637   uint32_t tmpcr2 = 0;
4638
4639   /* Disable the Channel 4: Reset the CC4E Bit */
4640   TIMx->CCER &= ~TIM_CCER_CC4E;
4641
4642   /* Get the TIMx CCER register value */
4643   tmpccer = TIMx->CCER;
4644   /* Get the TIMx CR2 register value */
4645   tmpcr2 =  TIMx->CR2;
4646
4647   /* Get the TIMx CCMR2 register value */
4648   tmpccmrx = TIMx->CCMR2;
4649
4650   /* Reset the Output Compare mode and Capture/Compare selection Bits */
4651   tmpccmrx &= ~TIM_CCMR2_OC4M;
4652   tmpccmrx &= ~TIM_CCMR2_CC4S;
4653
4654   /* Select the Output Compare Mode */
4655   tmpccmrx |= (OC_Config->OCMode << 8);
4656
4657   /* Reset the Output Polarity level */
4658   tmpccer &= ~TIM_CCER_CC4P;
4659   /* Set the Output Compare Polarity */
4660   tmpccer |= (OC_Config->OCPolarity << 12);
4661
4662   /* Write to TIMx CR2 */
4663   TIMx->CR2 = tmpcr2;
4664
4665   /* Write to TIMx CCMR2 */
4666   TIMx->CCMR2 = tmpccmrx;
4667
4668   /* Set the Capture Compare Register value */
4669   TIMx->CCR4 = OC_Config->Pulse;
4670
4671   /* Write to TIMx CCER */
4672   TIMx->CCER = tmpccer;
4673 }
4674
4675 /**
4676   * @brief  Configure the TI1 as Input.
4677   * @param  TIMx to select the TIM peripheral.
4678   * @param  TIM_ICPolarity : The Input Polarity.
4679   *          This parameter can be one of the following values:
4680   *            @arg TIM_ICPOLARITY_RISING
4681   *            @arg TIM_ICPOLARITY_FALLING
4682   *            @arg TIM_ICPOLARITY_BOTHEDGE
4683   * @param  TIM_ICSelection: specifies the input to be used.
4684   *          This parameter can be one of the following values:
4685   *            @arg TIM_ICSELECTION_DIRECTTI:    TIM Input 1 is selected to be connected to IC1.
4686   *            @arg TIM_ICSELECTION_INDIRECTTI:  TIM Input 1 is selected to be connected to IC2.
4687   *            @arg TIM_ICSELECTION_TRC:         TIM Input 1 is selected to be connected to TRC.
4688   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
4689   *          This parameter must be a value between 0x00 and 0x0F.
4690   * @retval None
4691   */
4692 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4693                        uint32_t TIM_ICFilter)
4694 {
4695   uint32_t tmpccmr1 = 0;
4696   uint32_t tmpccer = 0;
4697
4698   /* Disable the Channel 1: Reset the CC1E Bit */
4699   TIMx->CCER &= ~TIM_CCER_CC1E;
4700   tmpccmr1 = TIMx->CCMR1;
4701   tmpccer = TIMx->CCER;
4702
4703   /* Select the Input */
4704   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4705   {
4706     tmpccmr1 &= ~TIM_CCMR1_CC1S;
4707     tmpccmr1 |= TIM_ICSelection;
4708   }
4709   else
4710   {
4711     tmpccmr1 |= TIM_CCMR1_CC1S_0;
4712   }
4713
4714   /* Set the filter */
4715   tmpccmr1 &= ~TIM_CCMR1_IC1F;
4716   tmpccmr1 |= (TIM_ICFilter << 4);
4717
4718   /* Select the Polarity and set the CC1E Bit */
4719   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4720   tmpccer |= TIM_ICPolarity;
4721
4722   /* Write to TIMx CCMR1 and CCER registers */
4723   TIMx->CCMR1 = tmpccmr1;
4724   TIMx->CCER = tmpccer;
4725 }
4726
4727 /**
4728   * @brief  Configure the Polarity and Filter for TI1.
4729   * @param  TIMx to select the TIM peripheral.
4730   * @param  TIM_ICPolarity : The Input Polarity.
4731   *          This parameter can be one of the following values:
4732   *            @arg TIM_ICPOLARITY_RISING
4733   *            @arg TIM_ICPOLARITY_FALLING
4734   *            @arg TIM_ICPOLARITY_BOTHEDGE
4735   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
4736   *          This parameter must be a value between 0x00 and 0x0F.
4737   * @retval None
4738   */
4739 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4740 {
4741   uint32_t tmpccmr1 = 0;
4742   uint32_t tmpccer = 0;
4743
4744   /* Disable the Channel 1: Reset the CC1E Bit */
4745   tmpccer = TIMx->CCER;
4746   TIMx->CCER &= ~TIM_CCER_CC1E;
4747   tmpccmr1 = TIMx->CCMR1;
4748
4749   /* Set the filter */
4750   tmpccmr1 &= ~TIM_CCMR1_IC1F;
4751   tmpccmr1 |= (TIM_ICFilter << 4);
4752
4753   /* Select the Polarity and set the CC1E Bit */
4754   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4755   tmpccer |= TIM_ICPolarity;
4756
4757   /* Write to TIMx CCMR1 and CCER registers */
4758   TIMx->CCMR1 = tmpccmr1;
4759   TIMx->CCER = tmpccer;
4760 }
4761
4762 /**
4763   * @brief  Configure the TI2 as Input.
4764   * @param  TIMx to select the TIM peripheral
4765   * @param  TIM_ICPolarity : The Input Polarity.
4766   *          This parameter can be one of the following values:
4767   *            @arg TIM_ICPOLARITY_RISING
4768   *            @arg TIM_ICPOLARITY_FALLING
4769   *            @arg TIM_ICPOLARITY_BOTHEDGE
4770   * @param  TIM_ICSelection: specifies the input to be used.
4771   *          This parameter can be one of the following values:
4772   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 2 is selected to be connected to IC2.
4773   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
4774   *            @arg TIM_ICSELECTION_TRC:        TIM Input 2 is selected to be connected to TRC.
4775   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
4776   *          This parameter must be a value between 0x00 and 0x0F.
4777   * @retval None
4778   */
4779 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4780                        uint32_t TIM_ICFilter)
4781 {
4782   uint32_t tmpccmr1 = 0;
4783   uint32_t tmpccer = 0;
4784
4785   /* Disable the Channel 2: Reset the CC2E Bit */
4786   TIMx->CCER &= ~TIM_CCER_CC2E;
4787   tmpccmr1 = TIMx->CCMR1;
4788   tmpccer = TIMx->CCER;
4789
4790   /* Select the Input */
4791   tmpccmr1 &= ~TIM_CCMR1_CC2S;
4792   tmpccmr1 |= (TIM_ICSelection << 8);
4793
4794   /* Set the filter */
4795   tmpccmr1 &= ~TIM_CCMR1_IC2F;
4796   tmpccmr1 |= (TIM_ICFilter << 12);
4797
4798   /* Select the Polarity and set the CC2E Bit */
4799   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4800   tmpccer |= (TIM_ICPolarity << 4);
4801
4802   /* Write to TIMx CCMR1 and CCER registers */
4803   TIMx->CCMR1 = tmpccmr1 ;
4804   TIMx->CCER = tmpccer;
4805 }
4806
4807 /**
4808   * @brief  Configure the Polarity and Filter for TI2.
4809   * @param  TIMx to select the TIM peripheral.
4810   * @param  TIM_ICPolarity : The Input Polarity.
4811   *          This parameter can be one of the following values:
4812   *            @arg TIM_ICPOLARITY_RISING
4813   *            @arg TIM_ICPOLARITY_FALLING
4814   *            @arg TIM_ICPOLARITY_BOTHEDGE
4815   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
4816   *          This parameter must be a value between 0x00 and 0x0F.
4817   * @retval None
4818   */
4819 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4820 {
4821   uint32_t tmpccmr1 = 0;
4822   uint32_t tmpccer = 0;
4823
4824   /* Disable the Channel 2: Reset the CC2E Bit */
4825   TIMx->CCER &= ~TIM_CCER_CC2E;
4826   tmpccmr1 = TIMx->CCMR1;
4827   tmpccer = TIMx->CCER;
4828
4829   /* Set the filter */
4830   tmpccmr1 &= ~TIM_CCMR1_IC2F;
4831   tmpccmr1 |= (TIM_ICFilter << 12);
4832
4833   /* Select the Polarity and set the CC2E Bit */
4834   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4835   tmpccer |= (TIM_ICPolarity << 4);
4836
4837   /* Write to TIMx CCMR1 and CCER registers */
4838   TIMx->CCMR1 = tmpccmr1 ;
4839   TIMx->CCER = tmpccer;
4840 }
4841
4842 /**
4843   * @brief  Configure the TI3 as Input.
4844   * @param  TIMx to select the TIM peripheral
4845   * @param  TIM_ICPolarity : The Input Polarity.
4846   *          This parameter can be one of the following values:
4847   *            @arg TIM_ICPOLARITY_RISING
4848   *            @arg TIM_ICPOLARITY_FALLING
4849   *            @arg TIM_ICPOLARITY_BOTHEDGE
4850   * @param  TIM_ICSelection: specifies the input to be used.
4851   *          This parameter can be one of the following values:
4852   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 3 is selected to be connected to IC3.
4853   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
4854   *            @arg TIM_ICSELECTION_TRC:        TIM Input 3 is selected to be connected to TRC.
4855   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
4856   *          This parameter must be a value between 0x00 and 0x0F.
4857   * @retval None
4858   */
4859 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4860                        uint32_t TIM_ICFilter)
4861 {
4862   uint32_t tmpccmr2 = 0;
4863   uint32_t tmpccer = 0;
4864
4865   /* Disable the Channel 3: Reset the CC3E Bit */
4866   TIMx->CCER &= ~TIM_CCER_CC3E;
4867   tmpccmr2 = TIMx->CCMR2;
4868   tmpccer = TIMx->CCER;
4869
4870   /* Select the Input */
4871   tmpccmr2 &= ~TIM_CCMR2_CC3S;
4872   tmpccmr2 |= TIM_ICSelection;
4873
4874   /* Set the filter */
4875   tmpccmr2 &= ~TIM_CCMR2_IC3F;
4876   tmpccmr2 |= (TIM_ICFilter << 4);
4877
4878   /* Select the Polarity and set the CC3E Bit */
4879   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
4880   tmpccer |= (TIM_ICPolarity << 8);
4881
4882   /* Write to TIMx CCMR2 and CCER registers */
4883   TIMx->CCMR2 = tmpccmr2;
4884   TIMx->CCER = tmpccer;
4885 }
4886
4887 /**
4888   * @brief  Configure the TI4 as Input.
4889   * @param  TIMx to select the TIM peripheral
4890   * @param  TIM_ICPolarity : The Input Polarity.
4891   *          This parameter can be one of the following values:
4892   *            @arg TIM_ICPOLARITY_RISING
4893   *            @arg TIM_ICPOLARITY_FALLING
4894   *            @arg TIM_ICPOLARITY_BOTHEDGE
4895   * @param  TIM_ICSelection: specifies the input to be used.
4896   *          This parameter can be one of the following values:
4897   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 4 is selected to be connected to IC4.
4898   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
4899   *            @arg TIM_ICSELECTION_TRC:        TIM Input 4 is selected to be connected to TRC.
4900   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
4901   *          This parameter must be a value between 0x00 and 0x0F.
4902   * @retval None
4903   */
4904 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4905                        uint32_t TIM_ICFilter)
4906 {
4907   uint32_t tmpccmr2 = 0;
4908   uint32_t tmpccer = 0;
4909
4910   /* Disable the Channel 4: Reset the CC4E Bit */
4911   TIMx->CCER &= ~TIM_CCER_CC4E;
4912   tmpccmr2 = TIMx->CCMR2;
4913   tmpccer = TIMx->CCER;
4914
4915   /* Select the Input */
4916   tmpccmr2 &= ~TIM_CCMR2_CC4S;
4917   tmpccmr2 |= (TIM_ICSelection << 8);
4918
4919   /* Set the filter */
4920   tmpccmr2 &= ~TIM_CCMR2_IC4F;
4921   tmpccmr2 |= (TIM_ICFilter << 12);
4922
4923   /* Select the Polarity and set the CC4E Bit */
4924   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
4925   tmpccer |= (TIM_ICPolarity << 12);
4926
4927   /* Write to TIMx CCMR2 and CCER registers */
4928   TIMx->CCMR2 = tmpccmr2;
4929   TIMx->CCER = tmpccer ;
4930 }
4931
4932 /**
4933   * @brief  Selects the Input Trigger source
4934   * @param  TIMx to select the TIM peripheral
4935   * @param  InputTriggerSource: The Input Trigger source.
4936   *          This parameter can be one of the following values:
4937   *            @arg TIM_TS_ITR0: Internal Trigger 0
4938   *            @arg TIM_TS_ITR1: Internal Trigger 1
4939   *            @arg TIM_TS_ITR2: Internal Trigger 2
4940   *            @arg TIM_TS_ITR3: Internal Trigger 3
4941   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
4942   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
4943   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
4944   *            @arg TIM_TS_ETRF: External Trigger input
4945   * @retval None
4946   */
4947 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
4948 {
4949   uint32_t tmpsmcr = 0;
4950
4951    /* Get the TIMx SMCR register value */
4952    tmpsmcr = TIMx->SMCR;
4953    /* Reset the TS Bits */
4954    tmpsmcr &= ~TIM_SMCR_TS;
4955    /* Set the Input Trigger source and the slave mode*/
4956    tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
4957    /* Write to TIMx SMCR */
4958    TIMx->SMCR = tmpsmcr;
4959 }
4960 /**
4961   * @brief  Configures the TIMx External Trigger (ETR).
4962   * @param  TIMx to select the TIM peripheral
4963   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
4964   *          This parameter can be one of the following values:
4965   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
4966   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
4967   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
4968   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
4969   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
4970   *          This parameter can be one of the following values:
4971   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
4972   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
4973   * @param  ExtTRGFilter: External Trigger Filter.
4974   *          This parameter must be a value between 0x00 and 0x0F
4975   * @retval None
4976   */
4977 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
4978                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
4979 {
4980   uint32_t tmpsmcr = 0;
4981
4982   tmpsmcr = TIMx->SMCR;
4983
4984   /* Reset the ETR Bits */
4985   tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4986
4987   /* Set the Prescaler, the Filter value and the Polarity */
4988   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
4989
4990   /* Write to TIMx SMCR */
4991   TIMx->SMCR = tmpsmcr;
4992 }
4993
4994 /**
4995   * @brief  Enables or disables the TIM Capture Compare Channel x.
4996   * @param  TIMx to select the TIM peripheral
4997   * @param  Channel: specifies the TIM Channel
4998   *          This parameter can be one of the following values:
4999   *            @arg TIM_CHANNEL_1: TIM Channel 1
5000   *            @arg TIM_CHANNEL_2: TIM Channel 2
5001   *            @arg TIM_CHANNEL_3: TIM Channel 3
5002   *            @arg TIM_CHANNEL_4: TIM Channel 4
5003   * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
5004   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5005   * @retval None
5006   */
5007 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
5008 {
5009   uint32_t tmp = 0;
5010
5011   /* Check the parameters */
5012   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
5013   assert_param(IS_TIM_CHANNELS(Channel));
5014
5015   tmp = (uint16_t)(TIM_CCER_CC1E << Channel);
5016
5017   /* Reset the CCxE Bit */
5018   TIMx->CCER &= ~tmp;
5019
5020   /* Set or reset the CCxE Bit */
5021   TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
5022 }
5023
5024 /**
5025   * @}
5026   */
5027
5028 #endif /* HAL_TIM_MODULE_ENABLED */
5029
5030
5031
5032 /**
5033   * @}
5034   */
5035
5036 /**
5037   * @}
5038   */
5039 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/