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git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h
1 /*******************************************************************************
3 * This software is supplied by Renesas Electronics Corporation and is only
4 * intended for use with Renesas products. No other uses are authorized. This
5 * software is owned by Renesas Electronics Corporation and is protected under
6 * all applicable laws, including copyright laws.
7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16 * Renesas reserves the right, without notice, to make changes to this software
17 * and to discontinue the availability of this software. By using this software,
18 * you agree to the additional terms and conditions found by accessing the
20 * http://www.renesas.com/disclaimer*
21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22 *******************************************************************************/
23 /*******************************************************************************
24 * File Name : mtu2_iodefine.h
27 * Description : Definition of I/O Register (V1.00a)
28 ******************************************************************************/
29 #ifndef MTU2_IODEFINE_H
30 #define MTU2_IODEFINE_H
31 /* ->SEC M1.10.1 : Not magic number */
35 volatile uint8_t TCR_2
; /* TCR_2 */
36 volatile uint8_t TMDR_2
; /* TMDR_2 */
37 volatile uint8_t TIOR_2
; /* TIOR_2 */
38 volatile uint8_t dummy520
[1]; /* */
39 volatile uint8_t TIER_2
; /* TIER_2 */
40 volatile uint8_t TSR_2
; /* TSR_2 */
41 volatile uint16_t TCNT_2
; /* TCNT_2 */
42 volatile uint16_t TGRA_2
; /* TGRA_2 */
43 volatile uint16_t TGRB_2
; /* TGRB_2 */
44 volatile uint8_t dummy521
[500]; /* */
45 volatile uint8_t TCR_3
; /* TCR_3 */
46 volatile uint8_t TCR_4
; /* TCR_4 */
47 volatile uint8_t TMDR_3
; /* TMDR_3 */
48 volatile uint8_t TMDR_4
; /* TMDR_4 */
49 volatile uint8_t TIORH_3
; /* TIORH_3 */
50 volatile uint8_t TIORL_3
; /* TIORL_3 */
51 volatile uint8_t TIORH_4
; /* TIORH_4 */
52 volatile uint8_t TIORL_4
; /* TIORL_4 */
53 volatile uint8_t TIER_3
; /* TIER_3 */
54 volatile uint8_t TIER_4
; /* TIER_4 */
55 volatile uint8_t TOER
; /* TOER */
56 volatile uint8_t dummy522
[2]; /* */
57 volatile uint8_t TGCR
; /* TGCR */
58 volatile uint8_t TOCR1
; /* TOCR1 */
59 volatile uint8_t TOCR2
; /* TOCR2 */
60 volatile uint16_t TCNT_3
; /* TCNT_3 */
61 volatile uint16_t TCNT_4
; /* TCNT_4 */
62 volatile uint16_t TCDR
; /* TCDR */
63 volatile uint16_t TDDR
; /* TDDR */
64 volatile uint16_t TGRA_3
; /* TGRA_3 */
65 volatile uint16_t TGRB_3
; /* TGRB_3 */
66 volatile uint16_t TGRA_4
; /* TGRA_4 */
67 volatile uint16_t TGRB_4
; /* TGRB_4 */
68 volatile uint16_t TCNTS
; /* TCNTS */
69 volatile uint16_t TCBR
; /* TCBR */
70 volatile uint16_t TGRC_3
; /* TGRC_3 */
71 volatile uint16_t TGRD_3
; /* TGRD_3 */
72 volatile uint16_t TGRC_4
; /* TGRC_4 */
73 volatile uint16_t TGRD_4
; /* TGRD_4 */
74 volatile uint8_t TSR_3
; /* TSR_3 */
75 volatile uint8_t TSR_4
; /* TSR_4 */
76 volatile uint8_t dummy523
[2]; /* */
77 volatile uint8_t TITCR
; /* TITCR */
78 volatile uint8_t TITCNT
; /* TITCNT */
79 volatile uint8_t TBTER
; /* TBTER */
80 volatile uint8_t dummy524
[1]; /* */
81 volatile uint8_t TDER
; /* TDER */
82 volatile uint8_t dummy525
[1]; /* */
83 volatile uint8_t TOLBR
; /* TOLBR */
84 volatile uint8_t dummy526
[1]; /* */
85 volatile uint8_t TBTM_3
; /* TBTM_3 */
86 volatile uint8_t TBTM_4
; /* TBTM_4 */
87 volatile uint8_t dummy527
[6]; /* */
88 volatile uint16_t TADCR
; /* TADCR */
89 volatile uint8_t dummy528
[2]; /* */
90 volatile uint16_t TADCORA_4
; /* TADCORA_4 */
91 volatile uint16_t TADCORB_4
; /* TADCORB_4 */
92 volatile uint16_t TADCOBRA_4
; /* TADCOBRA_4 */
93 volatile uint16_t TADCOBRB_4
; /* TADCOBRB_4 */
94 volatile uint8_t dummy529
[20]; /* */
95 volatile uint8_t TWCR
; /* TWCR */
96 volatile uint8_t dummy530
[31]; /* */
97 volatile uint8_t TSTR
; /* TSTR */
98 volatile uint8_t TSYR
; /* TSYR */
99 volatile uint8_t dummy531
[2]; /* */
100 volatile uint8_t TRWER
; /* TRWER */
101 volatile uint8_t dummy532
[123]; /* */
102 volatile uint8_t TCR_0
; /* TCR_0 */
103 volatile uint8_t TMDR_0
; /* TMDR_0 */
104 volatile uint8_t TIORH_0
; /* TIORH_0 */
105 volatile uint8_t TIORL_0
; /* TIORL_0 */
106 volatile uint8_t TIER_0
; /* TIER_0 */
107 volatile uint8_t TSR_0
; /* TSR_0 */
108 volatile uint16_t TCNT_0
; /* TCNT_0 */
109 volatile uint16_t TGRA_0
; /* TGRA_0 */
110 volatile uint16_t TGRB_0
; /* TGRB_0 */
111 volatile uint16_t TGRC_0
; /* TGRC_0 */
112 volatile uint16_t TGRD_0
; /* TGRD_0 */
113 volatile uint8_t dummy533
[16]; /* */
114 volatile uint16_t TGRE_0
; /* TGRE_0 */
115 volatile uint16_t TGRF_0
; /* TGRF_0 */
116 volatile uint8_t TIER2_0
; /* TIER2_0 */
117 volatile uint8_t TSR2_0
; /* TSR2_0 */
118 volatile uint8_t TBTM_0
; /* TBTM_0 */
119 volatile uint8_t dummy534
[89]; /* */
120 volatile uint8_t TCR_1
; /* TCR_1 */
121 volatile uint8_t TMDR_1
; /* TMDR_1 */
122 volatile uint8_t TIOR_1
; /* TIOR_1 */
123 volatile uint8_t dummy535
[1]; /* */
124 volatile uint8_t TIER_1
; /* TIER_1 */
125 volatile uint8_t TSR_1
; /* TSR_1 */
126 volatile uint16_t TCNT_1
; /* TCNT_1 */
127 volatile uint16_t TGRA_1
; /* TGRA_1 */
128 volatile uint16_t TGRB_1
; /* TGRB_1 */
129 volatile uint8_t dummy536
[4]; /* */
130 volatile uint8_t TICCR
; /* TICCR */
134 #define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
137 #define MTU2TCR_2 MTU2.TCR_2
138 #define MTU2TMDR_2 MTU2.TMDR_2
139 #define MTU2TIOR_2 MTU2.TIOR_2
140 #define MTU2TIER_2 MTU2.TIER_2
141 #define MTU2TSR_2 MTU2.TSR_2
142 #define MTU2TCNT_2 MTU2.TCNT_2
143 #define MTU2TGRA_2 MTU2.TGRA_2
144 #define MTU2TGRB_2 MTU2.TGRB_2
145 #define MTU2TCR_3 MTU2.TCR_3
146 #define MTU2TCR_4 MTU2.TCR_4
147 #define MTU2TMDR_3 MTU2.TMDR_3
148 #define MTU2TMDR_4 MTU2.TMDR_4
149 #define MTU2TIORH_3 MTU2.TIORH_3
150 #define MTU2TIORL_3 MTU2.TIORL_3
151 #define MTU2TIORH_4 MTU2.TIORH_4
152 #define MTU2TIORL_4 MTU2.TIORL_4
153 #define MTU2TIER_3 MTU2.TIER_3
154 #define MTU2TIER_4 MTU2.TIER_4
155 #define MTU2TOER MTU2.TOER
156 #define MTU2TGCR MTU2.TGCR
157 #define MTU2TOCR1 MTU2.TOCR1
158 #define MTU2TOCR2 MTU2.TOCR2
159 #define MTU2TCNT_3 MTU2.TCNT_3
160 #define MTU2TCNT_4 MTU2.TCNT_4
161 #define MTU2TCDR MTU2.TCDR
162 #define MTU2TDDR MTU2.TDDR
163 #define MTU2TGRA_3 MTU2.TGRA_3
164 #define MTU2TGRB_3 MTU2.TGRB_3
165 #define MTU2TGRA_4 MTU2.TGRA_4
166 #define MTU2TGRB_4 MTU2.TGRB_4
167 #define MTU2TCNTS MTU2.TCNTS
168 #define MTU2TCBR MTU2.TCBR
169 #define MTU2TGRC_3 MTU2.TGRC_3
170 #define MTU2TGRD_3 MTU2.TGRD_3
171 #define MTU2TGRC_4 MTU2.TGRC_4
172 #define MTU2TGRD_4 MTU2.TGRD_4
173 #define MTU2TSR_3 MTU2.TSR_3
174 #define MTU2TSR_4 MTU2.TSR_4
175 #define MTU2TITCR MTU2.TITCR
176 #define MTU2TITCNT MTU2.TITCNT
177 #define MTU2TBTER MTU2.TBTER
178 #define MTU2TDER MTU2.TDER
179 #define MTU2TOLBR MTU2.TOLBR
180 #define MTU2TBTM_3 MTU2.TBTM_3
181 #define MTU2TBTM_4 MTU2.TBTM_4
182 #define MTU2TADCR MTU2.TADCR
183 #define MTU2TADCORA_4 MTU2.TADCORA_4
184 #define MTU2TADCORB_4 MTU2.TADCORB_4
185 #define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
186 #define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
187 #define MTU2TWCR MTU2.TWCR
188 #define MTU2TSTR MTU2.TSTR
189 #define MTU2TSYR MTU2.TSYR
190 #define MTU2TRWER MTU2.TRWER
191 #define MTU2TCR_0 MTU2.TCR_0
192 #define MTU2TMDR_0 MTU2.TMDR_0
193 #define MTU2TIORH_0 MTU2.TIORH_0
194 #define MTU2TIORL_0 MTU2.TIORL_0
195 #define MTU2TIER_0 MTU2.TIER_0
196 #define MTU2TSR_0 MTU2.TSR_0
197 #define MTU2TCNT_0 MTU2.TCNT_0
198 #define MTU2TGRA_0 MTU2.TGRA_0
199 #define MTU2TGRB_0 MTU2.TGRB_0
200 #define MTU2TGRC_0 MTU2.TGRC_0
201 #define MTU2TGRD_0 MTU2.TGRD_0
202 #define MTU2TGRE_0 MTU2.TGRE_0
203 #define MTU2TGRF_0 MTU2.TGRF_0
204 #define MTU2TIER2_0 MTU2.TIER2_0
205 #define MTU2TSR2_0 MTU2.TSR2_0
206 #define MTU2TBTM_0 MTU2.TBTM_0
207 #define MTU2TCR_1 MTU2.TCR_1
208 #define MTU2TMDR_1 MTU2.TMDR_1
209 #define MTU2TIOR_1 MTU2.TIOR_1
210 #define MTU2TIER_1 MTU2.TIER_1
211 #define MTU2TSR_1 MTU2.TSR_1
212 #define MTU2TCNT_1 MTU2.TCNT_1
213 #define MTU2TGRA_1 MTU2.TGRA_1
214 #define MTU2TGRB_1 MTU2.TGRB_1
215 #define MTU2TICCR MTU2.TICCR
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