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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_Freescale / TARGET_KLXX / TARGET_KL05Z / TOOLCHAIN_ARM_STD / startup_MKL05Z4.s
1 ;/*****************************************************************************
2 ; * @file: startup_MKL25Z4.s
3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
4 ; * MKL05Z4
5 ; * @version: 1.1
6 ; * @date: 2012-6-21
7 ; *
8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
9 ;*
10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
11 ; *
12 ; *****************************************************************************/
13
14
15 __initial_sp EQU 0x20000C00 ; Top of RAM
16
17 PRESERVE8
18 THUMB
19
20
21 ; Vector Table Mapped to Address 0 at Reset
22
23 AREA RESET, DATA, READONLY
24 EXPORT __Vectors
25 EXPORT __Vectors_End
26 EXPORT __Vectors_Size
27
28 __Vectors DCD __initial_sp ; Top of Stack
29 DCD Reset_Handler ; Reset Handler
30 DCD NMI_Handler ; NMI Handler
31 DCD HardFault_Handler ; Hard Fault Handler
32 DCD 0 ; Reserved
33 DCD 0 ; Reserved
34 DCD 0 ; Reserved
35 DCD 0 ; Reserved
36 DCD 0 ; Reserved
37 DCD 0 ; Reserved
38 DCD 0 ; Reserved
39 DCD SVC_Handler ; SVCall Handler
40 DCD 0 ; Reserved
41 DCD 0 ; Reserved
42 DCD PendSV_Handler ; PendSV Handler
43 DCD SysTick_Handler ; SysTick Handler
44
45 ; External Interrupts
46 DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
47 DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
48 DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
49 DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
50 DCD Reserved20_IRQHandler ; Reserved interrupt 20
51 DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
52 DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
53 DCD LLW_IRQHandler ; Low Leakage Wakeup
54 DCD I2C0_IRQHandler ; I2C0 interrupt
55 DCD Reserved_25_IRQHandler ; Reserved interrupt 25
56 DCD SPI0_IRQHandler ; SPI0 interrupt
57 DCD Reserved_27_IRQHandler ; Reserved interrupt 27
58 DCD UART0_IRQHandler ; UART0 status and error interrupt
59 DCD Reserved_29_IRQHandler ; Reserved interrupt 29
60 DCD Reserved_30_IRQHandler ; Reserved interrupt 30
61 DCD ADC0_IRQHandler ; ADC0 interrupt
62 DCD CMP0_IRQHandler ; CMP0 interrupt
63 DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
64 DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
65 DCD Reserved_35_IRQHandler ; Reserved interrupt 35
66 DCD RTC_IRQHandler ; RTC interrupt
67 DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
68 DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
69 DCD Reserved_39_IRQHandler ; Reserved interrupt 39
70 DCD Reserved_40_IRQHandler ; Reserved interrupt 40
71 DCD DAC0_IRQHandler ; DAC0 interrupt
72 DCD TSI0_IRQHandler ; TSI0 interrupt
73 DCD MCG_IRQHandler ; MCG interrupt
74 DCD LPTimer_IRQHandler ; LPTimer interrupt
75 DCD Reserved_45_IRQHandler ; Reserved interrupt 45
76 DCD PORTA_IRQHandler ; Port A interrupt
77 DCD PORTB_IRQHandler ; Port B interrupt
78 __Vectors_End
79
80 __Vectors_Size EQU __Vectors_End - __Vectors
81
82 ; <h> Flash Configuration
83 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
84 ; <i> and security information that allows the MCU to restrict acces to the FTFL module.
85 ; <h> Backdoor Comparison Key
86 ; <o0> Backdoor Key 0 <0x0-0xFF:2>
87 ; <o1> Backdoor Key 1 <0x0-0xFF:2>
88 ; <o2> Backdoor Key 2 <0x0-0xFF:2>
89 ; <o3> Backdoor Key 3 <0x0-0xFF:2>
90 ; <o4> Backdoor Key 4 <0x0-0xFF:2>
91 ; <o5> Backdoor Key 5 <0x0-0xFF:2>
92 ; <o6> Backdoor Key 6 <0x0-0xFF:2>
93 ; <o7> Backdoor Key 7 <0x0-0xFF:2>
94 BackDoorK0 EQU 0xFF
95 BackDoorK1 EQU 0xFF
96 BackDoorK2 EQU 0xFF
97 BackDoorK3 EQU 0xFF
98 BackDoorK4 EQU 0xFF
99 BackDoorK5 EQU 0xFF
100 BackDoorK6 EQU 0xFF
101 BackDoorK7 EQU 0xFF
102 ; </h>
103 ; <h> Program flash protection bytes (FPROT)
104 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
105 ; <i> Each bit protects a 1/32 region of the program flash memory.
106 ; <h> FPROT0
107 ; <i> Program flash protection bytes
108 ; <i> 1/32 - 8/32 region
109 ; <o.0> FPROT0.0
110 ; <o.1> FPROT0.1
111 ; <o.2> FPROT0.2
112 ; <o.3> FPROT0.3
113 ; <o.4> FPROT0.4
114 ; <o.5> FPROT0.5
115 ; <o.6> FPROT0.6
116 ; <o.7> FPROT0.7
117 nFPROT0 EQU 0x00
118 FPROT0 EQU nFPROT0:EOR:0xFF
119 ; </h>
120 ; <h> FPROT1
121 ; <i> Program Flash Region Protect Register 1
122 ; <i> 9/32 - 16/32 region
123 ; <o.0> FPROT1.0
124 ; <o.1> FPROT1.1
125 ; <o.2> FPROT1.2
126 ; <o.3> FPROT1.3
127 ; <o.4> FPROT1.4
128 ; <o.5> FPROT1.5
129 ; <o.6> FPROT1.6
130 ; <o.7> FPROT1.7
131 nFPROT1 EQU 0x00
132 FPROT1 EQU nFPROT1:EOR:0xFF
133 ; </h>
134 ; <h> FPROT2
135 ; <i> Program Flash Region Protect Register 2
136 ; <i> 17/32 - 24/32 region
137 ; <o.0> FPROT2.0
138 ; <o.1> FPROT2.1
139 ; <o.2> FPROT2.2
140 ; <o.3> FPROT2.3
141 ; <o.4> FPROT2.4
142 ; <o.5> FPROT2.5
143 ; <o.6> FPROT2.6
144 ; <o.7> FPROT2.7
145 nFPROT2 EQU 0x00
146 FPROT2 EQU nFPROT2:EOR:0xFF
147 ; </h>
148 ; <h> FPROT3
149 ; <i> Program Flash Region Protect Register 3
150 ; <i> 25/32 - 32/32 region
151 ; <o.0> FPROT3.0
152 ; <o.1> FPROT3.1
153 ; <o.2> FPROT3.2
154 ; <o.3> FPROT3.3
155 ; <o.4> FPROT3.4
156 ; <o.5> FPROT3.5
157 ; <o.6> FPROT3.6
158 ; <o.7> FPROT3.7
159 nFPROT3 EQU 0x00
160 FPROT3 EQU nFPROT3:EOR:0xFF
161 ; </h>
162 ; </h>
163 ; </h>
164 ; <h> Flash nonvolatile option byte (FOPT)
165 ; <i> Allows the user to customize the operation of the MCU at boot time.
166 ; <o.0> LPBOOT0
167 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
168 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
169 ; <o.4> LPBOOT1
170 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
171 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
172 ; <o.2> NMI_DIS
173 ; <0=> NMI interrupts are always blocked
174 ; <1=> NMI pin/interrupts reset default to enabled
175 ; <o.3> RESET_PIN_CFG
176 ; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
177 ; <1=> RESET pin is dedicated
178 ; <o.3> FAST_INIT
179 ; <0=> Slower initialization
180 ; <1=> Fast Initialization
181 FOPT EQU 0xFF
182 ; </h>
183 ; <h> Flash security byte (FSEC)
184 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
185 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
186 ; <o.0..1> SEC
187 ; <2=> MCU security status is unsecure
188 ; <3=> MCU security status is secure
189 ; <i> Flash Security
190 ; <i> This bits define the security state of the MCU.
191 ; <o.2..3> FSLACC
192 ; <2=> Freescale factory access denied
193 ; <3=> Freescale factory access granted
194 ; <i> Freescale Failure Analysis Access Code
195 ; <i> This bits define the security state of the MCU.
196 ; <o.4..5> MEEN
197 ; <2=> Mass erase is disabled
198 ; <3=> Mass erase is enabled
199 ; <i> Mass Erase Enable Bits
200 ; <i> Enables and disables mass erase capability of the FTFL module
201 ; <o.6..7> KEYEN
202 ; <2=> Backdoor key access enabled
203 ; <3=> Backdoor key access disabled
204 ; <i> Backdoor key Security Enable
205 ; <i> These bits enable and disable backdoor key access to the FTFL module.
206 FSEC EQU 0xFE
207 ; </h>
208
209 IF :LNOT::DEF:RAM_TARGET
210 AREA |.ARM.__at_0x400|, CODE, READONLY
211 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
212 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
213 DCB FPROT0, FPROT1, FPROT2, FPROT3
214 DCB FSEC, FOPT, 0xFF, 0xFF
215 ENDIF
216
217 AREA |.text|, CODE, READONLY
218
219
220 ; Reset Handler
221
222 Reset_Handler PROC
223 EXPORT Reset_Handler [WEAK]
224 IMPORT SystemInit
225 IMPORT __main
226 LDR R0, =SystemInit
227 BLX R0
228 LDR R0, =__main
229 BX R0
230 ENDP
231
232
233 ; Dummy Exception Handlers (infinite loops which can be modified)
234
235 NMI_Handler PROC
236 EXPORT NMI_Handler [WEAK]
237 B .
238 ENDP
239 HardFault_Handler\
240 PROC
241 EXPORT HardFault_Handler [WEAK]
242 B .
243 ENDP
244 SVC_Handler PROC
245 EXPORT SVC_Handler [WEAK]
246 B .
247 ENDP
248 PendSV_Handler PROC
249 EXPORT PendSV_Handler [WEAK]
250 B .
251 ENDP
252 SysTick_Handler PROC
253 EXPORT SysTick_Handler [WEAK]
254 B .
255 ENDP
256
257 Default_Handler PROC
258 EXPORT DMA0_IRQHandler [WEAK]
259 EXPORT DMA1_IRQHandler [WEAK]
260 EXPORT DMA2_IRQHandler [WEAK]
261 EXPORT DMA3_IRQHandler [WEAK]
262 EXPORT Reserved20_IRQHandler [WEAK]
263 EXPORT FTFA_IRQHandler [WEAK]
264 EXPORT LVD_LVW_IRQHandler [WEAK]
265 EXPORT LLW_IRQHandler [WEAK]
266 EXPORT I2C0_IRQHandler [WEAK]
267 EXPORT Reserved_25_IRQHandler [WEAK]
268 EXPORT SPI0_IRQHandler [WEAK]
269 EXPORT Reserved_27_IRQHandler [WEAK]
270 EXPORT UART0_IRQHandler [WEAK]
271 EXPORT Reserved_29_IRQHandler [WEAK]
272 EXPORT Reserved_30_IRQHandler [WEAK]
273 EXPORT ADC0_IRQHandler [WEAK]
274 EXPORT CMP0_IRQHandler [WEAK]
275 EXPORT TPM0_IRQHandler [WEAK]
276 EXPORT TPM1_IRQHandler [WEAK]
277 EXPORT Reserved_35_IRQHandler [WEAK]
278 EXPORT RTC_IRQHandler [WEAK]
279 EXPORT RTC_Seconds_IRQHandler [WEAK]
280 EXPORT PIT_IRQHandler [WEAK]
281 EXPORT Reserved_39_IRQHandler [WEAK]
282 EXPORT Reserved_40_IRQHandler [WEAK]
283 EXPORT DAC0_IRQHandler [WEAK]
284 EXPORT TSI0_IRQHandler [WEAK]
285 EXPORT MCG_IRQHandler [WEAK]
286 EXPORT LPTimer_IRQHandler [WEAK]
287 EXPORT Reserved_45_IRQHandler [WEAK]
288 EXPORT PORTA_IRQHandler [WEAK]
289 EXPORT PORTB_IRQHandler [WEAK]
290 EXPORT DefaultISR [WEAK]
291
292 DMA0_IRQHandler
293 DMA1_IRQHandler
294 DMA2_IRQHandler
295 DMA3_IRQHandler
296 Reserved20_IRQHandler
297 FTFA_IRQHandler
298 LVD_LVW_IRQHandler
299 LLW_IRQHandler
300 I2C0_IRQHandler
301 Reserved_25_IRQHandler
302 SPI0_IRQHandler
303 Reserved_27_IRQHandler
304 UART0_IRQHandler
305 Reserved_29_IRQHandler
306 Reserved_30_IRQHandler
307 ADC0_IRQHandler
308 CMP0_IRQHandler
309 TPM0_IRQHandler
310 TPM1_IRQHandler
311 Reserved_35_IRQHandler
312 RTC_IRQHandler
313 RTC_Seconds_IRQHandler
314 PIT_IRQHandler
315 Reserved_39_IRQHandler
316 Reserved_40_IRQHandler
317 DAC0_IRQHandler
318 TSI0_IRQHandler
319 MCG_IRQHandler
320 LPTimer_IRQHandler
321 Reserved_45_IRQHandler
322 PORTA_IRQHandler
323 PORTB_IRQHandler
324 DefaultISR
325
326 B .
327
328 ENDP
329
330
331 ALIGN
332 END
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