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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_Freescale / TARGET_KLXX / TARGET_KL25Z / MKL25Z4.h
1 /*
2 ** ###################################################################
3 ** Processor: MKL25Z128VLK4
4 ** Compilers: ARM Compiler
5 ** Freescale C/C++ for Embedded ARM
6 ** GNU C Compiler
7 ** IAR ANSI C/C++ Compiler for ARM
8 **
9 ** Reference manual: KL25RM, Rev.1, Jun 2012
10 ** Version: rev. 1.1, 2012-06-21
11 **
12 ** Abstract:
13 ** CMSIS Peripheral Access Layer for MKL25Z4
14 **
15 ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
16 **
17 ** http: www.freescale.com
18 ** mail: support@freescale.com
19 **
20 ** Revisions:
21 ** - rev. 1.0 (2012-06-13)
22 ** Initial version.
23 ** - rev. 1.1 (2012-06-21)
24 ** Update according to reference manual rev. 1.
25 **
26 ** ###################################################################
27 */
28
29 /**
30 * @file MKL25Z4.h
31 * @version 1.1
32 * @date 2012-06-21
33 * @brief CMSIS Peripheral Access Layer for MKL25Z4
34 *
35 * CMSIS Peripheral Access Layer for MKL25Z4
36 */
37
38 #if !defined(MKL25Z4_H_)
39 #define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
40
41 /** Memory map major version (memory maps with equal major version number are
42 * compatible) */
43 #define MCU_MEM_MAP_VERSION 0x0100u
44 /** Memory map minor version */
45 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u
46
47
48 /* ----------------------------------------------------------------------------
49 -- Interrupt vector numbers
50 ---------------------------------------------------------------------------- */
51
52 /**
53 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
54 * @{
55 */
56
57 /** Interrupt Number Definitions */
58 typedef enum IRQn {
59 /* Core interrupts */
60 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
61 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
62 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
63 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
64 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
65
66 /* Device specific interrupts */
67 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
68 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
69 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
70 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
71 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
72 FTFA_IRQn = 5, /**< FTFA interrupt */
73 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
74 LLW_IRQn = 7, /**< Low Leakage Wakeup */
75 I2C0_IRQn = 8, /**< I2C0 interrupt */
76 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
77 SPI0_IRQn = 10, /**< SPI0 interrupt */
78 SPI1_IRQn = 11, /**< SPI1 interrupt */
79 UART0_IRQn = 12, /**< UART0 status/error interrupt */
80 UART1_IRQn = 13, /**< UART1 status/error interrupt */
81 UART2_IRQn = 14, /**< UART2 status/error interrupt */
82 ADC0_IRQn = 15, /**< ADC0 interrupt */
83 CMP0_IRQn = 16, /**< CMP0 interrupt */
84 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
85 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
86 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
87 RTC_IRQn = 20, /**< RTC interrupt */
88 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
89 PIT_IRQn = 22, /**< PIT timer interrupt */
90 Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
91 USB0_IRQn = 24, /**< USB0 interrupt */
92 DAC0_IRQn = 25, /**< DAC interrupt */
93 TSI0_IRQn = 26, /**< TSI0 interrupt */
94 MCG_IRQn = 27, /**< MCG interrupt */
95 LPTimer_IRQn = 28, /**< LPTimer interrupt */
96 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
97 PORTA_IRQn = 30, /**< Port A interrupt */
98 PORTD_IRQn = 31 /**< Port D interrupt */
99 } IRQn_Type;
100
101 /**
102 * @}
103 */ /* end of group Interrupt_vector_numbers */
104
105
106 /* ----------------------------------------------------------------------------
107 -- Cortex M0 Core Configuration
108 ---------------------------------------------------------------------------- */
109
110 /**
111 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
112 * @{
113 */
114
115 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
116 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
117 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
118 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
119 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
120
121 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
122 #include "system_MKL25Z4.h" /* Device specific configuration file */
123
124 /**
125 * @}
126 */ /* end of group Cortex_Core_Configuration */
127
128
129 /* ----------------------------------------------------------------------------
130 -- Device Peripheral Access Layer
131 ---------------------------------------------------------------------------- */
132
133 /**
134 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
135 * @{
136 */
137
138
139 /*
140 ** Start of section using anonymous unions
141 */
142
143 #if defined(__ARMCC_VERSION)
144 #pragma push
145 #pragma anon_unions
146 #elif defined(__CWCC__)
147 #pragma push
148 #pragma cpp_extensions on
149 #elif defined(__GNUC__)
150 /* anonymous unions are enabled by default */
151 #elif defined(__IAR_SYSTEMS_ICC__)
152 #pragma language=extended
153 #else
154 #error Not supported compiler type
155 #endif
156
157 /* ----------------------------------------------------------------------------
158 -- ADC Peripheral Access Layer
159 ---------------------------------------------------------------------------- */
160
161 /**
162 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
163 * @{
164 */
165
166 /** ADC - Register Layout Typedef */
167 typedef struct {
168 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
169 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
170 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
171 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
172 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
173 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
174 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
175 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
176 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
177 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
178 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
179 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
180 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
181 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
182 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
183 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
184 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
185 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
186 uint8_t RESERVED_0[4];
187 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
188 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
189 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
190 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
191 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
192 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
193 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
194 } ADC_Type;
195
196 /* ----------------------------------------------------------------------------
197 -- ADC Register Masks
198 ---------------------------------------------------------------------------- */
199
200 /**
201 * @addtogroup ADC_Register_Masks ADC Register Masks
202 * @{
203 */
204
205 /* SC1 Bit Fields */
206 #define ADC_SC1_ADCH_MASK 0x1Fu
207 #define ADC_SC1_ADCH_SHIFT 0
208 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
209 #define ADC_SC1_DIFF_MASK 0x20u
210 #define ADC_SC1_DIFF_SHIFT 5
211 #define ADC_SC1_AIEN_MASK 0x40u
212 #define ADC_SC1_AIEN_SHIFT 6
213 #define ADC_SC1_COCO_MASK 0x80u
214 #define ADC_SC1_COCO_SHIFT 7
215 /* CFG1 Bit Fields */
216 #define ADC_CFG1_ADICLK_MASK 0x3u
217 #define ADC_CFG1_ADICLK_SHIFT 0
218 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
219 #define ADC_CFG1_MODE_MASK 0xCu
220 #define ADC_CFG1_MODE_SHIFT 2
221 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
222 #define ADC_CFG1_ADLSMP_MASK 0x10u
223 #define ADC_CFG1_ADLSMP_SHIFT 4
224 #define ADC_CFG1_ADIV_MASK 0x60u
225 #define ADC_CFG1_ADIV_SHIFT 5
226 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
227 #define ADC_CFG1_ADLPC_MASK 0x80u
228 #define ADC_CFG1_ADLPC_SHIFT 7
229 /* CFG2 Bit Fields */
230 #define ADC_CFG2_ADLSTS_MASK 0x3u
231 #define ADC_CFG2_ADLSTS_SHIFT 0
232 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
233 #define ADC_CFG2_ADHSC_MASK 0x4u
234 #define ADC_CFG2_ADHSC_SHIFT 2
235 #define ADC_CFG2_ADACKEN_MASK 0x8u
236 #define ADC_CFG2_ADACKEN_SHIFT 3
237 #define ADC_CFG2_MUXSEL_MASK 0x10u
238 #define ADC_CFG2_MUXSEL_SHIFT 4
239 /* R Bit Fields */
240 #define ADC_R_D_MASK 0xFFFFu
241 #define ADC_R_D_SHIFT 0
242 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
243 /* CV1 Bit Fields */
244 #define ADC_CV1_CV_MASK 0xFFFFu
245 #define ADC_CV1_CV_SHIFT 0
246 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
247 /* CV2 Bit Fields */
248 #define ADC_CV2_CV_MASK 0xFFFFu
249 #define ADC_CV2_CV_SHIFT 0
250 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
251 /* SC2 Bit Fields */
252 #define ADC_SC2_REFSEL_MASK 0x3u
253 #define ADC_SC2_REFSEL_SHIFT 0
254 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
255 #define ADC_SC2_DMAEN_MASK 0x4u
256 #define ADC_SC2_DMAEN_SHIFT 2
257 #define ADC_SC2_ACREN_MASK 0x8u
258 #define ADC_SC2_ACREN_SHIFT 3
259 #define ADC_SC2_ACFGT_MASK 0x10u
260 #define ADC_SC2_ACFGT_SHIFT 4
261 #define ADC_SC2_ACFE_MASK 0x20u
262 #define ADC_SC2_ACFE_SHIFT 5
263 #define ADC_SC2_ADTRG_MASK 0x40u
264 #define ADC_SC2_ADTRG_SHIFT 6
265 #define ADC_SC2_ADACT_MASK 0x80u
266 #define ADC_SC2_ADACT_SHIFT 7
267 /* SC3 Bit Fields */
268 #define ADC_SC3_AVGS_MASK 0x3u
269 #define ADC_SC3_AVGS_SHIFT 0
270 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
271 #define ADC_SC3_AVGE_MASK 0x4u
272 #define ADC_SC3_AVGE_SHIFT 2
273 #define ADC_SC3_ADCO_MASK 0x8u
274 #define ADC_SC3_ADCO_SHIFT 3
275 #define ADC_SC3_CALF_MASK 0x40u
276 #define ADC_SC3_CALF_SHIFT 6
277 #define ADC_SC3_CAL_MASK 0x80u
278 #define ADC_SC3_CAL_SHIFT 7
279 /* OFS Bit Fields */
280 #define ADC_OFS_OFS_MASK 0xFFFFu
281 #define ADC_OFS_OFS_SHIFT 0
282 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
283 /* PG Bit Fields */
284 #define ADC_PG_PG_MASK 0xFFFFu
285 #define ADC_PG_PG_SHIFT 0
286 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
287 /* MG Bit Fields */
288 #define ADC_MG_MG_MASK 0xFFFFu
289 #define ADC_MG_MG_SHIFT 0
290 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
291 /* CLPD Bit Fields */
292 #define ADC_CLPD_CLPD_MASK 0x3Fu
293 #define ADC_CLPD_CLPD_SHIFT 0
294 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
295 /* CLPS Bit Fields */
296 #define ADC_CLPS_CLPS_MASK 0x3Fu
297 #define ADC_CLPS_CLPS_SHIFT 0
298 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
299 /* CLP4 Bit Fields */
300 #define ADC_CLP4_CLP4_MASK 0x3FFu
301 #define ADC_CLP4_CLP4_SHIFT 0
302 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
303 /* CLP3 Bit Fields */
304 #define ADC_CLP3_CLP3_MASK 0x1FFu
305 #define ADC_CLP3_CLP3_SHIFT 0
306 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
307 /* CLP2 Bit Fields */
308 #define ADC_CLP2_CLP2_MASK 0xFFu
309 #define ADC_CLP2_CLP2_SHIFT 0
310 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
311 /* CLP1 Bit Fields */
312 #define ADC_CLP1_CLP1_MASK 0x7Fu
313 #define ADC_CLP1_CLP1_SHIFT 0
314 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
315 /* CLP0 Bit Fields */
316 #define ADC_CLP0_CLP0_MASK 0x3Fu
317 #define ADC_CLP0_CLP0_SHIFT 0
318 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
319 /* CLMD Bit Fields */
320 #define ADC_CLMD_CLMD_MASK 0x3Fu
321 #define ADC_CLMD_CLMD_SHIFT 0
322 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
323 /* CLMS Bit Fields */
324 #define ADC_CLMS_CLMS_MASK 0x3Fu
325 #define ADC_CLMS_CLMS_SHIFT 0
326 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
327 /* CLM4 Bit Fields */
328 #define ADC_CLM4_CLM4_MASK 0x3FFu
329 #define ADC_CLM4_CLM4_SHIFT 0
330 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
331 /* CLM3 Bit Fields */
332 #define ADC_CLM3_CLM3_MASK 0x1FFu
333 #define ADC_CLM3_CLM3_SHIFT 0
334 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
335 /* CLM2 Bit Fields */
336 #define ADC_CLM2_CLM2_MASK 0xFFu
337 #define ADC_CLM2_CLM2_SHIFT 0
338 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
339 /* CLM1 Bit Fields */
340 #define ADC_CLM1_CLM1_MASK 0x7Fu
341 #define ADC_CLM1_CLM1_SHIFT 0
342 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
343 /* CLM0 Bit Fields */
344 #define ADC_CLM0_CLM0_MASK 0x3Fu
345 #define ADC_CLM0_CLM0_SHIFT 0
346 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
347
348 /**
349 * @}
350 */ /* end of group ADC_Register_Masks */
351
352
353 /* ADC - Peripheral instance base addresses */
354 /** Peripheral ADC0 base address */
355 #define ADC0_BASE (0x4003B000u)
356 /** Peripheral ADC0 base pointer */
357 #define ADC0 ((ADC_Type *)ADC0_BASE)
358 /** Array initializer of ADC peripheral base pointers */
359 #define ADC_BASES { ADC0 }
360
361 /**
362 * @}
363 */ /* end of group ADC_Peripheral_Access_Layer */
364
365
366 /* ----------------------------------------------------------------------------
367 -- CMP Peripheral Access Layer
368 ---------------------------------------------------------------------------- */
369
370 /**
371 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
372 * @{
373 */
374
375 /** CMP - Register Layout Typedef */
376 typedef struct {
377 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
378 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
379 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
380 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
381 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
382 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
383 } CMP_Type;
384
385 /* ----------------------------------------------------------------------------
386 -- CMP Register Masks
387 ---------------------------------------------------------------------------- */
388
389 /**
390 * @addtogroup CMP_Register_Masks CMP Register Masks
391 * @{
392 */
393
394 /* CR0 Bit Fields */
395 #define CMP_CR0_HYSTCTR_MASK 0x3u
396 #define CMP_CR0_HYSTCTR_SHIFT 0
397 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
398 #define CMP_CR0_FILTER_CNT_MASK 0x70u
399 #define CMP_CR0_FILTER_CNT_SHIFT 4
400 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
401 /* CR1 Bit Fields */
402 #define CMP_CR1_EN_MASK 0x1u
403 #define CMP_CR1_EN_SHIFT 0
404 #define CMP_CR1_OPE_MASK 0x2u
405 #define CMP_CR1_OPE_SHIFT 1
406 #define CMP_CR1_COS_MASK 0x4u
407 #define CMP_CR1_COS_SHIFT 2
408 #define CMP_CR1_INV_MASK 0x8u
409 #define CMP_CR1_INV_SHIFT 3
410 #define CMP_CR1_PMODE_MASK 0x10u
411 #define CMP_CR1_PMODE_SHIFT 4
412 #define CMP_CR1_TRIGM_MASK 0x20u
413 #define CMP_CR1_TRIGM_SHIFT 5
414 #define CMP_CR1_WE_MASK 0x40u
415 #define CMP_CR1_WE_SHIFT 6
416 #define CMP_CR1_SE_MASK 0x80u
417 #define CMP_CR1_SE_SHIFT 7
418 /* FPR Bit Fields */
419 #define CMP_FPR_FILT_PER_MASK 0xFFu
420 #define CMP_FPR_FILT_PER_SHIFT 0
421 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
422 /* SCR Bit Fields */
423 #define CMP_SCR_COUT_MASK 0x1u
424 #define CMP_SCR_COUT_SHIFT 0
425 #define CMP_SCR_CFF_MASK 0x2u
426 #define CMP_SCR_CFF_SHIFT 1
427 #define CMP_SCR_CFR_MASK 0x4u
428 #define CMP_SCR_CFR_SHIFT 2
429 #define CMP_SCR_IEF_MASK 0x8u
430 #define CMP_SCR_IEF_SHIFT 3
431 #define CMP_SCR_IER_MASK 0x10u
432 #define CMP_SCR_IER_SHIFT 4
433 #define CMP_SCR_DMAEN_MASK 0x40u
434 #define CMP_SCR_DMAEN_SHIFT 6
435 /* DACCR Bit Fields */
436 #define CMP_DACCR_VOSEL_MASK 0x3Fu
437 #define CMP_DACCR_VOSEL_SHIFT 0
438 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
439 #define CMP_DACCR_VRSEL_MASK 0x40u
440 #define CMP_DACCR_VRSEL_SHIFT 6
441 #define CMP_DACCR_DACEN_MASK 0x80u
442 #define CMP_DACCR_DACEN_SHIFT 7
443 /* MUXCR Bit Fields */
444 #define CMP_MUXCR_MSEL_MASK 0x7u
445 #define CMP_MUXCR_MSEL_SHIFT 0
446 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
447 #define CMP_MUXCR_PSEL_MASK 0x38u
448 #define CMP_MUXCR_PSEL_SHIFT 3
449 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
450 #define CMP_MUXCR_PSTM_MASK 0x40u
451 #define CMP_MUXCR_PSTM_SHIFT 6
452
453 /**
454 * @}
455 */ /* end of group CMP_Register_Masks */
456
457
458 /* CMP - Peripheral instance base addresses */
459 /** Peripheral CMP0 base address */
460 #define CMP0_BASE (0x40073000u)
461 /** Peripheral CMP0 base pointer */
462 #define CMP0 ((CMP_Type *)CMP0_BASE)
463 /** Array initializer of CMP peripheral base pointers */
464 #define CMP_BASES { CMP0 }
465
466 /**
467 * @}
468 */ /* end of group CMP_Peripheral_Access_Layer */
469
470
471 /* ----------------------------------------------------------------------------
472 -- DAC Peripheral Access Layer
473 ---------------------------------------------------------------------------- */
474
475 /**
476 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
477 * @{
478 */
479
480 /** DAC - Register Layout Typedef */
481 typedef struct {
482 struct { /* offset: 0x0, array step: 0x2 */
483 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
484 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
485 } DAT[2];
486 uint8_t RESERVED_0[28];
487 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
488 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
489 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
490 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
491 } DAC_Type;
492
493 /* ----------------------------------------------------------------------------
494 -- DAC Register Masks
495 ---------------------------------------------------------------------------- */
496
497 /**
498 * @addtogroup DAC_Register_Masks DAC Register Masks
499 * @{
500 */
501
502 /* DATL Bit Fields */
503 #define DAC_DATL_DATA0_MASK 0xFFu
504 #define DAC_DATL_DATA0_SHIFT 0
505 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
506 /* DATH Bit Fields */
507 #define DAC_DATH_DATA1_MASK 0xFu
508 #define DAC_DATH_DATA1_SHIFT 0
509 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
510 /* SR Bit Fields */
511 #define DAC_SR_DACBFRPBF_MASK 0x1u
512 #define DAC_SR_DACBFRPBF_SHIFT 0
513 #define DAC_SR_DACBFRPTF_MASK 0x2u
514 #define DAC_SR_DACBFRPTF_SHIFT 1
515 /* C0 Bit Fields */
516 #define DAC_C0_DACBBIEN_MASK 0x1u
517 #define DAC_C0_DACBBIEN_SHIFT 0
518 #define DAC_C0_DACBTIEN_MASK 0x2u
519 #define DAC_C0_DACBTIEN_SHIFT 1
520 #define DAC_C0_LPEN_MASK 0x8u
521 #define DAC_C0_LPEN_SHIFT 3
522 #define DAC_C0_DACSWTRG_MASK 0x10u
523 #define DAC_C0_DACSWTRG_SHIFT 4
524 #define DAC_C0_DACTRGSEL_MASK 0x20u
525 #define DAC_C0_DACTRGSEL_SHIFT 5
526 #define DAC_C0_DACRFS_MASK 0x40u
527 #define DAC_C0_DACRFS_SHIFT 6
528 #define DAC_C0_DACEN_MASK 0x80u
529 #define DAC_C0_DACEN_SHIFT 7
530 /* C1 Bit Fields */
531 #define DAC_C1_DACBFEN_MASK 0x1u
532 #define DAC_C1_DACBFEN_SHIFT 0
533 #define DAC_C1_DACBFMD_MASK 0x4u
534 #define DAC_C1_DACBFMD_SHIFT 2
535 #define DAC_C1_DMAEN_MASK 0x80u
536 #define DAC_C1_DMAEN_SHIFT 7
537 /* C2 Bit Fields */
538 #define DAC_C2_DACBFUP_MASK 0x1u
539 #define DAC_C2_DACBFUP_SHIFT 0
540 #define DAC_C2_DACBFRP_MASK 0x10u
541 #define DAC_C2_DACBFRP_SHIFT 4
542
543 /**
544 * @}
545 */ /* end of group DAC_Register_Masks */
546
547
548 /* DAC - Peripheral instance base addresses */
549 /** Peripheral DAC0 base address */
550 #define DAC0_BASE (0x4003F000u)
551 /** Peripheral DAC0 base pointer */
552 #define DAC0 ((DAC_Type *)DAC0_BASE)
553 /** Array initializer of DAC peripheral base pointers */
554 #define DAC_BASES { DAC0 }
555
556 /**
557 * @}
558 */ /* end of group DAC_Peripheral_Access_Layer */
559
560
561 /* ----------------------------------------------------------------------------
562 -- DMA Peripheral Access Layer
563 ---------------------------------------------------------------------------- */
564
565 /**
566 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
567 * @{
568 */
569
570 /** DMA - Register Layout Typedef */
571 typedef struct {
572 union { /* offset: 0x0 */
573 __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
574 };
575 uint8_t RESERVED_0[252];
576 struct { /* offset: 0x100, array step: 0x10 */
577 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
578 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
579 union { /* offset: 0x108, array step: 0x10 */
580 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
581 struct { /* offset: 0x108, array step: 0x10 */
582 uint8_t RESERVED_0[3];
583 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
584 } DMA_DSR_ACCESS8BIT;
585 };
586 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
587 } DMA[4];
588 } DMA_Type;
589
590 /* ----------------------------------------------------------------------------
591 -- DMA Register Masks
592 ---------------------------------------------------------------------------- */
593
594 /**
595 * @addtogroup DMA_Register_Masks DMA Register Masks
596 * @{
597 */
598
599 /* REQC_ARR Bit Fields */
600 #define DMA_REQC_ARR_DMAC_MASK 0xFu
601 #define DMA_REQC_ARR_DMAC_SHIFT 0
602 #define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
603 #define DMA_REQC_ARR_CFSM_MASK 0x80u
604 #define DMA_REQC_ARR_CFSM_SHIFT 7
605 /* SAR Bit Fields */
606 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
607 #define DMA_SAR_SAR_SHIFT 0
608 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
609 /* DAR Bit Fields */
610 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
611 #define DMA_DAR_DAR_SHIFT 0
612 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
613 /* DSR_BCR Bit Fields */
614 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
615 #define DMA_DSR_BCR_BCR_SHIFT 0
616 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
617 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
618 #define DMA_DSR_BCR_DONE_SHIFT 24
619 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
620 #define DMA_DSR_BCR_BSY_SHIFT 25
621 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
622 #define DMA_DSR_BCR_REQ_SHIFT 26
623 #define DMA_DSR_BCR_BED_MASK 0x10000000u
624 #define DMA_DSR_BCR_BED_SHIFT 28
625 #define DMA_DSR_BCR_BES_MASK 0x20000000u
626 #define DMA_DSR_BCR_BES_SHIFT 29
627 #define DMA_DSR_BCR_CE_MASK 0x40000000u
628 #define DMA_DSR_BCR_CE_SHIFT 30
629 /* DCR Bit Fields */
630 #define DMA_DCR_LCH2_MASK 0x3u
631 #define DMA_DCR_LCH2_SHIFT 0
632 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
633 #define DMA_DCR_LCH1_MASK 0xCu
634 #define DMA_DCR_LCH1_SHIFT 2
635 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
636 #define DMA_DCR_LINKCC_MASK 0x30u
637 #define DMA_DCR_LINKCC_SHIFT 4
638 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
639 #define DMA_DCR_D_REQ_MASK 0x80u
640 #define DMA_DCR_D_REQ_SHIFT 7
641 #define DMA_DCR_DMOD_MASK 0xF00u
642 #define DMA_DCR_DMOD_SHIFT 8
643 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
644 #define DMA_DCR_SMOD_MASK 0xF000u
645 #define DMA_DCR_SMOD_SHIFT 12
646 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
647 #define DMA_DCR_START_MASK 0x10000u
648 #define DMA_DCR_START_SHIFT 16
649 #define DMA_DCR_DSIZE_MASK 0x60000u
650 #define DMA_DCR_DSIZE_SHIFT 17
651 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
652 #define DMA_DCR_DINC_MASK 0x80000u
653 #define DMA_DCR_DINC_SHIFT 19
654 #define DMA_DCR_SSIZE_MASK 0x300000u
655 #define DMA_DCR_SSIZE_SHIFT 20
656 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
657 #define DMA_DCR_SINC_MASK 0x400000u
658 #define DMA_DCR_SINC_SHIFT 22
659 #define DMA_DCR_EADREQ_MASK 0x800000u
660 #define DMA_DCR_EADREQ_SHIFT 23
661 #define DMA_DCR_AA_MASK 0x10000000u
662 #define DMA_DCR_AA_SHIFT 28
663 #define DMA_DCR_CS_MASK 0x20000000u
664 #define DMA_DCR_CS_SHIFT 29
665 #define DMA_DCR_ERQ_MASK 0x40000000u
666 #define DMA_DCR_ERQ_SHIFT 30
667 #define DMA_DCR_EINT_MASK 0x80000000u
668 #define DMA_DCR_EINT_SHIFT 31
669
670 /**
671 * @}
672 */ /* end of group DMA_Register_Masks */
673
674
675 /* DMA - Peripheral instance base addresses */
676 /** Peripheral DMA base address */
677 #define DMA_BASE (0x40008000u)
678 /** Peripheral DMA base pointer */
679 #define DMA0 ((DMA_Type *)DMA_BASE)
680 /** Array initializer of DMA peripheral base pointers */
681 #define DMA_BASES { DMA0 }
682
683 /**
684 * @}
685 */ /* end of group DMA_Peripheral_Access_Layer */
686
687
688 /* ----------------------------------------------------------------------------
689 -- DMAMUX Peripheral Access Layer
690 ---------------------------------------------------------------------------- */
691
692 /**
693 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
694 * @{
695 */
696
697 /** DMAMUX - Register Layout Typedef */
698 typedef struct {
699 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
700 } DMAMUX_Type;
701
702 /* ----------------------------------------------------------------------------
703 -- DMAMUX Register Masks
704 ---------------------------------------------------------------------------- */
705
706 /**
707 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
708 * @{
709 */
710
711 /* CHCFG Bit Fields */
712 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
713 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
714 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
715 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
716 #define DMAMUX_CHCFG_TRIG_SHIFT 6
717 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
718 #define DMAMUX_CHCFG_ENBL_SHIFT 7
719
720 /**
721 * @}
722 */ /* end of group DMAMUX_Register_Masks */
723
724
725 /* DMAMUX - Peripheral instance base addresses */
726 /** Peripheral DMAMUX0 base address */
727 #define DMAMUX0_BASE (0x40021000u)
728 /** Peripheral DMAMUX0 base pointer */
729 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
730 /** Array initializer of DMAMUX peripheral base pointers */
731 #define DMAMUX_BASES { DMAMUX0 }
732
733 /**
734 * @}
735 */ /* end of group DMAMUX_Peripheral_Access_Layer */
736
737
738 /* ----------------------------------------------------------------------------
739 -- FGPIO Peripheral Access Layer
740 ---------------------------------------------------------------------------- */
741
742 /**
743 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
744 * @{
745 */
746
747 /** FGPIO - Register Layout Typedef */
748 typedef struct {
749 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
750 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
751 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
752 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
753 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
754 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
755 } FGPIO_Type;
756
757 /* ----------------------------------------------------------------------------
758 -- FGPIO Register Masks
759 ---------------------------------------------------------------------------- */
760
761 /**
762 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
763 * @{
764 */
765
766 /* PDOR Bit Fields */
767 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
768 #define FGPIO_PDOR_PDO_SHIFT 0
769 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
770 /* PSOR Bit Fields */
771 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
772 #define FGPIO_PSOR_PTSO_SHIFT 0
773 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
774 /* PCOR Bit Fields */
775 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
776 #define FGPIO_PCOR_PTCO_SHIFT 0
777 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
778 /* PTOR Bit Fields */
779 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
780 #define FGPIO_PTOR_PTTO_SHIFT 0
781 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
782 /* PDIR Bit Fields */
783 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
784 #define FGPIO_PDIR_PDI_SHIFT 0
785 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
786 /* PDDR Bit Fields */
787 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
788 #define FGPIO_PDDR_PDD_SHIFT 0
789 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
790
791 /**
792 * @}
793 */ /* end of group FGPIO_Register_Masks */
794
795
796 /* FGPIO - Peripheral instance base addresses */
797 /** Peripheral FPTA base address */
798 #define FPTA_BASE (0xF80FF000u)
799 /** Peripheral FPTA base pointer */
800 #define FPTA ((FGPIO_Type *)FPTA_BASE)
801 /** Peripheral FPTB base address */
802 #define FPTB_BASE (0xF80FF040u)
803 /** Peripheral FPTB base pointer */
804 #define FPTB ((FGPIO_Type *)FPTB_BASE)
805 /** Peripheral FPTC base address */
806 #define FPTC_BASE (0xF80FF080u)
807 /** Peripheral FPTC base pointer */
808 #define FPTC ((FGPIO_Type *)FPTC_BASE)
809 /** Peripheral FPTD base address */
810 #define FPTD_BASE (0xF80FF0C0u)
811 /** Peripheral FPTD base pointer */
812 #define FPTD ((FGPIO_Type *)FPTD_BASE)
813 /** Peripheral FPTE base address */
814 #define FPTE_BASE (0xF80FF100u)
815 /** Peripheral FPTE base pointer */
816 #define FPTE ((FGPIO_Type *)FPTE_BASE)
817 /** Array initializer of FGPIO peripheral base pointers */
818 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
819
820 /**
821 * @}
822 */ /* end of group FGPIO_Peripheral_Access_Layer */
823
824
825 /* ----------------------------------------------------------------------------
826 -- FTFA Peripheral Access Layer
827 ---------------------------------------------------------------------------- */
828
829 /**
830 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
831 * @{
832 */
833
834 /** FTFA - Register Layout Typedef */
835 typedef struct {
836 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
837 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
838 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
839 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
840 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
841 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
842 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
843 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
844 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
845 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
846 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
847 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
848 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
849 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
850 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
851 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
852 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
853 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
854 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
855 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
856 } FTFA_Type;
857
858 /* ----------------------------------------------------------------------------
859 -- FTFA Register Masks
860 ---------------------------------------------------------------------------- */
861
862 /**
863 * @addtogroup FTFA_Register_Masks FTFA Register Masks
864 * @{
865 */
866
867 /* FSTAT Bit Fields */
868 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
869 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
870 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
871 #define FTFA_FSTAT_FPVIOL_SHIFT 4
872 #define FTFA_FSTAT_ACCERR_MASK 0x20u
873 #define FTFA_FSTAT_ACCERR_SHIFT 5
874 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
875 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
876 #define FTFA_FSTAT_CCIF_MASK 0x80u
877 #define FTFA_FSTAT_CCIF_SHIFT 7
878 /* FCNFG Bit Fields */
879 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
880 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
881 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
882 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
883 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
884 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
885 #define FTFA_FCNFG_CCIE_MASK 0x80u
886 #define FTFA_FCNFG_CCIE_SHIFT 7
887 /* FSEC Bit Fields */
888 #define FTFA_FSEC_SEC_MASK 0x3u
889 #define FTFA_FSEC_SEC_SHIFT 0
890 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
891 #define FTFA_FSEC_FSLACC_MASK 0xCu
892 #define FTFA_FSEC_FSLACC_SHIFT 2
893 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
894 #define FTFA_FSEC_MEEN_MASK 0x30u
895 #define FTFA_FSEC_MEEN_SHIFT 4
896 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
897 #define FTFA_FSEC_KEYEN_MASK 0xC0u
898 #define FTFA_FSEC_KEYEN_SHIFT 6
899 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
900 /* FOPT Bit Fields */
901 #define FTFA_FOPT_OPT_MASK 0xFFu
902 #define FTFA_FOPT_OPT_SHIFT 0
903 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
904 /* FCCOB3 Bit Fields */
905 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
906 #define FTFA_FCCOB3_CCOBn_SHIFT 0
907 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
908 /* FCCOB2 Bit Fields */
909 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
910 #define FTFA_FCCOB2_CCOBn_SHIFT 0
911 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
912 /* FCCOB1 Bit Fields */
913 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
914 #define FTFA_FCCOB1_CCOBn_SHIFT 0
915 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
916 /* FCCOB0 Bit Fields */
917 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
918 #define FTFA_FCCOB0_CCOBn_SHIFT 0
919 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
920 /* FCCOB7 Bit Fields */
921 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
922 #define FTFA_FCCOB7_CCOBn_SHIFT 0
923 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
924 /* FCCOB6 Bit Fields */
925 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
926 #define FTFA_FCCOB6_CCOBn_SHIFT 0
927 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
928 /* FCCOB5 Bit Fields */
929 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
930 #define FTFA_FCCOB5_CCOBn_SHIFT 0
931 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
932 /* FCCOB4 Bit Fields */
933 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
934 #define FTFA_FCCOB4_CCOBn_SHIFT 0
935 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
936 /* FCCOBB Bit Fields */
937 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
938 #define FTFA_FCCOBB_CCOBn_SHIFT 0
939 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
940 /* FCCOBA Bit Fields */
941 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
942 #define FTFA_FCCOBA_CCOBn_SHIFT 0
943 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
944 /* FCCOB9 Bit Fields */
945 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
946 #define FTFA_FCCOB9_CCOBn_SHIFT 0
947 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
948 /* FCCOB8 Bit Fields */
949 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
950 #define FTFA_FCCOB8_CCOBn_SHIFT 0
951 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
952 /* FPROT3 Bit Fields */
953 #define FTFA_FPROT3_PROT_MASK 0xFFu
954 #define FTFA_FPROT3_PROT_SHIFT 0
955 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
956 /* FPROT2 Bit Fields */
957 #define FTFA_FPROT2_PROT_MASK 0xFFu
958 #define FTFA_FPROT2_PROT_SHIFT 0
959 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
960 /* FPROT1 Bit Fields */
961 #define FTFA_FPROT1_PROT_MASK 0xFFu
962 #define FTFA_FPROT1_PROT_SHIFT 0
963 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
964 /* FPROT0 Bit Fields */
965 #define FTFA_FPROT0_PROT_MASK 0xFFu
966 #define FTFA_FPROT0_PROT_SHIFT 0
967 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
968
969 /**
970 * @}
971 */ /* end of group FTFA_Register_Masks */
972
973
974 /* FTFA - Peripheral instance base addresses */
975 /** Peripheral FTFA base address */
976 #define FTFA_BASE (0x40020000u)
977 /** Peripheral FTFA base pointer */
978 #define FTFA ((FTFA_Type *)FTFA_BASE)
979 /** Array initializer of FTFA peripheral base pointers */
980 #define FTFA_BASES { FTFA }
981
982 /**
983 * @}
984 */ /* end of group FTFA_Peripheral_Access_Layer */
985
986
987 /* ----------------------------------------------------------------------------
988 -- GPIO Peripheral Access Layer
989 ---------------------------------------------------------------------------- */
990
991 /**
992 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
993 * @{
994 */
995
996 /** GPIO - Register Layout Typedef */
997 typedef struct {
998 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
999 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
1000 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
1001 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
1002 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
1003 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
1004 } GPIO_Type;
1005
1006 /* ----------------------------------------------------------------------------
1007 -- GPIO Register Masks
1008 ---------------------------------------------------------------------------- */
1009
1010 /**
1011 * @addtogroup GPIO_Register_Masks GPIO Register Masks
1012 * @{
1013 */
1014
1015 /* PDOR Bit Fields */
1016 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
1017 #define GPIO_PDOR_PDO_SHIFT 0
1018 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
1019 /* PSOR Bit Fields */
1020 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
1021 #define GPIO_PSOR_PTSO_SHIFT 0
1022 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
1023 /* PCOR Bit Fields */
1024 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
1025 #define GPIO_PCOR_PTCO_SHIFT 0
1026 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
1027 /* PTOR Bit Fields */
1028 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
1029 #define GPIO_PTOR_PTTO_SHIFT 0
1030 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
1031 /* PDIR Bit Fields */
1032 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
1033 #define GPIO_PDIR_PDI_SHIFT 0
1034 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
1035 /* PDDR Bit Fields */
1036 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
1037 #define GPIO_PDDR_PDD_SHIFT 0
1038 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
1039
1040 /**
1041 * @}
1042 */ /* end of group GPIO_Register_Masks */
1043
1044
1045 /* GPIO - Peripheral instance base addresses */
1046 /** Peripheral PTA base address */
1047 #define PTA_BASE (0x400FF000u)
1048 /** Peripheral PTA base pointer */
1049 #define PTA ((GPIO_Type *)PTA_BASE)
1050 /** Peripheral PTB base address */
1051 #define PTB_BASE (0x400FF040u)
1052 /** Peripheral PTB base pointer */
1053 #define PTB ((GPIO_Type *)PTB_BASE)
1054 /** Peripheral PTC base address */
1055 #define PTC_BASE (0x400FF080u)
1056 /** Peripheral PTC base pointer */
1057 #define PTC ((GPIO_Type *)PTC_BASE)
1058 /** Peripheral PTD base address */
1059 #define PTD_BASE (0x400FF0C0u)
1060 /** Peripheral PTD base pointer */
1061 #define PTD ((GPIO_Type *)PTD_BASE)
1062 /** Peripheral PTE base address */
1063 #define PTE_BASE (0x400FF100u)
1064 /** Peripheral PTE base pointer */
1065 #define PTE ((GPIO_Type *)PTE_BASE)
1066 /** Array initializer of GPIO peripheral base pointers */
1067 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
1068
1069 /**
1070 * @}
1071 */ /* end of group GPIO_Peripheral_Access_Layer */
1072
1073
1074 /* ----------------------------------------------------------------------------
1075 -- I2C Peripheral Access Layer
1076 ---------------------------------------------------------------------------- */
1077
1078 /**
1079 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
1080 * @{
1081 */
1082
1083 /** I2C - Register Layout Typedef */
1084 typedef struct {
1085 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
1086 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
1087 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
1088 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
1089 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
1090 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
1091 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
1092 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
1093 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
1094 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
1095 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
1096 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
1097 } I2C_Type;
1098
1099 /* ----------------------------------------------------------------------------
1100 -- I2C Register Masks
1101 ---------------------------------------------------------------------------- */
1102
1103 /**
1104 * @addtogroup I2C_Register_Masks I2C Register Masks
1105 * @{
1106 */
1107
1108 /* A1 Bit Fields */
1109 #define I2C_A1_AD_MASK 0xFEu
1110 #define I2C_A1_AD_SHIFT 1
1111 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
1112 /* F Bit Fields */
1113 #define I2C_F_ICR_MASK 0x3Fu
1114 #define I2C_F_ICR_SHIFT 0
1115 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
1116 #define I2C_F_MULT_MASK 0xC0u
1117 #define I2C_F_MULT_SHIFT 6
1118 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
1119 /* C1 Bit Fields */
1120 #define I2C_C1_DMAEN_MASK 0x1u
1121 #define I2C_C1_DMAEN_SHIFT 0
1122 #define I2C_C1_WUEN_MASK 0x2u
1123 #define I2C_C1_WUEN_SHIFT 1
1124 #define I2C_C1_RSTA_MASK 0x4u
1125 #define I2C_C1_RSTA_SHIFT 2
1126 #define I2C_C1_TXAK_MASK 0x8u
1127 #define I2C_C1_TXAK_SHIFT 3
1128 #define I2C_C1_TX_MASK 0x10u
1129 #define I2C_C1_TX_SHIFT 4
1130 #define I2C_C1_MST_MASK 0x20u
1131 #define I2C_C1_MST_SHIFT 5
1132 #define I2C_C1_IICIE_MASK 0x40u
1133 #define I2C_C1_IICIE_SHIFT 6
1134 #define I2C_C1_IICEN_MASK 0x80u
1135 #define I2C_C1_IICEN_SHIFT 7
1136 /* S Bit Fields */
1137 #define I2C_S_RXAK_MASK 0x1u
1138 #define I2C_S_RXAK_SHIFT 0
1139 #define I2C_S_IICIF_MASK 0x2u
1140 #define I2C_S_IICIF_SHIFT 1
1141 #define I2C_S_SRW_MASK 0x4u
1142 #define I2C_S_SRW_SHIFT 2
1143 #define I2C_S_RAM_MASK 0x8u
1144 #define I2C_S_RAM_SHIFT 3
1145 #define I2C_S_ARBL_MASK 0x10u
1146 #define I2C_S_ARBL_SHIFT 4
1147 #define I2C_S_BUSY_MASK 0x20u
1148 #define I2C_S_BUSY_SHIFT 5
1149 #define I2C_S_IAAS_MASK 0x40u
1150 #define I2C_S_IAAS_SHIFT 6
1151 #define I2C_S_TCF_MASK 0x80u
1152 #define I2C_S_TCF_SHIFT 7
1153 /* D Bit Fields */
1154 #define I2C_D_DATA_MASK 0xFFu
1155 #define I2C_D_DATA_SHIFT 0
1156 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
1157 /* C2 Bit Fields */
1158 #define I2C_C2_AD_MASK 0x7u
1159 #define I2C_C2_AD_SHIFT 0
1160 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
1161 #define I2C_C2_RMEN_MASK 0x8u
1162 #define I2C_C2_RMEN_SHIFT 3
1163 #define I2C_C2_SBRC_MASK 0x10u
1164 #define I2C_C2_SBRC_SHIFT 4
1165 #define I2C_C2_HDRS_MASK 0x20u
1166 #define I2C_C2_HDRS_SHIFT 5
1167 #define I2C_C2_ADEXT_MASK 0x40u
1168 #define I2C_C2_ADEXT_SHIFT 6
1169 #define I2C_C2_GCAEN_MASK 0x80u
1170 #define I2C_C2_GCAEN_SHIFT 7
1171 /* FLT Bit Fields */
1172 #define I2C_FLT_FLT_MASK 0x1Fu
1173 #define I2C_FLT_FLT_SHIFT 0
1174 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
1175 #define I2C_FLT_STOPIE_MASK 0x20u
1176 #define I2C_FLT_STOPIE_SHIFT 5
1177 #define I2C_FLT_STOPF_MASK 0x40u
1178 #define I2C_FLT_STOPF_SHIFT 6
1179 #define I2C_FLT_SHEN_MASK 0x80u
1180 #define I2C_FLT_SHEN_SHIFT 7
1181 /* RA Bit Fields */
1182 #define I2C_RA_RAD_MASK 0xFEu
1183 #define I2C_RA_RAD_SHIFT 1
1184 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
1185 /* SMB Bit Fields */
1186 #define I2C_SMB_SHTF2IE_MASK 0x1u
1187 #define I2C_SMB_SHTF2IE_SHIFT 0
1188 #define I2C_SMB_SHTF2_MASK 0x2u
1189 #define I2C_SMB_SHTF2_SHIFT 1
1190 #define I2C_SMB_SHTF1_MASK 0x4u
1191 #define I2C_SMB_SHTF1_SHIFT 2
1192 #define I2C_SMB_SLTF_MASK 0x8u
1193 #define I2C_SMB_SLTF_SHIFT 3
1194 #define I2C_SMB_TCKSEL_MASK 0x10u
1195 #define I2C_SMB_TCKSEL_SHIFT 4
1196 #define I2C_SMB_SIICAEN_MASK 0x20u
1197 #define I2C_SMB_SIICAEN_SHIFT 5
1198 #define I2C_SMB_ALERTEN_MASK 0x40u
1199 #define I2C_SMB_ALERTEN_SHIFT 6
1200 #define I2C_SMB_FACK_MASK 0x80u
1201 #define I2C_SMB_FACK_SHIFT 7
1202 /* A2 Bit Fields */
1203 #define I2C_A2_SAD_MASK 0xFEu
1204 #define I2C_A2_SAD_SHIFT 1
1205 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
1206 /* SLTH Bit Fields */
1207 #define I2C_SLTH_SSLT_MASK 0xFFu
1208 #define I2C_SLTH_SSLT_SHIFT 0
1209 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
1210 /* SLTL Bit Fields */
1211 #define I2C_SLTL_SSLT_MASK 0xFFu
1212 #define I2C_SLTL_SSLT_SHIFT 0
1213 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
1214
1215 /**
1216 * @}
1217 */ /* end of group I2C_Register_Masks */
1218
1219
1220 /* I2C - Peripheral instance base addresses */
1221 /** Peripheral I2C0 base address */
1222 #define I2C0_BASE (0x40066000u)
1223 /** Peripheral I2C0 base pointer */
1224 #define I2C0 ((I2C_Type *)I2C0_BASE)
1225 /** Peripheral I2C1 base address */
1226 #define I2C1_BASE (0x40067000u)
1227 /** Peripheral I2C1 base pointer */
1228 #define I2C1 ((I2C_Type *)I2C1_BASE)
1229 /** Array initializer of I2C peripheral base pointers */
1230 #define I2C_BASES { I2C0, I2C1 }
1231
1232 /**
1233 * @}
1234 */ /* end of group I2C_Peripheral_Access_Layer */
1235
1236
1237 /* ----------------------------------------------------------------------------
1238 -- LLWU Peripheral Access Layer
1239 ---------------------------------------------------------------------------- */
1240
1241 /**
1242 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
1243 * @{
1244 */
1245
1246 /** LLWU - Register Layout Typedef */
1247 typedef struct {
1248 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
1249 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
1250 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
1251 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
1252 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
1253 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
1254 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
1255 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
1256 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
1257 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
1258 } LLWU_Type;
1259
1260 /* ----------------------------------------------------------------------------
1261 -- LLWU Register Masks
1262 ---------------------------------------------------------------------------- */
1263
1264 /**
1265 * @addtogroup LLWU_Register_Masks LLWU Register Masks
1266 * @{
1267 */
1268
1269 /* PE1 Bit Fields */
1270 #define LLWU_PE1_WUPE0_MASK 0x3u
1271 #define LLWU_PE1_WUPE0_SHIFT 0
1272 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
1273 #define LLWU_PE1_WUPE1_MASK 0xCu
1274 #define LLWU_PE1_WUPE1_SHIFT 2
1275 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
1276 #define LLWU_PE1_WUPE2_MASK 0x30u
1277 #define LLWU_PE1_WUPE2_SHIFT 4
1278 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
1279 #define LLWU_PE1_WUPE3_MASK 0xC0u
1280 #define LLWU_PE1_WUPE3_SHIFT 6
1281 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
1282 /* PE2 Bit Fields */
1283 #define LLWU_PE2_WUPE4_MASK 0x3u
1284 #define LLWU_PE2_WUPE4_SHIFT 0
1285 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
1286 #define LLWU_PE2_WUPE5_MASK 0xCu
1287 #define LLWU_PE2_WUPE5_SHIFT 2
1288 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
1289 #define LLWU_PE2_WUPE6_MASK 0x30u
1290 #define LLWU_PE2_WUPE6_SHIFT 4
1291 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
1292 #define LLWU_PE2_WUPE7_MASK 0xC0u
1293 #define LLWU_PE2_WUPE7_SHIFT 6
1294 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
1295 /* PE3 Bit Fields */
1296 #define LLWU_PE3_WUPE8_MASK 0x3u
1297 #define LLWU_PE3_WUPE8_SHIFT 0
1298 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
1299 #define LLWU_PE3_WUPE9_MASK 0xCu
1300 #define LLWU_PE3_WUPE9_SHIFT 2
1301 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
1302 #define LLWU_PE3_WUPE10_MASK 0x30u
1303 #define LLWU_PE3_WUPE10_SHIFT 4
1304 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
1305 #define LLWU_PE3_WUPE11_MASK 0xC0u
1306 #define LLWU_PE3_WUPE11_SHIFT 6
1307 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
1308 /* PE4 Bit Fields */
1309 #define LLWU_PE4_WUPE12_MASK 0x3u
1310 #define LLWU_PE4_WUPE12_SHIFT 0
1311 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
1312 #define LLWU_PE4_WUPE13_MASK 0xCu
1313 #define LLWU_PE4_WUPE13_SHIFT 2
1314 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
1315 #define LLWU_PE4_WUPE14_MASK 0x30u
1316 #define LLWU_PE4_WUPE14_SHIFT 4
1317 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
1318 #define LLWU_PE4_WUPE15_MASK 0xC0u
1319 #define LLWU_PE4_WUPE15_SHIFT 6
1320 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
1321 /* ME Bit Fields */
1322 #define LLWU_ME_WUME0_MASK 0x1u
1323 #define LLWU_ME_WUME0_SHIFT 0
1324 #define LLWU_ME_WUME1_MASK 0x2u
1325 #define LLWU_ME_WUME1_SHIFT 1
1326 #define LLWU_ME_WUME2_MASK 0x4u
1327 #define LLWU_ME_WUME2_SHIFT 2
1328 #define LLWU_ME_WUME3_MASK 0x8u
1329 #define LLWU_ME_WUME3_SHIFT 3
1330 #define LLWU_ME_WUME4_MASK 0x10u
1331 #define LLWU_ME_WUME4_SHIFT 4
1332 #define LLWU_ME_WUME5_MASK 0x20u
1333 #define LLWU_ME_WUME5_SHIFT 5
1334 #define LLWU_ME_WUME6_MASK 0x40u
1335 #define LLWU_ME_WUME6_SHIFT 6
1336 #define LLWU_ME_WUME7_MASK 0x80u
1337 #define LLWU_ME_WUME7_SHIFT 7
1338 /* F1 Bit Fields */
1339 #define LLWU_F1_WUF0_MASK 0x1u
1340 #define LLWU_F1_WUF0_SHIFT 0
1341 #define LLWU_F1_WUF1_MASK 0x2u
1342 #define LLWU_F1_WUF1_SHIFT 1
1343 #define LLWU_F1_WUF2_MASK 0x4u
1344 #define LLWU_F1_WUF2_SHIFT 2
1345 #define LLWU_F1_WUF3_MASK 0x8u
1346 #define LLWU_F1_WUF3_SHIFT 3
1347 #define LLWU_F1_WUF4_MASK 0x10u
1348 #define LLWU_F1_WUF4_SHIFT 4
1349 #define LLWU_F1_WUF5_MASK 0x20u
1350 #define LLWU_F1_WUF5_SHIFT 5
1351 #define LLWU_F1_WUF6_MASK 0x40u
1352 #define LLWU_F1_WUF6_SHIFT 6
1353 #define LLWU_F1_WUF7_MASK 0x80u
1354 #define LLWU_F1_WUF7_SHIFT 7
1355 /* F2 Bit Fields */
1356 #define LLWU_F2_WUF8_MASK 0x1u
1357 #define LLWU_F2_WUF8_SHIFT 0
1358 #define LLWU_F2_WUF9_MASK 0x2u
1359 #define LLWU_F2_WUF9_SHIFT 1
1360 #define LLWU_F2_WUF10_MASK 0x4u
1361 #define LLWU_F2_WUF10_SHIFT 2
1362 #define LLWU_F2_WUF11_MASK 0x8u
1363 #define LLWU_F2_WUF11_SHIFT 3
1364 #define LLWU_F2_WUF12_MASK 0x10u
1365 #define LLWU_F2_WUF12_SHIFT 4
1366 #define LLWU_F2_WUF13_MASK 0x20u
1367 #define LLWU_F2_WUF13_SHIFT 5
1368 #define LLWU_F2_WUF14_MASK 0x40u
1369 #define LLWU_F2_WUF14_SHIFT 6
1370 #define LLWU_F2_WUF15_MASK 0x80u
1371 #define LLWU_F2_WUF15_SHIFT 7
1372 /* F3 Bit Fields */
1373 #define LLWU_F3_MWUF0_MASK 0x1u
1374 #define LLWU_F3_MWUF0_SHIFT 0
1375 #define LLWU_F3_MWUF1_MASK 0x2u
1376 #define LLWU_F3_MWUF1_SHIFT 1
1377 #define LLWU_F3_MWUF2_MASK 0x4u
1378 #define LLWU_F3_MWUF2_SHIFT 2
1379 #define LLWU_F3_MWUF3_MASK 0x8u
1380 #define LLWU_F3_MWUF3_SHIFT 3
1381 #define LLWU_F3_MWUF4_MASK 0x10u
1382 #define LLWU_F3_MWUF4_SHIFT 4
1383 #define LLWU_F3_MWUF5_MASK 0x20u
1384 #define LLWU_F3_MWUF5_SHIFT 5
1385 #define LLWU_F3_MWUF6_MASK 0x40u
1386 #define LLWU_F3_MWUF6_SHIFT 6
1387 #define LLWU_F3_MWUF7_MASK 0x80u
1388 #define LLWU_F3_MWUF7_SHIFT 7
1389 /* FILT1 Bit Fields */
1390 #define LLWU_FILT1_FILTSEL_MASK 0xFu
1391 #define LLWU_FILT1_FILTSEL_SHIFT 0
1392 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
1393 #define LLWU_FILT1_FILTE_MASK 0x60u
1394 #define LLWU_FILT1_FILTE_SHIFT 5
1395 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
1396 #define LLWU_FILT1_FILTF_MASK 0x80u
1397 #define LLWU_FILT1_FILTF_SHIFT 7
1398 /* FILT2 Bit Fields */
1399 #define LLWU_FILT2_FILTSEL_MASK 0xFu
1400 #define LLWU_FILT2_FILTSEL_SHIFT 0
1401 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
1402 #define LLWU_FILT2_FILTE_MASK 0x60u
1403 #define LLWU_FILT2_FILTE_SHIFT 5
1404 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
1405 #define LLWU_FILT2_FILTF_MASK 0x80u
1406 #define LLWU_FILT2_FILTF_SHIFT 7
1407
1408 /**
1409 * @}
1410 */ /* end of group LLWU_Register_Masks */
1411
1412
1413 /* LLWU - Peripheral instance base addresses */
1414 /** Peripheral LLWU base address */
1415 #define LLWU_BASE (0x4007C000u)
1416 /** Peripheral LLWU base pointer */
1417 #define LLWU ((LLWU_Type *)LLWU_BASE)
1418 /** Array initializer of LLWU peripheral base pointers */
1419 #define LLWU_BASES { LLWU }
1420
1421 /**
1422 * @}
1423 */ /* end of group LLWU_Peripheral_Access_Layer */
1424
1425
1426 /* ----------------------------------------------------------------------------
1427 -- LPTMR Peripheral Access Layer
1428 ---------------------------------------------------------------------------- */
1429
1430 /**
1431 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
1432 * @{
1433 */
1434
1435 /** LPTMR - Register Layout Typedef */
1436 typedef struct {
1437 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
1438 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
1439 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
1440 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
1441 } LPTMR_Type;
1442
1443 /* ----------------------------------------------------------------------------
1444 -- LPTMR Register Masks
1445 ---------------------------------------------------------------------------- */
1446
1447 /**
1448 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
1449 * @{
1450 */
1451
1452 /* CSR Bit Fields */
1453 #define LPTMR_CSR_TEN_MASK 0x1u
1454 #define LPTMR_CSR_TEN_SHIFT 0
1455 #define LPTMR_CSR_TMS_MASK 0x2u
1456 #define LPTMR_CSR_TMS_SHIFT 1
1457 #define LPTMR_CSR_TFC_MASK 0x4u
1458 #define LPTMR_CSR_TFC_SHIFT 2
1459 #define LPTMR_CSR_TPP_MASK 0x8u
1460 #define LPTMR_CSR_TPP_SHIFT 3
1461 #define LPTMR_CSR_TPS_MASK 0x30u
1462 #define LPTMR_CSR_TPS_SHIFT 4
1463 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
1464 #define LPTMR_CSR_TIE_MASK 0x40u
1465 #define LPTMR_CSR_TIE_SHIFT 6
1466 #define LPTMR_CSR_TCF_MASK 0x80u
1467 #define LPTMR_CSR_TCF_SHIFT 7
1468 /* PSR Bit Fields */
1469 #define LPTMR_PSR_PCS_MASK 0x3u
1470 #define LPTMR_PSR_PCS_SHIFT 0
1471 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
1472 #define LPTMR_PSR_PBYP_MASK 0x4u
1473 #define LPTMR_PSR_PBYP_SHIFT 2
1474 #define LPTMR_PSR_PRESCALE_MASK 0x78u
1475 #define LPTMR_PSR_PRESCALE_SHIFT 3
1476 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
1477 /* CMR Bit Fields */
1478 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
1479 #define LPTMR_CMR_COMPARE_SHIFT 0
1480 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
1481 /* CNR Bit Fields */
1482 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
1483 #define LPTMR_CNR_COUNTER_SHIFT 0
1484 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
1485
1486 /**
1487 * @}
1488 */ /* end of group LPTMR_Register_Masks */
1489
1490
1491 /* LPTMR - Peripheral instance base addresses */
1492 /** Peripheral LPTMR0 base address */
1493 #define LPTMR0_BASE (0x40040000u)
1494 /** Peripheral LPTMR0 base pointer */
1495 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
1496 /** Array initializer of LPTMR peripheral base pointers */
1497 #define LPTMR_BASES { LPTMR0 }
1498
1499 /**
1500 * @}
1501 */ /* end of group LPTMR_Peripheral_Access_Layer */
1502
1503
1504 /* ----------------------------------------------------------------------------
1505 -- MCG Peripheral Access Layer
1506 ---------------------------------------------------------------------------- */
1507
1508 /**
1509 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
1510 * @{
1511 */
1512
1513 /** MCG - Register Layout Typedef */
1514 typedef struct {
1515 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
1516 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
1517 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
1518 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
1519 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
1520 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
1521 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
1522 uint8_t RESERVED_0[1];
1523 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
1524 uint8_t RESERVED_1[1];
1525 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
1526 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
1527 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
1528 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
1529 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
1530 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
1531 } MCG_Type;
1532
1533 /* ----------------------------------------------------------------------------
1534 -- MCG Register Masks
1535 ---------------------------------------------------------------------------- */
1536
1537 /**
1538 * @addtogroup MCG_Register_Masks MCG Register Masks
1539 * @{
1540 */
1541
1542 /* C1 Bit Fields */
1543 #define MCG_C1_IREFSTEN_MASK 0x1u
1544 #define MCG_C1_IREFSTEN_SHIFT 0
1545 #define MCG_C1_IRCLKEN_MASK 0x2u
1546 #define MCG_C1_IRCLKEN_SHIFT 1
1547 #define MCG_C1_IREFS_MASK 0x4u
1548 #define MCG_C1_IREFS_SHIFT 2
1549 #define MCG_C1_FRDIV_MASK 0x38u
1550 #define MCG_C1_FRDIV_SHIFT 3
1551 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
1552 #define MCG_C1_CLKS_MASK 0xC0u
1553 #define MCG_C1_CLKS_SHIFT 6
1554 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
1555 /* C2 Bit Fields */
1556 #define MCG_C2_IRCS_MASK 0x1u
1557 #define MCG_C2_IRCS_SHIFT 0
1558 #define MCG_C2_LP_MASK 0x2u
1559 #define MCG_C2_LP_SHIFT 1
1560 #define MCG_C2_EREFS0_MASK 0x4u
1561 #define MCG_C2_EREFS0_SHIFT 2
1562 #define MCG_C2_HGO0_MASK 0x8u
1563 #define MCG_C2_HGO0_SHIFT 3
1564 #define MCG_C2_RANGE0_MASK 0x30u
1565 #define MCG_C2_RANGE0_SHIFT 4
1566 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
1567 #define MCG_C2_LOCRE0_MASK 0x80u
1568 #define MCG_C2_LOCRE0_SHIFT 7
1569 /* C3 Bit Fields */
1570 #define MCG_C3_SCTRIM_MASK 0xFFu
1571 #define MCG_C3_SCTRIM_SHIFT 0
1572 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
1573 /* C4 Bit Fields */
1574 #define MCG_C4_SCFTRIM_MASK 0x1u
1575 #define MCG_C4_SCFTRIM_SHIFT 0
1576 #define MCG_C4_FCTRIM_MASK 0x1Eu
1577 #define MCG_C4_FCTRIM_SHIFT 1
1578 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
1579 #define MCG_C4_DRST_DRS_MASK 0x60u
1580 #define MCG_C4_DRST_DRS_SHIFT 5
1581 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
1582 #define MCG_C4_DMX32_MASK 0x80u
1583 #define MCG_C4_DMX32_SHIFT 7
1584 /* C5 Bit Fields */
1585 #define MCG_C5_PRDIV0_MASK 0x1Fu
1586 #define MCG_C5_PRDIV0_SHIFT 0
1587 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
1588 #define MCG_C5_PLLSTEN0_MASK 0x20u
1589 #define MCG_C5_PLLSTEN0_SHIFT 5
1590 #define MCG_C5_PLLCLKEN0_MASK 0x40u
1591 #define MCG_C5_PLLCLKEN0_SHIFT 6
1592 /* C6 Bit Fields */
1593 #define MCG_C6_VDIV0_MASK 0x1Fu
1594 #define MCG_C6_VDIV0_SHIFT 0
1595 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
1596 #define MCG_C6_CME0_MASK 0x20u
1597 #define MCG_C6_CME0_SHIFT 5
1598 #define MCG_C6_PLLS_MASK 0x40u
1599 #define MCG_C6_PLLS_SHIFT 6
1600 #define MCG_C6_LOLIE0_MASK 0x80u
1601 #define MCG_C6_LOLIE0_SHIFT 7
1602 /* S Bit Fields */
1603 #define MCG_S_IRCST_MASK 0x1u
1604 #define MCG_S_IRCST_SHIFT 0
1605 #define MCG_S_OSCINIT0_MASK 0x2u
1606 #define MCG_S_OSCINIT0_SHIFT 1
1607 #define MCG_S_CLKST_MASK 0xCu
1608 #define MCG_S_CLKST_SHIFT 2
1609 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
1610 #define MCG_S_IREFST_MASK 0x10u
1611 #define MCG_S_IREFST_SHIFT 4
1612 #define MCG_S_PLLST_MASK 0x20u
1613 #define MCG_S_PLLST_SHIFT 5
1614 #define MCG_S_LOCK0_MASK 0x40u
1615 #define MCG_S_LOCK0_SHIFT 6
1616 #define MCG_S_LOLS_MASK 0x80u
1617 #define MCG_S_LOLS_SHIFT 7
1618 /* SC Bit Fields */
1619 #define MCG_SC_LOCS0_MASK 0x1u
1620 #define MCG_SC_LOCS0_SHIFT 0
1621 #define MCG_SC_FCRDIV_MASK 0xEu
1622 #define MCG_SC_FCRDIV_SHIFT 1
1623 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
1624 #define MCG_SC_FLTPRSRV_MASK 0x10u
1625 #define MCG_SC_FLTPRSRV_SHIFT 4
1626 #define MCG_SC_ATMF_MASK 0x20u
1627 #define MCG_SC_ATMF_SHIFT 5
1628 #define MCG_SC_ATMS_MASK 0x40u
1629 #define MCG_SC_ATMS_SHIFT 6
1630 #define MCG_SC_ATME_MASK 0x80u
1631 #define MCG_SC_ATME_SHIFT 7
1632 /* ATCVH Bit Fields */
1633 #define MCG_ATCVH_ATCVH_MASK 0xFFu
1634 #define MCG_ATCVH_ATCVH_SHIFT 0
1635 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
1636 /* ATCVL Bit Fields */
1637 #define MCG_ATCVL_ATCVL_MASK 0xFFu
1638 #define MCG_ATCVL_ATCVL_SHIFT 0
1639 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
1640 /* C8 Bit Fields */
1641 #define MCG_C8_LOLRE_MASK 0x40u
1642 #define MCG_C8_LOLRE_SHIFT 6
1643
1644 /**
1645 * @}
1646 */ /* end of group MCG_Register_Masks */
1647
1648
1649 /* MCG - Peripheral instance base addresses */
1650 /** Peripheral MCG base address */
1651 #define MCG_BASE (0x40064000u)
1652 /** Peripheral MCG base pointer */
1653 #define MCG ((MCG_Type *)MCG_BASE)
1654 /** Array initializer of MCG peripheral base pointers */
1655 #define MCG_BASES { MCG }
1656
1657 /**
1658 * @}
1659 */ /* end of group MCG_Peripheral_Access_Layer */
1660
1661
1662 /* ----------------------------------------------------------------------------
1663 -- MCM Peripheral Access Layer
1664 ---------------------------------------------------------------------------- */
1665
1666 /**
1667 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
1668 * @{
1669 */
1670
1671 /** MCM - Register Layout Typedef */
1672 typedef struct {
1673 uint8_t RESERVED_0[8];
1674 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
1675 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
1676 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
1677 uint8_t RESERVED_1[48];
1678 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
1679 } MCM_Type;
1680
1681 /* ----------------------------------------------------------------------------
1682 -- MCM Register Masks
1683 ---------------------------------------------------------------------------- */
1684
1685 /**
1686 * @addtogroup MCM_Register_Masks MCM Register Masks
1687 * @{
1688 */
1689
1690 /* PLASC Bit Fields */
1691 #define MCM_PLASC_ASC_MASK 0xFFu
1692 #define MCM_PLASC_ASC_SHIFT 0
1693 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
1694 /* PLAMC Bit Fields */
1695 #define MCM_PLAMC_AMC_MASK 0xFFu
1696 #define MCM_PLAMC_AMC_SHIFT 0
1697 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
1698 /* PLACR Bit Fields */
1699 #define MCM_PLACR_ARB_MASK 0x200u
1700 #define MCM_PLACR_ARB_SHIFT 9
1701 #define MCM_PLACR_CFCC_MASK 0x400u
1702 #define MCM_PLACR_CFCC_SHIFT 10
1703 #define MCM_PLACR_DFCDA_MASK 0x800u
1704 #define MCM_PLACR_DFCDA_SHIFT 11
1705 #define MCM_PLACR_DFCIC_MASK 0x1000u
1706 #define MCM_PLACR_DFCIC_SHIFT 12
1707 #define MCM_PLACR_DFCC_MASK 0x2000u
1708 #define MCM_PLACR_DFCC_SHIFT 13
1709 #define MCM_PLACR_EFDS_MASK 0x4000u
1710 #define MCM_PLACR_EFDS_SHIFT 14
1711 #define MCM_PLACR_DFCS_MASK 0x8000u
1712 #define MCM_PLACR_DFCS_SHIFT 15
1713 #define MCM_PLACR_ESFC_MASK 0x10000u
1714 #define MCM_PLACR_ESFC_SHIFT 16
1715 /* CPO Bit Fields */
1716 #define MCM_CPO_CPOREQ_MASK 0x1u
1717 #define MCM_CPO_CPOREQ_SHIFT 0
1718 #define MCM_CPO_CPOACK_MASK 0x2u
1719 #define MCM_CPO_CPOACK_SHIFT 1
1720 #define MCM_CPO_CPOWOI_MASK 0x4u
1721 #define MCM_CPO_CPOWOI_SHIFT 2
1722
1723 /**
1724 * @}
1725 */ /* end of group MCM_Register_Masks */
1726
1727
1728 /* MCM - Peripheral instance base addresses */
1729 /** Peripheral MCM base address */
1730 #define MCM_BASE (0xF0003000u)
1731 /** Peripheral MCM base pointer */
1732 #define MCM ((MCM_Type *)MCM_BASE)
1733 /** Array initializer of MCM peripheral base pointers */
1734 #define MCM_BASES { MCM }
1735
1736 /**
1737 * @}
1738 */ /* end of group MCM_Peripheral_Access_Layer */
1739
1740
1741 /* ----------------------------------------------------------------------------
1742 -- MTB Peripheral Access Layer
1743 ---------------------------------------------------------------------------- */
1744
1745 /**
1746 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
1747 * @{
1748 */
1749
1750 /** MTB - Register Layout Typedef */
1751 typedef struct {
1752 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
1753 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
1754 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
1755 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
1756 uint8_t RESERVED_0[3824];
1757 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
1758 uint8_t RESERVED_1[156];
1759 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
1760 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
1761 uint8_t RESERVED_2[8];
1762 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
1763 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
1764 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
1765 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
1766 uint8_t RESERVED_3[8];
1767 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
1768 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
1769 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
1770 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
1771 } MTB_Type;
1772
1773 /* ----------------------------------------------------------------------------
1774 -- MTB Register Masks
1775 ---------------------------------------------------------------------------- */
1776
1777 /**
1778 * @addtogroup MTB_Register_Masks MTB Register Masks
1779 * @{
1780 */
1781
1782 /* POSITION Bit Fields */
1783 #define MTB_POSITION_WRAP_MASK 0x4u
1784 #define MTB_POSITION_WRAP_SHIFT 2
1785 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
1786 #define MTB_POSITION_POINTER_SHIFT 3
1787 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
1788 /* MASTER Bit Fields */
1789 #define MTB_MASTER_MASK_MASK 0x1Fu
1790 #define MTB_MASTER_MASK_SHIFT 0
1791 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
1792 #define MTB_MASTER_TSTARTEN_MASK 0x20u
1793 #define MTB_MASTER_TSTARTEN_SHIFT 5
1794 #define MTB_MASTER_TSTOPEN_MASK 0x40u
1795 #define MTB_MASTER_TSTOPEN_SHIFT 6
1796 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
1797 #define MTB_MASTER_SFRWPRIV_SHIFT 7
1798 #define MTB_MASTER_RAMPRIV_MASK 0x100u
1799 #define MTB_MASTER_RAMPRIV_SHIFT 8
1800 #define MTB_MASTER_HALTREQ_MASK 0x200u
1801 #define MTB_MASTER_HALTREQ_SHIFT 9
1802 #define MTB_MASTER_EN_MASK 0x80000000u
1803 #define MTB_MASTER_EN_SHIFT 31
1804 /* FLOW Bit Fields */
1805 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
1806 #define MTB_FLOW_AUTOSTOP_SHIFT 0
1807 #define MTB_FLOW_AUTOHALT_MASK 0x2u
1808 #define MTB_FLOW_AUTOHALT_SHIFT 1
1809 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
1810 #define MTB_FLOW_WATERMARK_SHIFT 3
1811 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
1812 /* BASE Bit Fields */
1813 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
1814 #define MTB_BASE_BASEADDR_SHIFT 0
1815 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
1816 /* MODECTRL Bit Fields */
1817 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
1818 #define MTB_MODECTRL_MODECTRL_SHIFT 0
1819 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
1820 /* TAGSET Bit Fields */
1821 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
1822 #define MTB_TAGSET_TAGSET_SHIFT 0
1823 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
1824 /* TAGCLEAR Bit Fields */
1825 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
1826 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
1827 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
1828 /* LOCKACCESS Bit Fields */
1829 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
1830 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
1831 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
1832 /* LOCKSTAT Bit Fields */
1833 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
1834 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
1835 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
1836 /* AUTHSTAT Bit Fields */
1837 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
1838 #define MTB_AUTHSTAT_BIT0_SHIFT 0
1839 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
1840 #define MTB_AUTHSTAT_BIT1_SHIFT 1
1841 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
1842 #define MTB_AUTHSTAT_BIT2_SHIFT 2
1843 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
1844 #define MTB_AUTHSTAT_BIT3_SHIFT 3
1845 /* DEVICEARCH Bit Fields */
1846 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
1847 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
1848 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
1849 /* DEVICECFG Bit Fields */
1850 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
1851 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
1852 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
1853 /* DEVICETYPID Bit Fields */
1854 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
1855 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
1856 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
1857 /* PERIPHID Bit Fields */
1858 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
1859 #define MTB_PERIPHID_PERIPHID_SHIFT 0
1860 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
1861 /* COMPID Bit Fields */
1862 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
1863 #define MTB_COMPID_COMPID_SHIFT 0
1864 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
1865
1866 /**
1867 * @}
1868 */ /* end of group MTB_Register_Masks */
1869
1870
1871 /* MTB - Peripheral instance base addresses */
1872 /** Peripheral MTB base address */
1873 #define MTB_BASE (0xF0000000u)
1874 /** Peripheral MTB base pointer */
1875 #define MTB ((MTB_Type *)MTB_BASE)
1876 /** Array initializer of MTB peripheral base pointers */
1877 #define MTB_BASES { MTB }
1878
1879 /**
1880 * @}
1881 */ /* end of group MTB_Peripheral_Access_Layer */
1882
1883
1884 /* ----------------------------------------------------------------------------
1885 -- MTBDWT Peripheral Access Layer
1886 ---------------------------------------------------------------------------- */
1887
1888 /**
1889 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
1890 * @{
1891 */
1892
1893 /** MTBDWT - Register Layout Typedef */
1894 typedef struct {
1895 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
1896 uint8_t RESERVED_0[28];
1897 struct { /* offset: 0x20, array step: 0x10 */
1898 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
1899 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
1900 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
1901 uint8_t RESERVED_0[4];
1902 } COMPARATOR[2];
1903 uint8_t RESERVED_1[448];
1904 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
1905 uint8_t RESERVED_2[3524];
1906 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
1907 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
1908 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
1909 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
1910 } MTBDWT_Type;
1911
1912 /* ----------------------------------------------------------------------------
1913 -- MTBDWT Register Masks
1914 ---------------------------------------------------------------------------- */
1915
1916 /**
1917 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
1918 * @{
1919 */
1920
1921 /* CTRL Bit Fields */
1922 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
1923 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
1924 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
1925 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
1926 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
1927 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
1928 /* COMP Bit Fields */
1929 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
1930 #define MTBDWT_COMP_COMP_SHIFT 0
1931 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
1932 /* MASK Bit Fields */
1933 #define MTBDWT_MASK_MASK_MASK 0x1Fu
1934 #define MTBDWT_MASK_MASK_SHIFT 0
1935 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
1936 /* FCT Bit Fields */
1937 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
1938 #define MTBDWT_FCT_FUNCTION_SHIFT 0
1939 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
1940 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
1941 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
1942 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
1943 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
1944 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
1945 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
1946 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
1947 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
1948 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
1949 #define MTBDWT_FCT_MATCHED_SHIFT 24
1950 /* TBCTRL Bit Fields */
1951 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
1952 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
1953 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
1954 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
1955 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
1956 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
1957 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
1958 /* DEVICECFG Bit Fields */
1959 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
1960 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
1961 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
1962 /* DEVICETYPID Bit Fields */
1963 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
1964 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
1965 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
1966 /* PERIPHID Bit Fields */
1967 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
1968 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
1969 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
1970 /* COMPID Bit Fields */
1971 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
1972 #define MTBDWT_COMPID_COMPID_SHIFT 0
1973 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
1974
1975 /**
1976 * @}
1977 */ /* end of group MTBDWT_Register_Masks */
1978
1979
1980 /* MTBDWT - Peripheral instance base addresses */
1981 /** Peripheral MTBDWT base address */
1982 #define MTBDWT_BASE (0xF0001000u)
1983 /** Peripheral MTBDWT base pointer */
1984 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
1985 /** Array initializer of MTBDWT peripheral base pointers */
1986 #define MTBDWT_BASES { MTBDWT }
1987
1988 /**
1989 * @}
1990 */ /* end of group MTBDWT_Peripheral_Access_Layer */
1991
1992
1993 /* ----------------------------------------------------------------------------
1994 -- NV Peripheral Access Layer
1995 ---------------------------------------------------------------------------- */
1996
1997 /**
1998 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
1999 * @{
2000 */
2001
2002 /** NV - Register Layout Typedef */
2003 typedef struct {
2004 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
2005 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
2006 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
2007 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
2008 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
2009 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
2010 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
2011 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
2012 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
2013 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
2014 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
2015 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
2016 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
2017 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
2018 } NV_Type;
2019
2020 /* ----------------------------------------------------------------------------
2021 -- NV Register Masks
2022 ---------------------------------------------------------------------------- */
2023
2024 /**
2025 * @addtogroup NV_Register_Masks NV Register Masks
2026 * @{
2027 */
2028
2029 /* BACKKEY3 Bit Fields */
2030 #define NV_BACKKEY3_KEY_MASK 0xFFu
2031 #define NV_BACKKEY3_KEY_SHIFT 0
2032 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
2033 /* BACKKEY2 Bit Fields */
2034 #define NV_BACKKEY2_KEY_MASK 0xFFu
2035 #define NV_BACKKEY2_KEY_SHIFT 0
2036 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
2037 /* BACKKEY1 Bit Fields */
2038 #define NV_BACKKEY1_KEY_MASK 0xFFu
2039 #define NV_BACKKEY1_KEY_SHIFT 0
2040 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
2041 /* BACKKEY0 Bit Fields */
2042 #define NV_BACKKEY0_KEY_MASK 0xFFu
2043 #define NV_BACKKEY0_KEY_SHIFT 0
2044 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
2045 /* BACKKEY7 Bit Fields */
2046 #define NV_BACKKEY7_KEY_MASK 0xFFu
2047 #define NV_BACKKEY7_KEY_SHIFT 0
2048 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
2049 /* BACKKEY6 Bit Fields */
2050 #define NV_BACKKEY6_KEY_MASK 0xFFu
2051 #define NV_BACKKEY6_KEY_SHIFT 0
2052 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
2053 /* BACKKEY5 Bit Fields */
2054 #define NV_BACKKEY5_KEY_MASK 0xFFu
2055 #define NV_BACKKEY5_KEY_SHIFT 0
2056 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
2057 /* BACKKEY4 Bit Fields */
2058 #define NV_BACKKEY4_KEY_MASK 0xFFu
2059 #define NV_BACKKEY4_KEY_SHIFT 0
2060 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
2061 /* FPROT3 Bit Fields */
2062 #define NV_FPROT3_PROT_MASK 0xFFu
2063 #define NV_FPROT3_PROT_SHIFT 0
2064 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
2065 /* FPROT2 Bit Fields */
2066 #define NV_FPROT2_PROT_MASK 0xFFu
2067 #define NV_FPROT2_PROT_SHIFT 0
2068 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
2069 /* FPROT1 Bit Fields */
2070 #define NV_FPROT1_PROT_MASK 0xFFu
2071 #define NV_FPROT1_PROT_SHIFT 0
2072 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
2073 /* FPROT0 Bit Fields */
2074 #define NV_FPROT0_PROT_MASK 0xFFu
2075 #define NV_FPROT0_PROT_SHIFT 0
2076 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
2077 /* FSEC Bit Fields */
2078 #define NV_FSEC_SEC_MASK 0x3u
2079 #define NV_FSEC_SEC_SHIFT 0
2080 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
2081 #define NV_FSEC_FSLACC_MASK 0xCu
2082 #define NV_FSEC_FSLACC_SHIFT 2
2083 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
2084 #define NV_FSEC_MEEN_MASK 0x30u
2085 #define NV_FSEC_MEEN_SHIFT 4
2086 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
2087 #define NV_FSEC_KEYEN_MASK 0xC0u
2088 #define NV_FSEC_KEYEN_SHIFT 6
2089 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
2090 /* FOPT Bit Fields */
2091 #define NV_FOPT_LPBOOT0_MASK 0x1u
2092 #define NV_FOPT_LPBOOT0_SHIFT 0
2093 #define NV_FOPT_NMI_DIS_MASK 0x4u
2094 #define NV_FOPT_NMI_DIS_SHIFT 2
2095 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
2096 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
2097 #define NV_FOPT_LPBOOT1_MASK 0x10u
2098 #define NV_FOPT_LPBOOT1_SHIFT 4
2099 #define NV_FOPT_FAST_INIT_MASK 0x20u
2100 #define NV_FOPT_FAST_INIT_SHIFT 5
2101
2102 /**
2103 * @}
2104 */ /* end of group NV_Register_Masks */
2105
2106
2107 /* NV - Peripheral instance base addresses */
2108 /** Peripheral FTFA_FlashConfig base address */
2109 #define FTFA_FlashConfig_BASE (0x400u)
2110 /** Peripheral FTFA_FlashConfig base pointer */
2111 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
2112 /** Array initializer of NV peripheral base pointers */
2113 #define NV_BASES { FTFA_FlashConfig }
2114
2115 /**
2116 * @}
2117 */ /* end of group NV_Peripheral_Access_Layer */
2118
2119
2120 /* ----------------------------------------------------------------------------
2121 -- OSC Peripheral Access Layer
2122 ---------------------------------------------------------------------------- */
2123
2124 /**
2125 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
2126 * @{
2127 */
2128
2129 /** OSC - Register Layout Typedef */
2130 typedef struct {
2131 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
2132 } OSC_Type;
2133
2134 /* ----------------------------------------------------------------------------
2135 -- OSC Register Masks
2136 ---------------------------------------------------------------------------- */
2137
2138 /**
2139 * @addtogroup OSC_Register_Masks OSC Register Masks
2140 * @{
2141 */
2142
2143 /* CR Bit Fields */
2144 #define OSC_CR_SC16P_MASK 0x1u
2145 #define OSC_CR_SC16P_SHIFT 0
2146 #define OSC_CR_SC8P_MASK 0x2u
2147 #define OSC_CR_SC8P_SHIFT 1
2148 #define OSC_CR_SC4P_MASK 0x4u
2149 #define OSC_CR_SC4P_SHIFT 2
2150 #define OSC_CR_SC2P_MASK 0x8u
2151 #define OSC_CR_SC2P_SHIFT 3
2152 #define OSC_CR_EREFSTEN_MASK 0x20u
2153 #define OSC_CR_EREFSTEN_SHIFT 5
2154 #define OSC_CR_ERCLKEN_MASK 0x80u
2155 #define OSC_CR_ERCLKEN_SHIFT 7
2156
2157 /**
2158 * @}
2159 */ /* end of group OSC_Register_Masks */
2160
2161
2162 /* OSC - Peripheral instance base addresses */
2163 /** Peripheral OSC0 base address */
2164 #define OSC0_BASE (0x40065000u)
2165 /** Peripheral OSC0 base pointer */
2166 #define OSC0 ((OSC_Type *)OSC0_BASE)
2167 /** Array initializer of OSC peripheral base pointers */
2168 #define OSC_BASES { OSC0 }
2169
2170 /**
2171 * @}
2172 */ /* end of group OSC_Peripheral_Access_Layer */
2173
2174
2175 /* ----------------------------------------------------------------------------
2176 -- PIT Peripheral Access Layer
2177 ---------------------------------------------------------------------------- */
2178
2179 /**
2180 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
2181 * @{
2182 */
2183
2184 /** PIT - Register Layout Typedef */
2185 typedef struct {
2186 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
2187 uint8_t RESERVED_0[220];
2188 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
2189 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
2190 uint8_t RESERVED_1[24];
2191 struct { /* offset: 0x100, array step: 0x10 */
2192 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
2193 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
2194 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
2195 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
2196 } CHANNEL[2];
2197 } PIT_Type;
2198
2199 /* ----------------------------------------------------------------------------
2200 -- PIT Register Masks
2201 ---------------------------------------------------------------------------- */
2202
2203 /**
2204 * @addtogroup PIT_Register_Masks PIT Register Masks
2205 * @{
2206 */
2207
2208 /* MCR Bit Fields */
2209 #define PIT_MCR_FRZ_MASK 0x1u
2210 #define PIT_MCR_FRZ_SHIFT 0
2211 #define PIT_MCR_MDIS_MASK 0x2u
2212 #define PIT_MCR_MDIS_SHIFT 1
2213 /* LTMR64H Bit Fields */
2214 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
2215 #define PIT_LTMR64H_LTH_SHIFT 0
2216 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
2217 /* LTMR64L Bit Fields */
2218 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
2219 #define PIT_LTMR64L_LTL_SHIFT 0
2220 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
2221 /* LDVAL Bit Fields */
2222 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
2223 #define PIT_LDVAL_TSV_SHIFT 0
2224 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
2225 /* CVAL Bit Fields */
2226 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
2227 #define PIT_CVAL_TVL_SHIFT 0
2228 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
2229 /* TCTRL Bit Fields */
2230 #define PIT_TCTRL_TEN_MASK 0x1u
2231 #define PIT_TCTRL_TEN_SHIFT 0
2232 #define PIT_TCTRL_TIE_MASK 0x2u
2233 #define PIT_TCTRL_TIE_SHIFT 1
2234 #define PIT_TCTRL_CHN_MASK 0x4u
2235 #define PIT_TCTRL_CHN_SHIFT 2
2236 /* TFLG Bit Fields */
2237 #define PIT_TFLG_TIF_MASK 0x1u
2238 #define PIT_TFLG_TIF_SHIFT 0
2239
2240 /**
2241 * @}
2242 */ /* end of group PIT_Register_Masks */
2243
2244
2245 /* PIT - Peripheral instance base addresses */
2246 /** Peripheral PIT base address */
2247 #define PIT_BASE (0x40037000u)
2248 /** Peripheral PIT base pointer */
2249 #define PIT ((PIT_Type *)PIT_BASE)
2250 /** Array initializer of PIT peripheral base pointers */
2251 #define PIT_BASES { PIT }
2252
2253 /**
2254 * @}
2255 */ /* end of group PIT_Peripheral_Access_Layer */
2256
2257
2258 /* ----------------------------------------------------------------------------
2259 -- PMC Peripheral Access Layer
2260 ---------------------------------------------------------------------------- */
2261
2262 /**
2263 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
2264 * @{
2265 */
2266
2267 /** PMC - Register Layout Typedef */
2268 typedef struct {
2269 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
2270 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
2271 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
2272 } PMC_Type;
2273
2274 /* ----------------------------------------------------------------------------
2275 -- PMC Register Masks
2276 ---------------------------------------------------------------------------- */
2277
2278 /**
2279 * @addtogroup PMC_Register_Masks PMC Register Masks
2280 * @{
2281 */
2282
2283 /* LVDSC1 Bit Fields */
2284 #define PMC_LVDSC1_LVDV_MASK 0x3u
2285 #define PMC_LVDSC1_LVDV_SHIFT 0
2286 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
2287 #define PMC_LVDSC1_LVDRE_MASK 0x10u
2288 #define PMC_LVDSC1_LVDRE_SHIFT 4
2289 #define PMC_LVDSC1_LVDIE_MASK 0x20u
2290 #define PMC_LVDSC1_LVDIE_SHIFT 5
2291 #define PMC_LVDSC1_LVDACK_MASK 0x40u
2292 #define PMC_LVDSC1_LVDACK_SHIFT 6
2293 #define PMC_LVDSC1_LVDF_MASK 0x80u
2294 #define PMC_LVDSC1_LVDF_SHIFT 7
2295 /* LVDSC2 Bit Fields */
2296 #define PMC_LVDSC2_LVWV_MASK 0x3u
2297 #define PMC_LVDSC2_LVWV_SHIFT 0
2298 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
2299 #define PMC_LVDSC2_LVWIE_MASK 0x20u
2300 #define PMC_LVDSC2_LVWIE_SHIFT 5
2301 #define PMC_LVDSC2_LVWACK_MASK 0x40u
2302 #define PMC_LVDSC2_LVWACK_SHIFT 6
2303 #define PMC_LVDSC2_LVWF_MASK 0x80u
2304 #define PMC_LVDSC2_LVWF_SHIFT 7
2305 /* REGSC Bit Fields */
2306 #define PMC_REGSC_BGBE_MASK 0x1u
2307 #define PMC_REGSC_BGBE_SHIFT 0
2308 #define PMC_REGSC_REGONS_MASK 0x4u
2309 #define PMC_REGSC_REGONS_SHIFT 2
2310 #define PMC_REGSC_ACKISO_MASK 0x8u
2311 #define PMC_REGSC_ACKISO_SHIFT 3
2312 #define PMC_REGSC_BGEN_MASK 0x10u
2313 #define PMC_REGSC_BGEN_SHIFT 4
2314
2315 /**
2316 * @}
2317 */ /* end of group PMC_Register_Masks */
2318
2319
2320 /* PMC - Peripheral instance base addresses */
2321 /** Peripheral PMC base address */
2322 #define PMC_BASE (0x4007D000u)
2323 /** Peripheral PMC base pointer */
2324 #define PMC ((PMC_Type *)PMC_BASE)
2325 /** Array initializer of PMC peripheral base pointers */
2326 #define PMC_BASES { PMC }
2327
2328 /**
2329 * @}
2330 */ /* end of group PMC_Peripheral_Access_Layer */
2331
2332
2333 /* ----------------------------------------------------------------------------
2334 -- PORT Peripheral Access Layer
2335 ---------------------------------------------------------------------------- */
2336
2337 /**
2338 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
2339 * @{
2340 */
2341
2342 /** PORT - Register Layout Typedef */
2343 typedef struct {
2344 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
2345 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
2346 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
2347 uint8_t RESERVED_0[24];
2348 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
2349 } PORT_Type;
2350
2351 /* ----------------------------------------------------------------------------
2352 -- PORT Register Masks
2353 ---------------------------------------------------------------------------- */
2354
2355 /**
2356 * @addtogroup PORT_Register_Masks PORT Register Masks
2357 * @{
2358 */
2359
2360 /* PCR Bit Fields */
2361 #define PORT_PCR_PS_MASK 0x1u
2362 #define PORT_PCR_PS_SHIFT 0
2363 #define PORT_PCR_PE_MASK 0x2u
2364 #define PORT_PCR_PE_SHIFT 1
2365 #define PORT_PCR_SRE_MASK 0x4u
2366 #define PORT_PCR_SRE_SHIFT 2
2367 #define PORT_PCR_PFE_MASK 0x10u
2368 #define PORT_PCR_PFE_SHIFT 4
2369 #define PORT_PCR_DSE_MASK 0x40u
2370 #define PORT_PCR_DSE_SHIFT 6
2371 #define PORT_PCR_MUX_MASK 0x700u
2372 #define PORT_PCR_MUX_SHIFT 8
2373 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
2374 #define PORT_PCR_IRQC_MASK 0xF0000u
2375 #define PORT_PCR_IRQC_SHIFT 16
2376 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
2377 #define PORT_PCR_ISF_MASK 0x1000000u
2378 #define PORT_PCR_ISF_SHIFT 24
2379 /* GPCLR Bit Fields */
2380 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
2381 #define PORT_GPCLR_GPWD_SHIFT 0
2382 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
2383 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
2384 #define PORT_GPCLR_GPWE_SHIFT 16
2385 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
2386 /* GPCHR Bit Fields */
2387 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
2388 #define PORT_GPCHR_GPWD_SHIFT 0
2389 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
2390 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
2391 #define PORT_GPCHR_GPWE_SHIFT 16
2392 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
2393 /* ISFR Bit Fields */
2394 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
2395 #define PORT_ISFR_ISF_SHIFT 0
2396 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
2397
2398 /**
2399 * @}
2400 */ /* end of group PORT_Register_Masks */
2401
2402
2403 /* PORT - Peripheral instance base addresses */
2404 /** Peripheral PORTA base address */
2405 #define PORTA_BASE (0x40049000u)
2406 /** Peripheral PORTA base pointer */
2407 #define PORTA ((PORT_Type *)PORTA_BASE)
2408 /** Peripheral PORTB base address */
2409 #define PORTB_BASE (0x4004A000u)
2410 /** Peripheral PORTB base pointer */
2411 #define PORTB ((PORT_Type *)PORTB_BASE)
2412 /** Peripheral PORTC base address */
2413 #define PORTC_BASE (0x4004B000u)
2414 /** Peripheral PORTC base pointer */
2415 #define PORTC ((PORT_Type *)PORTC_BASE)
2416 /** Peripheral PORTD base address */
2417 #define PORTD_BASE (0x4004C000u)
2418 /** Peripheral PORTD base pointer */
2419 #define PORTD ((PORT_Type *)PORTD_BASE)
2420 /** Peripheral PORTE base address */
2421 #define PORTE_BASE (0x4004D000u)
2422 /** Peripheral PORTE base pointer */
2423 #define PORTE ((PORT_Type *)PORTE_BASE)
2424 /** Array initializer of PORT peripheral base pointers */
2425 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
2426
2427 /**
2428 * @}
2429 */ /* end of group PORT_Peripheral_Access_Layer */
2430
2431
2432 /* ----------------------------------------------------------------------------
2433 -- RCM Peripheral Access Layer
2434 ---------------------------------------------------------------------------- */
2435
2436 /**
2437 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
2438 * @{
2439 */
2440
2441 /** RCM - Register Layout Typedef */
2442 typedef struct {
2443 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
2444 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
2445 uint8_t RESERVED_0[2];
2446 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
2447 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
2448 } RCM_Type;
2449
2450 /* ----------------------------------------------------------------------------
2451 -- RCM Register Masks
2452 ---------------------------------------------------------------------------- */
2453
2454 /**
2455 * @addtogroup RCM_Register_Masks RCM Register Masks
2456 * @{
2457 */
2458
2459 /* SRS0 Bit Fields */
2460 #define RCM_SRS0_WAKEUP_MASK 0x1u
2461 #define RCM_SRS0_WAKEUP_SHIFT 0
2462 #define RCM_SRS0_LVD_MASK 0x2u
2463 #define RCM_SRS0_LVD_SHIFT 1
2464 #define RCM_SRS0_LOC_MASK 0x4u
2465 #define RCM_SRS0_LOC_SHIFT 2
2466 #define RCM_SRS0_LOL_MASK 0x8u
2467 #define RCM_SRS0_LOL_SHIFT 3
2468 #define RCM_SRS0_WDOG_MASK 0x20u
2469 #define RCM_SRS0_WDOG_SHIFT 5
2470 #define RCM_SRS0_PIN_MASK 0x40u
2471 #define RCM_SRS0_PIN_SHIFT 6
2472 #define RCM_SRS0_POR_MASK 0x80u
2473 #define RCM_SRS0_POR_SHIFT 7
2474 /* SRS1 Bit Fields */
2475 #define RCM_SRS1_LOCKUP_MASK 0x2u
2476 #define RCM_SRS1_LOCKUP_SHIFT 1
2477 #define RCM_SRS1_SW_MASK 0x4u
2478 #define RCM_SRS1_SW_SHIFT 2
2479 #define RCM_SRS1_MDM_AP_MASK 0x8u
2480 #define RCM_SRS1_MDM_AP_SHIFT 3
2481 #define RCM_SRS1_SACKERR_MASK 0x20u
2482 #define RCM_SRS1_SACKERR_SHIFT 5
2483 /* RPFC Bit Fields */
2484 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
2485 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
2486 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
2487 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
2488 #define RCM_RPFC_RSTFLTSS_SHIFT 2
2489 /* RPFW Bit Fields */
2490 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
2491 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
2492 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
2493
2494 /**
2495 * @}
2496 */ /* end of group RCM_Register_Masks */
2497
2498
2499 /* RCM - Peripheral instance base addresses */
2500 /** Peripheral RCM base address */
2501 #define RCM_BASE (0x4007F000u)
2502 /** Peripheral RCM base pointer */
2503 #define RCM ((RCM_Type *)RCM_BASE)
2504 /** Array initializer of RCM peripheral base pointers */
2505 #define RCM_BASES { RCM }
2506
2507 /**
2508 * @}
2509 */ /* end of group RCM_Peripheral_Access_Layer */
2510
2511
2512 /* ----------------------------------------------------------------------------
2513 -- ROM Peripheral Access Layer
2514 ---------------------------------------------------------------------------- */
2515
2516 /**
2517 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
2518 * @{
2519 */
2520
2521 /** ROM - Register Layout Typedef */
2522 typedef struct {
2523 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
2524 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
2525 uint8_t RESERVED_0[4028];
2526 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
2527 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
2528 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
2529 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
2530 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
2531 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
2532 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
2533 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
2534 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
2535 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
2536 } ROM_Type;
2537
2538 /* ----------------------------------------------------------------------------
2539 -- ROM Register Masks
2540 ---------------------------------------------------------------------------- */
2541
2542 /**
2543 * @addtogroup ROM_Register_Masks ROM Register Masks
2544 * @{
2545 */
2546
2547 /* ENTRY Bit Fields */
2548 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
2549 #define ROM_ENTRY_ENTRY_SHIFT 0
2550 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
2551 /* TABLEMARK Bit Fields */
2552 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
2553 #define ROM_TABLEMARK_MARK_SHIFT 0
2554 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
2555 /* SYSACCESS Bit Fields */
2556 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
2557 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
2558 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
2559 /* PERIPHID4 Bit Fields */
2560 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
2561 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
2562 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
2563 /* PERIPHID5 Bit Fields */
2564 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
2565 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
2566 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
2567 /* PERIPHID6 Bit Fields */
2568 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
2569 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
2570 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
2571 /* PERIPHID7 Bit Fields */
2572 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
2573 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
2574 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
2575 /* PERIPHID0 Bit Fields */
2576 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
2577 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
2578 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
2579 /* PERIPHID1 Bit Fields */
2580 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
2581 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
2582 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
2583 /* PERIPHID2 Bit Fields */
2584 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
2585 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
2586 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
2587 /* PERIPHID3 Bit Fields */
2588 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
2589 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
2590 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
2591 /* COMPID Bit Fields */
2592 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
2593 #define ROM_COMPID_COMPID_SHIFT 0
2594 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
2595
2596 /**
2597 * @}
2598 */ /* end of group ROM_Register_Masks */
2599
2600
2601 /* ROM - Peripheral instance base addresses */
2602 /** Peripheral ROM base address */
2603 #define ROM_BASE (0xF0002000u)
2604 /** Peripheral ROM base pointer */
2605 #define ROM ((ROM_Type *)ROM_BASE)
2606 /** Array initializer of ROM peripheral base pointers */
2607 #define ROM_BASES { ROM }
2608
2609 /**
2610 * @}
2611 */ /* end of group ROM_Peripheral_Access_Layer */
2612
2613
2614 /* ----------------------------------------------------------------------------
2615 -- RTC Peripheral Access Layer
2616 ---------------------------------------------------------------------------- */
2617
2618 /**
2619 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
2620 * @{
2621 */
2622
2623 /** RTC - Register Layout Typedef */
2624 typedef struct {
2625 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
2626 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
2627 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
2628 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
2629 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
2630 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
2631 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
2632 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
2633 } RTC_Type;
2634
2635 /* ----------------------------------------------------------------------------
2636 -- RTC Register Masks
2637 ---------------------------------------------------------------------------- */
2638
2639 /**
2640 * @addtogroup RTC_Register_Masks RTC Register Masks
2641 * @{
2642 */
2643
2644 /* TSR Bit Fields */
2645 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
2646 #define RTC_TSR_TSR_SHIFT 0
2647 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
2648 /* TPR Bit Fields */
2649 #define RTC_TPR_TPR_MASK 0xFFFFu
2650 #define RTC_TPR_TPR_SHIFT 0
2651 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
2652 /* TAR Bit Fields */
2653 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
2654 #define RTC_TAR_TAR_SHIFT 0
2655 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
2656 /* TCR Bit Fields */
2657 #define RTC_TCR_TCR_MASK 0xFFu
2658 #define RTC_TCR_TCR_SHIFT 0
2659 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
2660 #define RTC_TCR_CIR_MASK 0xFF00u
2661 #define RTC_TCR_CIR_SHIFT 8
2662 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
2663 #define RTC_TCR_TCV_MASK 0xFF0000u
2664 #define RTC_TCR_TCV_SHIFT 16
2665 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
2666 #define RTC_TCR_CIC_MASK 0xFF000000u
2667 #define RTC_TCR_CIC_SHIFT 24
2668 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
2669 /* CR Bit Fields */
2670 #define RTC_CR_SWR_MASK 0x1u
2671 #define RTC_CR_SWR_SHIFT 0
2672 #define RTC_CR_WPE_MASK 0x2u
2673 #define RTC_CR_WPE_SHIFT 1
2674 #define RTC_CR_SUP_MASK 0x4u
2675 #define RTC_CR_SUP_SHIFT 2
2676 #define RTC_CR_UM_MASK 0x8u
2677 #define RTC_CR_UM_SHIFT 3
2678 #define RTC_CR_OSCE_MASK 0x100u
2679 #define RTC_CR_OSCE_SHIFT 8
2680 #define RTC_CR_CLKO_MASK 0x200u
2681 #define RTC_CR_CLKO_SHIFT 9
2682 #define RTC_CR_SC16P_MASK 0x400u
2683 #define RTC_CR_SC16P_SHIFT 10
2684 #define RTC_CR_SC8P_MASK 0x800u
2685 #define RTC_CR_SC8P_SHIFT 11
2686 #define RTC_CR_SC4P_MASK 0x1000u
2687 #define RTC_CR_SC4P_SHIFT 12
2688 #define RTC_CR_SC2P_MASK 0x2000u
2689 #define RTC_CR_SC2P_SHIFT 13
2690 /* SR Bit Fields */
2691 #define RTC_SR_TIF_MASK 0x1u
2692 #define RTC_SR_TIF_SHIFT 0
2693 #define RTC_SR_TOF_MASK 0x2u
2694 #define RTC_SR_TOF_SHIFT 1
2695 #define RTC_SR_TAF_MASK 0x4u
2696 #define RTC_SR_TAF_SHIFT 2
2697 #define RTC_SR_TCE_MASK 0x10u
2698 #define RTC_SR_TCE_SHIFT 4
2699 /* LR Bit Fields */
2700 #define RTC_LR_TCL_MASK 0x8u
2701 #define RTC_LR_TCL_SHIFT 3
2702 #define RTC_LR_CRL_MASK 0x10u
2703 #define RTC_LR_CRL_SHIFT 4
2704 #define RTC_LR_SRL_MASK 0x20u
2705 #define RTC_LR_SRL_SHIFT 5
2706 #define RTC_LR_LRL_MASK 0x40u
2707 #define RTC_LR_LRL_SHIFT 6
2708 /* IER Bit Fields */
2709 #define RTC_IER_TIIE_MASK 0x1u
2710 #define RTC_IER_TIIE_SHIFT 0
2711 #define RTC_IER_TOIE_MASK 0x2u
2712 #define RTC_IER_TOIE_SHIFT 1
2713 #define RTC_IER_TAIE_MASK 0x4u
2714 #define RTC_IER_TAIE_SHIFT 2
2715 #define RTC_IER_TSIE_MASK 0x10u
2716 #define RTC_IER_TSIE_SHIFT 4
2717 #define RTC_IER_WPON_MASK 0x80u
2718 #define RTC_IER_WPON_SHIFT 7
2719
2720 /**
2721 * @}
2722 */ /* end of group RTC_Register_Masks */
2723
2724
2725 /* RTC - Peripheral instance base addresses */
2726 /** Peripheral RTC base address */
2727 #define RTC_BASE (0x4003D000u)
2728 /** Peripheral RTC base pointer */
2729 #define RTC ((RTC_Type *)RTC_BASE)
2730 /** Array initializer of RTC peripheral base pointers */
2731 #define RTC_BASES { RTC }
2732
2733 /**
2734 * @}
2735 */ /* end of group RTC_Peripheral_Access_Layer */
2736
2737
2738 /* ----------------------------------------------------------------------------
2739 -- SIM Peripheral Access Layer
2740 ---------------------------------------------------------------------------- */
2741
2742 /**
2743 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
2744 * @{
2745 */
2746
2747 /** SIM - Register Layout Typedef */
2748 typedef struct {
2749 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
2750 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
2751 uint8_t RESERVED_0[4092];
2752 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
2753 uint8_t RESERVED_1[4];
2754 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
2755 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
2756 uint8_t RESERVED_2[4];
2757 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
2758 uint8_t RESERVED_3[8];
2759 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
2760 uint8_t RESERVED_4[12];
2761 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
2762 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
2763 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
2764 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
2765 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
2766 uint8_t RESERVED_5[4];
2767 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
2768 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
2769 uint8_t RESERVED_6[4];
2770 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
2771 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
2772 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
2773 uint8_t RESERVED_7[156];
2774 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
2775 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
2776 } SIM_Type;
2777
2778 /* ----------------------------------------------------------------------------
2779 -- SIM Register Masks
2780 ---------------------------------------------------------------------------- */
2781
2782 /**
2783 * @addtogroup SIM_Register_Masks SIM Register Masks
2784 * @{
2785 */
2786
2787 /* SOPT1 Bit Fields */
2788 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
2789 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
2790 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
2791 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
2792 #define SIM_SOPT1_USBVSTBY_SHIFT 29
2793 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
2794 #define SIM_SOPT1_USBSSTBY_SHIFT 30
2795 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
2796 #define SIM_SOPT1_USBREGEN_SHIFT 31
2797 /* SOPT1CFG Bit Fields */
2798 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
2799 #define SIM_SOPT1CFG_URWE_SHIFT 24
2800 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
2801 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
2802 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
2803 #define SIM_SOPT1CFG_USSWE_SHIFT 26
2804 /* SOPT2 Bit Fields */
2805 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
2806 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
2807 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
2808 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
2809 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
2810 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
2811 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
2812 #define SIM_SOPT2_USBSRC_MASK 0x40000u
2813 #define SIM_SOPT2_USBSRC_SHIFT 18
2814 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
2815 #define SIM_SOPT2_TPMSRC_SHIFT 24
2816 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
2817 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
2818 #define SIM_SOPT2_UART0SRC_SHIFT 26
2819 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
2820 /* SOPT4 Bit Fields */
2821 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
2822 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
2823 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
2824 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
2825 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
2826 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
2827 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
2828 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
2829 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
2830 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
2831 /* SOPT5 Bit Fields */
2832 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
2833 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
2834 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
2835 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
2836 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
2837 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
2838 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
2839 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
2840 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
2841 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
2842 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
2843 #define SIM_SOPT5_UART0ODE_SHIFT 16
2844 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
2845 #define SIM_SOPT5_UART1ODE_SHIFT 17
2846 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
2847 #define SIM_SOPT5_UART2ODE_SHIFT 18
2848 /* SOPT7 Bit Fields */
2849 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
2850 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
2851 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
2852 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
2853 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
2854 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
2855 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
2856 /* SDID Bit Fields */
2857 #define SIM_SDID_PINID_MASK 0xFu
2858 #define SIM_SDID_PINID_SHIFT 0
2859 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
2860 #define SIM_SDID_DIEID_MASK 0xF80u
2861 #define SIM_SDID_DIEID_SHIFT 7
2862 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
2863 #define SIM_SDID_REVID_MASK 0xF000u
2864 #define SIM_SDID_REVID_SHIFT 12
2865 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
2866 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
2867 #define SIM_SDID_SRAMSIZE_SHIFT 16
2868 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
2869 #define SIM_SDID_SERIESID_MASK 0xF00000u
2870 #define SIM_SDID_SERIESID_SHIFT 20
2871 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
2872 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
2873 #define SIM_SDID_SUBFAMID_SHIFT 24
2874 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
2875 #define SIM_SDID_FAMID_MASK 0xF0000000u
2876 #define SIM_SDID_FAMID_SHIFT 28
2877 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
2878 /* SCGC4 Bit Fields */
2879 #define SIM_SCGC4_I2C0_MASK 0x40u
2880 #define SIM_SCGC4_I2C0_SHIFT 6
2881 #define SIM_SCGC4_I2C1_MASK 0x80u
2882 #define SIM_SCGC4_I2C1_SHIFT 7
2883 #define SIM_SCGC4_UART0_MASK 0x400u
2884 #define SIM_SCGC4_UART0_SHIFT 10
2885 #define SIM_SCGC4_UART1_MASK 0x800u
2886 #define SIM_SCGC4_UART1_SHIFT 11
2887 #define SIM_SCGC4_UART2_MASK 0x1000u
2888 #define SIM_SCGC4_UART2_SHIFT 12
2889 #define SIM_SCGC4_USBOTG_MASK 0x40000u
2890 #define SIM_SCGC4_USBOTG_SHIFT 18
2891 #define SIM_SCGC4_CMP_MASK 0x80000u
2892 #define SIM_SCGC4_CMP_SHIFT 19
2893 #define SIM_SCGC4_SPI0_MASK 0x400000u
2894 #define SIM_SCGC4_SPI0_SHIFT 22
2895 #define SIM_SCGC4_SPI1_MASK 0x800000u
2896 #define SIM_SCGC4_SPI1_SHIFT 23
2897 /* SCGC5 Bit Fields */
2898 #define SIM_SCGC5_LPTMR_MASK 0x1u
2899 #define SIM_SCGC5_LPTMR_SHIFT 0
2900 #define SIM_SCGC5_TSI_MASK 0x20u
2901 #define SIM_SCGC5_TSI_SHIFT 5
2902 #define SIM_SCGC5_PORTA_MASK 0x200u
2903 #define SIM_SCGC5_PORTA_SHIFT 9
2904 #define SIM_SCGC5_PORTB_MASK 0x400u
2905 #define SIM_SCGC5_PORTB_SHIFT 10
2906 #define SIM_SCGC5_PORTC_MASK 0x800u
2907 #define SIM_SCGC5_PORTC_SHIFT 11
2908 #define SIM_SCGC5_PORTD_MASK 0x1000u
2909 #define SIM_SCGC5_PORTD_SHIFT 12
2910 #define SIM_SCGC5_PORTE_MASK 0x2000u
2911 #define SIM_SCGC5_PORTE_SHIFT 13
2912 /* SCGC6 Bit Fields */
2913 #define SIM_SCGC6_FTF_MASK 0x1u
2914 #define SIM_SCGC6_FTF_SHIFT 0
2915 #define SIM_SCGC6_DMAMUX_MASK 0x2u
2916 #define SIM_SCGC6_DMAMUX_SHIFT 1
2917 #define SIM_SCGC6_PIT_MASK 0x800000u
2918 #define SIM_SCGC6_PIT_SHIFT 23
2919 #define SIM_SCGC6_TPM0_MASK 0x1000000u
2920 #define SIM_SCGC6_TPM0_SHIFT 24
2921 #define SIM_SCGC6_TPM1_MASK 0x2000000u
2922 #define SIM_SCGC6_TPM1_SHIFT 25
2923 #define SIM_SCGC6_TPM2_MASK 0x4000000u
2924 #define SIM_SCGC6_TPM2_SHIFT 26
2925 #define SIM_SCGC6_ADC0_MASK 0x8000000u
2926 #define SIM_SCGC6_ADC0_SHIFT 27
2927 #define SIM_SCGC6_RTC_MASK 0x20000000u
2928 #define SIM_SCGC6_RTC_SHIFT 29
2929 #define SIM_SCGC6_DAC0_MASK 0x80000000u
2930 #define SIM_SCGC6_DAC0_SHIFT 31
2931 /* SCGC7 Bit Fields */
2932 #define SIM_SCGC7_DMA_MASK 0x100u
2933 #define SIM_SCGC7_DMA_SHIFT 8
2934 /* CLKDIV1 Bit Fields */
2935 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
2936 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
2937 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
2938 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
2939 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
2940 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
2941 /* FCFG1 Bit Fields */
2942 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
2943 #define SIM_FCFG1_FLASHDIS_SHIFT 0
2944 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
2945 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
2946 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
2947 #define SIM_FCFG1_PFSIZE_SHIFT 24
2948 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
2949 /* FCFG2 Bit Fields */
2950 #define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
2951 #define SIM_FCFG2_MAXADDR_SHIFT 24
2952 #define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
2953 /* UIDMH Bit Fields */
2954 #define SIM_UIDMH_UID_MASK 0xFFFFu
2955 #define SIM_UIDMH_UID_SHIFT 0
2956 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
2957 /* UIDML Bit Fields */
2958 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
2959 #define SIM_UIDML_UID_SHIFT 0
2960 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
2961 /* UIDL Bit Fields */
2962 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
2963 #define SIM_UIDL_UID_SHIFT 0
2964 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
2965 /* COPC Bit Fields */
2966 #define SIM_COPC_COPW_MASK 0x1u
2967 #define SIM_COPC_COPW_SHIFT 0
2968 #define SIM_COPC_COPCLKS_MASK 0x2u
2969 #define SIM_COPC_COPCLKS_SHIFT 1
2970 #define SIM_COPC_COPT_MASK 0xCu
2971 #define SIM_COPC_COPT_SHIFT 2
2972 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
2973 /* SRVCOP Bit Fields */
2974 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
2975 #define SIM_SRVCOP_SRVCOP_SHIFT 0
2976 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
2977
2978 /**
2979 * @}
2980 */ /* end of group SIM_Register_Masks */
2981
2982
2983 /* SIM - Peripheral instance base addresses */
2984 /** Peripheral SIM base address */
2985 #define SIM_BASE (0x40047000u)
2986 /** Peripheral SIM base pointer */
2987 #define SIM ((SIM_Type *)SIM_BASE)
2988 /** Array initializer of SIM peripheral base pointers */
2989 #define SIM_BASES { SIM }
2990
2991 /**
2992 * @}
2993 */ /* end of group SIM_Peripheral_Access_Layer */
2994
2995
2996 /* ----------------------------------------------------------------------------
2997 -- SMC Peripheral Access Layer
2998 ---------------------------------------------------------------------------- */
2999
3000 /**
3001 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
3002 * @{
3003 */
3004
3005 /** SMC - Register Layout Typedef */
3006 typedef struct {
3007 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
3008 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
3009 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
3010 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
3011 } SMC_Type;
3012
3013 /* ----------------------------------------------------------------------------
3014 -- SMC Register Masks
3015 ---------------------------------------------------------------------------- */
3016
3017 /**
3018 * @addtogroup SMC_Register_Masks SMC Register Masks
3019 * @{
3020 */
3021
3022 /* PMPROT Bit Fields */
3023 #define SMC_PMPROT_AVLLS_MASK 0x2u
3024 #define SMC_PMPROT_AVLLS_SHIFT 1
3025 #define SMC_PMPROT_ALLS_MASK 0x8u
3026 #define SMC_PMPROT_ALLS_SHIFT 3
3027 #define SMC_PMPROT_AVLP_MASK 0x20u
3028 #define SMC_PMPROT_AVLP_SHIFT 5
3029 /* PMCTRL Bit Fields */
3030 #define SMC_PMCTRL_STOPM_MASK 0x7u
3031 #define SMC_PMCTRL_STOPM_SHIFT 0
3032 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
3033 #define SMC_PMCTRL_STOPA_MASK 0x8u
3034 #define SMC_PMCTRL_STOPA_SHIFT 3
3035 #define SMC_PMCTRL_RUNM_MASK 0x60u
3036 #define SMC_PMCTRL_RUNM_SHIFT 5
3037 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
3038 /* STOPCTRL Bit Fields */
3039 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
3040 #define SMC_STOPCTRL_VLLSM_SHIFT 0
3041 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
3042 #define SMC_STOPCTRL_PORPO_MASK 0x20u
3043 #define SMC_STOPCTRL_PORPO_SHIFT 5
3044 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
3045 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
3046 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
3047 /* PMSTAT Bit Fields */
3048 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
3049 #define SMC_PMSTAT_PMSTAT_SHIFT 0
3050 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
3051
3052 /**
3053 * @}
3054 */ /* end of group SMC_Register_Masks */
3055
3056
3057 /* SMC - Peripheral instance base addresses */
3058 /** Peripheral SMC base address */
3059 #define SMC_BASE (0x4007E000u)
3060 /** Peripheral SMC base pointer */
3061 #define SMC ((SMC_Type *)SMC_BASE)
3062 /** Array initializer of SMC peripheral base pointers */
3063 #define SMC_BASES { SMC }
3064
3065 /**
3066 * @}
3067 */ /* end of group SMC_Peripheral_Access_Layer */
3068
3069
3070 /* ----------------------------------------------------------------------------
3071 -- SPI Peripheral Access Layer
3072 ---------------------------------------------------------------------------- */
3073
3074 /**
3075 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
3076 * @{
3077 */
3078
3079 /** SPI - Register Layout Typedef */
3080 typedef struct {
3081 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
3082 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
3083 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
3084 __I uint8_t S; /**< SPI status register, offset: 0x3 */
3085 uint8_t RESERVED_0[1];
3086 __IO uint8_t D; /**< SPI data register, offset: 0x5 */
3087 uint8_t RESERVED_1[1];
3088 __IO uint8_t M; /**< SPI match register, offset: 0x7 */
3089 } SPI_Type;
3090
3091 /* ----------------------------------------------------------------------------
3092 -- SPI Register Masks
3093 ---------------------------------------------------------------------------- */
3094
3095 /**
3096 * @addtogroup SPI_Register_Masks SPI Register Masks
3097 * @{
3098 */
3099
3100 /* C1 Bit Fields */
3101 #define SPI_C1_LSBFE_MASK 0x1u
3102 #define SPI_C1_LSBFE_SHIFT 0
3103 #define SPI_C1_SSOE_MASK 0x2u
3104 #define SPI_C1_SSOE_SHIFT 1
3105 #define SPI_C1_CPHA_MASK 0x4u
3106 #define SPI_C1_CPHA_SHIFT 2
3107 #define SPI_C1_CPOL_MASK 0x8u
3108 #define SPI_C1_CPOL_SHIFT 3
3109 #define SPI_C1_MSTR_MASK 0x10u
3110 #define SPI_C1_MSTR_SHIFT 4
3111 #define SPI_C1_SPTIE_MASK 0x20u
3112 #define SPI_C1_SPTIE_SHIFT 5
3113 #define SPI_C1_SPE_MASK 0x40u
3114 #define SPI_C1_SPE_SHIFT 6
3115 #define SPI_C1_SPIE_MASK 0x80u
3116 #define SPI_C1_SPIE_SHIFT 7
3117 /* C2 Bit Fields */
3118 #define SPI_C2_SPC0_MASK 0x1u
3119 #define SPI_C2_SPC0_SHIFT 0
3120 #define SPI_C2_SPISWAI_MASK 0x2u
3121 #define SPI_C2_SPISWAI_SHIFT 1
3122 #define SPI_C2_RXDMAE_MASK 0x4u
3123 #define SPI_C2_RXDMAE_SHIFT 2
3124 #define SPI_C2_BIDIROE_MASK 0x8u
3125 #define SPI_C2_BIDIROE_SHIFT 3
3126 #define SPI_C2_MODFEN_MASK 0x10u
3127 #define SPI_C2_MODFEN_SHIFT 4
3128 #define SPI_C2_TXDMAE_MASK 0x20u
3129 #define SPI_C2_TXDMAE_SHIFT 5
3130 #define SPI_C2_SPLPIE_MASK 0x40u
3131 #define SPI_C2_SPLPIE_SHIFT 6
3132 #define SPI_C2_SPMIE_MASK 0x80u
3133 #define SPI_C2_SPMIE_SHIFT 7
3134 /* BR Bit Fields */
3135 #define SPI_BR_SPR_MASK 0xFu
3136 #define SPI_BR_SPR_SHIFT 0
3137 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
3138 #define SPI_BR_SPPR_MASK 0x70u
3139 #define SPI_BR_SPPR_SHIFT 4
3140 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
3141 /* S Bit Fields */
3142 #define SPI_S_MODF_MASK 0x10u
3143 #define SPI_S_MODF_SHIFT 4
3144 #define SPI_S_SPTEF_MASK 0x20u
3145 #define SPI_S_SPTEF_SHIFT 5
3146 #define SPI_S_SPMF_MASK 0x40u
3147 #define SPI_S_SPMF_SHIFT 6
3148 #define SPI_S_SPRF_MASK 0x80u
3149 #define SPI_S_SPRF_SHIFT 7
3150 /* D Bit Fields */
3151 #define SPI_D_Bits_MASK 0xFFu
3152 #define SPI_D_Bits_SHIFT 0
3153 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
3154 /* M Bit Fields */
3155 #define SPI_M_Bits_MASK 0xFFu
3156 #define SPI_M_Bits_SHIFT 0
3157 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
3158
3159 /**
3160 * @}
3161 */ /* end of group SPI_Register_Masks */
3162
3163
3164 /* SPI - Peripheral instance base addresses */
3165 /** Peripheral SPI0 base address */
3166 #define SPI0_BASE (0x40076000u)
3167 /** Peripheral SPI0 base pointer */
3168 #define SPI0 ((SPI_Type *)SPI0_BASE)
3169 /** Peripheral SPI1 base address */
3170 #define SPI1_BASE (0x40077000u)
3171 /** Peripheral SPI1 base pointer */
3172 #define SPI1 ((SPI_Type *)SPI1_BASE)
3173 /** Array initializer of SPI peripheral base pointers */
3174 #define SPI_BASES { SPI0, SPI1 }
3175
3176 /**
3177 * @}
3178 */ /* end of group SPI_Peripheral_Access_Layer */
3179
3180
3181 /* ----------------------------------------------------------------------------
3182 -- TPM Peripheral Access Layer
3183 ---------------------------------------------------------------------------- */
3184
3185 /**
3186 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
3187 * @{
3188 */
3189
3190 /** TPM - Register Layout Typedef */
3191 typedef struct {
3192 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
3193 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
3194 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
3195 struct { /* offset: 0xC, array step: 0x8 */
3196 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
3197 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
3198 } CONTROLS[6];
3199 uint8_t RESERVED_0[20];
3200 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
3201 uint8_t RESERVED_1[48];
3202 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
3203 } TPM_Type;
3204
3205 /* ----------------------------------------------------------------------------
3206 -- TPM Register Masks
3207 ---------------------------------------------------------------------------- */
3208
3209 /**
3210 * @addtogroup TPM_Register_Masks TPM Register Masks
3211 * @{
3212 */
3213
3214 /* SC Bit Fields */
3215 #define TPM_SC_PS_MASK 0x7u
3216 #define TPM_SC_PS_SHIFT 0
3217 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
3218 #define TPM_SC_CMOD_MASK 0x18u
3219 #define TPM_SC_CMOD_SHIFT 3
3220 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
3221 #define TPM_SC_CPWMS_MASK 0x20u
3222 #define TPM_SC_CPWMS_SHIFT 5
3223 #define TPM_SC_TOIE_MASK 0x40u
3224 #define TPM_SC_TOIE_SHIFT 6
3225 #define TPM_SC_TOF_MASK 0x80u
3226 #define TPM_SC_TOF_SHIFT 7
3227 #define TPM_SC_DMA_MASK 0x100u
3228 #define TPM_SC_DMA_SHIFT 8
3229 /* CNT Bit Fields */
3230 #define TPM_CNT_COUNT_MASK 0xFFFFu
3231 #define TPM_CNT_COUNT_SHIFT 0
3232 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
3233 /* MOD Bit Fields */
3234 #define TPM_MOD_MOD_MASK 0xFFFFu
3235 #define TPM_MOD_MOD_SHIFT 0
3236 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
3237 /* CnSC Bit Fields */
3238 #define TPM_CnSC_DMA_MASK 0x1u
3239 #define TPM_CnSC_DMA_SHIFT 0
3240 #define TPM_CnSC_ELSA_MASK 0x4u
3241 #define TPM_CnSC_ELSA_SHIFT 2
3242 #define TPM_CnSC_ELSB_MASK 0x8u
3243 #define TPM_CnSC_ELSB_SHIFT 3
3244 #define TPM_CnSC_MSA_MASK 0x10u
3245 #define TPM_CnSC_MSA_SHIFT 4
3246 #define TPM_CnSC_MSB_MASK 0x20u
3247 #define TPM_CnSC_MSB_SHIFT 5
3248 #define TPM_CnSC_CHIE_MASK 0x40u
3249 #define TPM_CnSC_CHIE_SHIFT 6
3250 #define TPM_CnSC_CHF_MASK 0x80u
3251 #define TPM_CnSC_CHF_SHIFT 7
3252 /* CnV Bit Fields */
3253 #define TPM_CnV_VAL_MASK 0xFFFFu
3254 #define TPM_CnV_VAL_SHIFT 0
3255 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
3256 /* STATUS Bit Fields */
3257 #define TPM_STATUS_CH0F_MASK 0x1u
3258 #define TPM_STATUS_CH0F_SHIFT 0
3259 #define TPM_STATUS_CH1F_MASK 0x2u
3260 #define TPM_STATUS_CH1F_SHIFT 1
3261 #define TPM_STATUS_CH2F_MASK 0x4u
3262 #define TPM_STATUS_CH2F_SHIFT 2
3263 #define TPM_STATUS_CH3F_MASK 0x8u
3264 #define TPM_STATUS_CH3F_SHIFT 3
3265 #define TPM_STATUS_CH4F_MASK 0x10u
3266 #define TPM_STATUS_CH4F_SHIFT 4
3267 #define TPM_STATUS_CH5F_MASK 0x20u
3268 #define TPM_STATUS_CH5F_SHIFT 5
3269 #define TPM_STATUS_TOF_MASK 0x100u
3270 #define TPM_STATUS_TOF_SHIFT 8
3271 /* CONF Bit Fields */
3272 #define TPM_CONF_DOZEEN_MASK 0x20u
3273 #define TPM_CONF_DOZEEN_SHIFT 5
3274 #define TPM_CONF_DBGMODE_MASK 0xC0u
3275 #define TPM_CONF_DBGMODE_SHIFT 6
3276 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
3277 #define TPM_CONF_GTBEEN_MASK 0x200u
3278 #define TPM_CONF_GTBEEN_SHIFT 9
3279 #define TPM_CONF_CSOT_MASK 0x10000u
3280 #define TPM_CONF_CSOT_SHIFT 16
3281 #define TPM_CONF_CSOO_MASK 0x20000u
3282 #define TPM_CONF_CSOO_SHIFT 17
3283 #define TPM_CONF_CROT_MASK 0x40000u
3284 #define TPM_CONF_CROT_SHIFT 18
3285 #define TPM_CONF_TRGSEL_MASK 0xF000000u
3286 #define TPM_CONF_TRGSEL_SHIFT 24
3287 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
3288
3289 /**
3290 * @}
3291 */ /* end of group TPM_Register_Masks */
3292
3293
3294 /* TPM - Peripheral instance base addresses */
3295 /** Peripheral TPM0 base address */
3296 #define TPM0_BASE (0x40038000u)
3297 /** Peripheral TPM0 base pointer */
3298 #define TPM0 ((TPM_Type *)TPM0_BASE)
3299 /** Peripheral TPM1 base address */
3300 #define TPM1_BASE (0x40039000u)
3301 /** Peripheral TPM1 base pointer */
3302 #define TPM1 ((TPM_Type *)TPM1_BASE)
3303 /** Peripheral TPM2 base address */
3304 #define TPM2_BASE (0x4003A000u)
3305 /** Peripheral TPM2 base pointer */
3306 #define TPM2 ((TPM_Type *)TPM2_BASE)
3307 /** Array initializer of TPM peripheral base pointers */
3308 #define TPM_BASES { TPM0, TPM1, TPM2 }
3309
3310 /**
3311 * @}
3312 */ /* end of group TPM_Peripheral_Access_Layer */
3313
3314
3315 /* ----------------------------------------------------------------------------
3316 -- TSI Peripheral Access Layer
3317 ---------------------------------------------------------------------------- */
3318
3319 /**
3320 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
3321 * @{
3322 */
3323
3324 /** TSI - Register Layout Typedef */
3325 typedef struct {
3326 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
3327 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
3328 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
3329 } TSI_Type;
3330
3331 /* ----------------------------------------------------------------------------
3332 -- TSI Register Masks
3333 ---------------------------------------------------------------------------- */
3334
3335 /**
3336 * @addtogroup TSI_Register_Masks TSI Register Masks
3337 * @{
3338 */
3339
3340 /* GENCS Bit Fields */
3341 #define TSI_GENCS_CURSW_MASK 0x2u
3342 #define TSI_GENCS_CURSW_SHIFT 1
3343 #define TSI_GENCS_EOSF_MASK 0x4u
3344 #define TSI_GENCS_EOSF_SHIFT 2
3345 #define TSI_GENCS_SCNIP_MASK 0x8u
3346 #define TSI_GENCS_SCNIP_SHIFT 3
3347 #define TSI_GENCS_STM_MASK 0x10u
3348 #define TSI_GENCS_STM_SHIFT 4
3349 #define TSI_GENCS_STPE_MASK 0x20u
3350 #define TSI_GENCS_STPE_SHIFT 5
3351 #define TSI_GENCS_TSIIEN_MASK 0x40u
3352 #define TSI_GENCS_TSIIEN_SHIFT 6
3353 #define TSI_GENCS_TSIEN_MASK 0x80u
3354 #define TSI_GENCS_TSIEN_SHIFT 7
3355 #define TSI_GENCS_NSCN_MASK 0x1F00u
3356 #define TSI_GENCS_NSCN_SHIFT 8
3357 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
3358 #define TSI_GENCS_PS_MASK 0xE000u
3359 #define TSI_GENCS_PS_SHIFT 13
3360 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
3361 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
3362 #define TSI_GENCS_EXTCHRG_SHIFT 16
3363 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
3364 #define TSI_GENCS_DVOLT_MASK 0x180000u
3365 #define TSI_GENCS_DVOLT_SHIFT 19
3366 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
3367 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
3368 #define TSI_GENCS_REFCHRG_SHIFT 21
3369 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
3370 #define TSI_GENCS_MODE_MASK 0xF000000u
3371 #define TSI_GENCS_MODE_SHIFT 24
3372 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
3373 #define TSI_GENCS_ESOR_MASK 0x10000000u
3374 #define TSI_GENCS_ESOR_SHIFT 28
3375 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
3376 #define TSI_GENCS_OUTRGF_SHIFT 31
3377 /* DATA Bit Fields */
3378 #define TSI_DATA_TSICNT_MASK 0xFFFFu
3379 #define TSI_DATA_TSICNT_SHIFT 0
3380 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
3381 #define TSI_DATA_SWTS_MASK 0x400000u
3382 #define TSI_DATA_SWTS_SHIFT 22
3383 #define TSI_DATA_DMAEN_MASK 0x800000u
3384 #define TSI_DATA_DMAEN_SHIFT 23
3385 #define TSI_DATA_TSICH_MASK 0xF0000000u
3386 #define TSI_DATA_TSICH_SHIFT 28
3387 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
3388 /* TSHD Bit Fields */
3389 #define TSI_TSHD_THRESL_MASK 0xFFFFu
3390 #define TSI_TSHD_THRESL_SHIFT 0
3391 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
3392 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
3393 #define TSI_TSHD_THRESH_SHIFT 16
3394 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
3395
3396 /**
3397 * @}
3398 */ /* end of group TSI_Register_Masks */
3399
3400
3401 /* TSI - Peripheral instance base addresses */
3402 /** Peripheral TSI0 base address */
3403 #define TSI0_BASE (0x40045000u)
3404 /** Peripheral TSI0 base pointer */
3405 #define TSI0 ((TSI_Type *)TSI0_BASE)
3406 /** Array initializer of TSI peripheral base pointers */
3407 #define TSI_BASES { TSI0 }
3408
3409 /**
3410 * @}
3411 */ /* end of group TSI_Peripheral_Access_Layer */
3412
3413
3414 /* ----------------------------------------------------------------------------
3415 -- UART Peripheral Access Layer
3416 ---------------------------------------------------------------------------- */
3417
3418 /**
3419 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
3420 * @{
3421 */
3422
3423 /** UART - Register Layout Typedef */
3424 typedef struct {
3425 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
3426 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
3427 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
3428 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
3429 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
3430 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
3431 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
3432 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
3433 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
3434 } UART_Type;
3435
3436 /* ----------------------------------------------------------------------------
3437 -- UART Register Masks
3438 ---------------------------------------------------------------------------- */
3439
3440 /**
3441 * @addtogroup UART_Register_Masks UART Register Masks
3442 * @{
3443 */
3444
3445 /* BDH Bit Fields */
3446 #define UART_BDH_SBR_MASK 0x1Fu
3447 #define UART_BDH_SBR_SHIFT 0
3448 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
3449 #define UART_BDH_SBNS_MASK 0x20u
3450 #define UART_BDH_SBNS_SHIFT 5
3451 #define UART_BDH_RXEDGIE_MASK 0x40u
3452 #define UART_BDH_RXEDGIE_SHIFT 6
3453 #define UART_BDH_LBKDIE_MASK 0x80u
3454 #define UART_BDH_LBKDIE_SHIFT 7
3455 /* BDL Bit Fields */
3456 #define UART_BDL_SBR_MASK 0xFFu
3457 #define UART_BDL_SBR_SHIFT 0
3458 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
3459 /* C1 Bit Fields */
3460 #define UART_C1_PT_MASK 0x1u
3461 #define UART_C1_PT_SHIFT 0
3462 #define UART_C1_PE_MASK 0x2u
3463 #define UART_C1_PE_SHIFT 1
3464 #define UART_C1_ILT_MASK 0x4u
3465 #define UART_C1_ILT_SHIFT 2
3466 #define UART_C1_WAKE_MASK 0x8u
3467 #define UART_C1_WAKE_SHIFT 3
3468 #define UART_C1_M_MASK 0x10u
3469 #define UART_C1_M_SHIFT 4
3470 #define UART_C1_RSRC_MASK 0x20u
3471 #define UART_C1_RSRC_SHIFT 5
3472 #define UART_C1_UARTSWAI_MASK 0x40u
3473 #define UART_C1_UARTSWAI_SHIFT 6
3474 #define UART_C1_LOOPS_MASK 0x80u
3475 #define UART_C1_LOOPS_SHIFT 7
3476 /* C2 Bit Fields */
3477 #define UART_C2_SBK_MASK 0x1u
3478 #define UART_C2_SBK_SHIFT 0
3479 #define UART_C2_RWU_MASK 0x2u
3480 #define UART_C2_RWU_SHIFT 1
3481 #define UART_C2_RE_MASK 0x4u
3482 #define UART_C2_RE_SHIFT 2
3483 #define UART_C2_TE_MASK 0x8u
3484 #define UART_C2_TE_SHIFT 3
3485 #define UART_C2_ILIE_MASK 0x10u
3486 #define UART_C2_ILIE_SHIFT 4
3487 #define UART_C2_RIE_MASK 0x20u
3488 #define UART_C2_RIE_SHIFT 5
3489 #define UART_C2_TCIE_MASK 0x40u
3490 #define UART_C2_TCIE_SHIFT 6
3491 #define UART_C2_TIE_MASK 0x80u
3492 #define UART_C2_TIE_SHIFT 7
3493 /* S1 Bit Fields */
3494 #define UART_S1_PF_MASK 0x1u
3495 #define UART_S1_PF_SHIFT 0
3496 #define UART_S1_FE_MASK 0x2u
3497 #define UART_S1_FE_SHIFT 1
3498 #define UART_S1_NF_MASK 0x4u
3499 #define UART_S1_NF_SHIFT 2
3500 #define UART_S1_OR_MASK 0x8u
3501 #define UART_S1_OR_SHIFT 3
3502 #define UART_S1_IDLE_MASK 0x10u
3503 #define UART_S1_IDLE_SHIFT 4
3504 #define UART_S1_RDRF_MASK 0x20u
3505 #define UART_S1_RDRF_SHIFT 5
3506 #define UART_S1_TC_MASK 0x40u
3507 #define UART_S1_TC_SHIFT 6
3508 #define UART_S1_TDRE_MASK 0x80u
3509 #define UART_S1_TDRE_SHIFT 7
3510 /* S2 Bit Fields */
3511 #define UART_S2_RAF_MASK 0x1u
3512 #define UART_S2_RAF_SHIFT 0
3513 #define UART_S2_LBKDE_MASK 0x2u
3514 #define UART_S2_LBKDE_SHIFT 1
3515 #define UART_S2_BRK13_MASK 0x4u
3516 #define UART_S2_BRK13_SHIFT 2
3517 #define UART_S2_RWUID_MASK 0x8u
3518 #define UART_S2_RWUID_SHIFT 3
3519 #define UART_S2_RXINV_MASK 0x10u
3520 #define UART_S2_RXINV_SHIFT 4
3521 #define UART_S2_RXEDGIF_MASK 0x40u
3522 #define UART_S2_RXEDGIF_SHIFT 6
3523 #define UART_S2_LBKDIF_MASK 0x80u
3524 #define UART_S2_LBKDIF_SHIFT 7
3525 /* C3 Bit Fields */
3526 #define UART_C3_PEIE_MASK 0x1u
3527 #define UART_C3_PEIE_SHIFT 0
3528 #define UART_C3_FEIE_MASK 0x2u
3529 #define UART_C3_FEIE_SHIFT 1
3530 #define UART_C3_NEIE_MASK 0x4u
3531 #define UART_C3_NEIE_SHIFT 2
3532 #define UART_C3_ORIE_MASK 0x8u
3533 #define UART_C3_ORIE_SHIFT 3
3534 #define UART_C3_TXINV_MASK 0x10u
3535 #define UART_C3_TXINV_SHIFT 4
3536 #define UART_C3_TXDIR_MASK 0x20u
3537 #define UART_C3_TXDIR_SHIFT 5
3538 #define UART_C3_T8_MASK 0x40u
3539 #define UART_C3_T8_SHIFT 6
3540 #define UART_C3_R8_MASK 0x80u
3541 #define UART_C3_R8_SHIFT 7
3542 /* D Bit Fields */
3543 #define UART_D_R0T0_MASK 0x1u
3544 #define UART_D_R0T0_SHIFT 0
3545 #define UART_D_R1T1_MASK 0x2u
3546 #define UART_D_R1T1_SHIFT 1
3547 #define UART_D_R2T2_MASK 0x4u
3548 #define UART_D_R2T2_SHIFT 2
3549 #define UART_D_R3T3_MASK 0x8u
3550 #define UART_D_R3T3_SHIFT 3
3551 #define UART_D_R4T4_MASK 0x10u
3552 #define UART_D_R4T4_SHIFT 4
3553 #define UART_D_R5T5_MASK 0x20u
3554 #define UART_D_R5T5_SHIFT 5
3555 #define UART_D_R6T6_MASK 0x40u
3556 #define UART_D_R6T6_SHIFT 6
3557 #define UART_D_R7T7_MASK 0x80u
3558 #define UART_D_R7T7_SHIFT 7
3559 /* C4 Bit Fields */
3560 #define UART_C4_LBKDDMAS_MASK 0x8u
3561 #define UART_C4_LBKDDMAS_SHIFT 3
3562 #define UART_C4_ILDMAS_MASK 0x10u
3563 #define UART_C4_ILDMAS_SHIFT 4
3564 #define UART_C4_RDMAS_MASK 0x20u
3565 #define UART_C4_RDMAS_SHIFT 5
3566 #define UART_C4_TCDMAS_MASK 0x40u
3567 #define UART_C4_TCDMAS_SHIFT 6
3568 #define UART_C4_TDMAS_MASK 0x80u
3569 #define UART_C4_TDMAS_SHIFT 7
3570
3571 /**
3572 * @}
3573 */ /* end of group UART_Register_Masks */
3574
3575
3576 /* UART - Peripheral instance base addresses */
3577 /** Peripheral UART1 base address */
3578 #define UART1_BASE (0x4006B000u)
3579 /** Peripheral UART1 base pointer */
3580 #define UART1 ((UART_Type *)UART1_BASE)
3581 /** Peripheral UART2 base address */
3582 #define UART2_BASE (0x4006C000u)
3583 /** Peripheral UART2 base pointer */
3584 #define UART2 ((UART_Type *)UART2_BASE)
3585 /** Array initializer of UART peripheral base pointers */
3586 #define UART_BASES { UART1, UART2 }
3587
3588 /**
3589 * @}
3590 */ /* end of group UART_Peripheral_Access_Layer */
3591
3592
3593 /* ----------------------------------------------------------------------------
3594 -- UARTLP Peripheral Access Layer
3595 ---------------------------------------------------------------------------- */
3596
3597 /**
3598 * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
3599 * @{
3600 */
3601
3602 /** UARTLP - Register Layout Typedef */
3603 typedef struct {
3604 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
3605 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
3606 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
3607 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
3608 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
3609 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
3610 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
3611 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
3612 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
3613 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
3614 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
3615 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
3616 } UARTLP_Type;
3617
3618 /* ----------------------------------------------------------------------------
3619 -- UARTLP Register Masks
3620 ---------------------------------------------------------------------------- */
3621
3622 /**
3623 * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
3624 * @{
3625 */
3626
3627 /* BDH Bit Fields */
3628 #define UARTLP_BDH_SBR_MASK 0x1Fu
3629 #define UARTLP_BDH_SBR_SHIFT 0
3630 #define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
3631 #define UARTLP_BDH_SBNS_MASK 0x20u
3632 #define UARTLP_BDH_SBNS_SHIFT 5
3633 #define UARTLP_BDH_RXEDGIE_MASK 0x40u
3634 #define UARTLP_BDH_RXEDGIE_SHIFT 6
3635 #define UARTLP_BDH_LBKDIE_MASK 0x80u
3636 #define UARTLP_BDH_LBKDIE_SHIFT 7
3637 /* BDL Bit Fields */
3638 #define UARTLP_BDL_SBR_MASK 0xFFu
3639 #define UARTLP_BDL_SBR_SHIFT 0
3640 #define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
3641 /* C1 Bit Fields */
3642 #define UARTLP_C1_PT_MASK 0x1u
3643 #define UARTLP_C1_PT_SHIFT 0
3644 #define UARTLP_C1_PE_MASK 0x2u
3645 #define UARTLP_C1_PE_SHIFT 1
3646 #define UARTLP_C1_ILT_MASK 0x4u
3647 #define UARTLP_C1_ILT_SHIFT 2
3648 #define UARTLP_C1_WAKE_MASK 0x8u
3649 #define UARTLP_C1_WAKE_SHIFT 3
3650 #define UARTLP_C1_M_MASK 0x10u
3651 #define UARTLP_C1_M_SHIFT 4
3652 #define UARTLP_C1_RSRC_MASK 0x20u
3653 #define UARTLP_C1_RSRC_SHIFT 5
3654 #define UARTLP_C1_DOZEEN_MASK 0x40u
3655 #define UARTLP_C1_DOZEEN_SHIFT 6
3656 #define UARTLP_C1_LOOPS_MASK 0x80u
3657 #define UARTLP_C1_LOOPS_SHIFT 7
3658 /* C2 Bit Fields */
3659 #define UARTLP_C2_SBK_MASK 0x1u
3660 #define UARTLP_C2_SBK_SHIFT 0
3661 #define UARTLP_C2_RWU_MASK 0x2u
3662 #define UARTLP_C2_RWU_SHIFT 1
3663 #define UARTLP_C2_RE_MASK 0x4u
3664 #define UARTLP_C2_RE_SHIFT 2
3665 #define UARTLP_C2_TE_MASK 0x8u
3666 #define UARTLP_C2_TE_SHIFT 3
3667 #define UARTLP_C2_ILIE_MASK 0x10u
3668 #define UARTLP_C2_ILIE_SHIFT 4
3669 #define UARTLP_C2_RIE_MASK 0x20u
3670 #define UARTLP_C2_RIE_SHIFT 5
3671 #define UARTLP_C2_TCIE_MASK 0x40u
3672 #define UARTLP_C2_TCIE_SHIFT 6
3673 #define UARTLP_C2_TIE_MASK 0x80u
3674 #define UARTLP_C2_TIE_SHIFT 7
3675 /* S1 Bit Fields */
3676 #define UARTLP_S1_PF_MASK 0x1u
3677 #define UARTLP_S1_PF_SHIFT 0
3678 #define UARTLP_S1_FE_MASK 0x2u
3679 #define UARTLP_S1_FE_SHIFT 1
3680 #define UARTLP_S1_NF_MASK 0x4u
3681 #define UARTLP_S1_NF_SHIFT 2
3682 #define UARTLP_S1_OR_MASK 0x8u
3683 #define UARTLP_S1_OR_SHIFT 3
3684 #define UARTLP_S1_IDLE_MASK 0x10u
3685 #define UARTLP_S1_IDLE_SHIFT 4
3686 #define UARTLP_S1_RDRF_MASK 0x20u
3687 #define UARTLP_S1_RDRF_SHIFT 5
3688 #define UARTLP_S1_TC_MASK 0x40u
3689 #define UARTLP_S1_TC_SHIFT 6
3690 #define UARTLP_S1_TDRE_MASK 0x80u
3691 #define UARTLP_S1_TDRE_SHIFT 7
3692 /* S2 Bit Fields */
3693 #define UARTLP_S2_RAF_MASK 0x1u
3694 #define UARTLP_S2_RAF_SHIFT 0
3695 #define UARTLP_S2_LBKDE_MASK 0x2u
3696 #define UARTLP_S2_LBKDE_SHIFT 1
3697 #define UARTLP_S2_BRK13_MASK 0x4u
3698 #define UARTLP_S2_BRK13_SHIFT 2
3699 #define UARTLP_S2_RWUID_MASK 0x8u
3700 #define UARTLP_S2_RWUID_SHIFT 3
3701 #define UARTLP_S2_RXINV_MASK 0x10u
3702 #define UARTLP_S2_RXINV_SHIFT 4
3703 #define UARTLP_S2_MSBF_MASK 0x20u
3704 #define UARTLP_S2_MSBF_SHIFT 5
3705 #define UARTLP_S2_RXEDGIF_MASK 0x40u
3706 #define UARTLP_S2_RXEDGIF_SHIFT 6
3707 #define UARTLP_S2_LBKDIF_MASK 0x80u
3708 #define UARTLP_S2_LBKDIF_SHIFT 7
3709 /* C3 Bit Fields */
3710 #define UARTLP_C3_PEIE_MASK 0x1u
3711 #define UARTLP_C3_PEIE_SHIFT 0
3712 #define UARTLP_C3_FEIE_MASK 0x2u
3713 #define UARTLP_C3_FEIE_SHIFT 1
3714 #define UARTLP_C3_NEIE_MASK 0x4u
3715 #define UARTLP_C3_NEIE_SHIFT 2
3716 #define UARTLP_C3_ORIE_MASK 0x8u
3717 #define UARTLP_C3_ORIE_SHIFT 3
3718 #define UARTLP_C3_TXINV_MASK 0x10u
3719 #define UARTLP_C3_TXINV_SHIFT 4
3720 #define UARTLP_C3_TXDIR_MASK 0x20u
3721 #define UARTLP_C3_TXDIR_SHIFT 5
3722 #define UARTLP_C3_R9T8_MASK 0x40u
3723 #define UARTLP_C3_R9T8_SHIFT 6
3724 #define UARTLP_C3_R8T9_MASK 0x80u
3725 #define UARTLP_C3_R8T9_SHIFT 7
3726 /* D Bit Fields */
3727 #define UARTLP_D_R0T0_MASK 0x1u
3728 #define UARTLP_D_R0T0_SHIFT 0
3729 #define UARTLP_D_R1T1_MASK 0x2u
3730 #define UARTLP_D_R1T1_SHIFT 1
3731 #define UARTLP_D_R2T2_MASK 0x4u
3732 #define UARTLP_D_R2T2_SHIFT 2
3733 #define UARTLP_D_R3T3_MASK 0x8u
3734 #define UARTLP_D_R3T3_SHIFT 3
3735 #define UARTLP_D_R4T4_MASK 0x10u
3736 #define UARTLP_D_R4T4_SHIFT 4
3737 #define UARTLP_D_R5T5_MASK 0x20u
3738 #define UARTLP_D_R5T5_SHIFT 5
3739 #define UARTLP_D_R6T6_MASK 0x40u
3740 #define UARTLP_D_R6T6_SHIFT 6
3741 #define UARTLP_D_R7T7_MASK 0x80u
3742 #define UARTLP_D_R7T7_SHIFT 7
3743 /* MA1 Bit Fields */
3744 #define UARTLP_MA1_MA_MASK 0xFFu
3745 #define UARTLP_MA1_MA_SHIFT 0
3746 #define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
3747 /* MA2 Bit Fields */
3748 #define UARTLP_MA2_MA_MASK 0xFFu
3749 #define UARTLP_MA2_MA_SHIFT 0
3750 #define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
3751 /* C4 Bit Fields */
3752 #define UARTLP_C4_OSR_MASK 0x1Fu
3753 #define UARTLP_C4_OSR_SHIFT 0
3754 #define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
3755 #define UARTLP_C4_M10_MASK 0x20u
3756 #define UARTLP_C4_M10_SHIFT 5
3757 #define UARTLP_C4_MAEN2_MASK 0x40u
3758 #define UARTLP_C4_MAEN2_SHIFT 6
3759 #define UARTLP_C4_MAEN1_MASK 0x80u
3760 #define UARTLP_C4_MAEN1_SHIFT 7
3761 /* C5 Bit Fields */
3762 #define UARTLP_C5_RESYNCDIS_MASK 0x1u
3763 #define UARTLP_C5_RESYNCDIS_SHIFT 0
3764 #define UARTLP_C5_BOTHEDGE_MASK 0x2u
3765 #define UARTLP_C5_BOTHEDGE_SHIFT 1
3766 #define UARTLP_C5_RDMAE_MASK 0x20u
3767 #define UARTLP_C5_RDMAE_SHIFT 5
3768 #define UARTLP_C5_TDMAE_MASK 0x80u
3769 #define UARTLP_C5_TDMAE_SHIFT 7
3770
3771 /**
3772 * @}
3773 */ /* end of group UARTLP_Register_Masks */
3774
3775
3776 /* UARTLP - Peripheral instance base addresses */
3777 /** Peripheral UART0 base address */
3778 #define UART0_BASE (0x4006A000u)
3779 /** Peripheral UART0 base pointer */
3780 #define UART0 ((UARTLP_Type *)UART0_BASE)
3781 /** Array initializer of UARTLP peripheral base pointers */
3782 #define UARTLP_BASES { UART0 }
3783
3784 /**
3785 * @}
3786 */ /* end of group UARTLP_Peripheral_Access_Layer */
3787
3788
3789 /* ----------------------------------------------------------------------------
3790 -- USB Peripheral Access Layer
3791 ---------------------------------------------------------------------------- */
3792
3793 /**
3794 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
3795 * @{
3796 */
3797
3798 /** USB - Register Layout Typedef */
3799 typedef struct {
3800 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
3801 uint8_t RESERVED_0[3];
3802 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
3803 uint8_t RESERVED_1[3];
3804 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
3805 uint8_t RESERVED_2[3];
3806 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
3807 uint8_t RESERVED_3[3];
3808 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
3809 uint8_t RESERVED_4[3];
3810 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
3811 uint8_t RESERVED_5[3];
3812 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
3813 uint8_t RESERVED_6[3];
3814 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
3815 uint8_t RESERVED_7[99];
3816 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
3817 uint8_t RESERVED_8[3];
3818 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
3819 uint8_t RESERVED_9[3];
3820 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
3821 uint8_t RESERVED_10[3];
3822 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
3823 uint8_t RESERVED_11[3];
3824 __I uint8_t STAT; /**< Status register, offset: 0x90 */
3825 uint8_t RESERVED_12[3];
3826 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
3827 uint8_t RESERVED_13[3];
3828 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
3829 uint8_t RESERVED_14[3];
3830 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
3831 uint8_t RESERVED_15[3];
3832 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
3833 uint8_t RESERVED_16[3];
3834 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
3835 uint8_t RESERVED_17[3];
3836 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
3837 uint8_t RESERVED_18[3];
3838 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
3839 uint8_t RESERVED_19[3];
3840 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
3841 uint8_t RESERVED_20[3];
3842 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
3843 uint8_t RESERVED_21[11];
3844 struct { /* offset: 0xC0, array step: 0x4 */
3845 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
3846 uint8_t RESERVED_0[3];
3847 } ENDPOINT[16];
3848 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
3849 uint8_t RESERVED_22[3];
3850 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
3851 uint8_t RESERVED_23[3];
3852 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
3853 uint8_t RESERVED_24[3];
3854 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
3855 } USB_Type;
3856
3857 /* ----------------------------------------------------------------------------
3858 -- USB Register Masks
3859 ---------------------------------------------------------------------------- */
3860
3861 /**
3862 * @addtogroup USB_Register_Masks USB Register Masks
3863 * @{
3864 */
3865
3866 /* PERID Bit Fields */
3867 #define USB_PERID_ID_MASK 0x3Fu
3868 #define USB_PERID_ID_SHIFT 0
3869 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
3870 /* IDCOMP Bit Fields */
3871 #define USB_IDCOMP_NID_MASK 0x3Fu
3872 #define USB_IDCOMP_NID_SHIFT 0
3873 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
3874 /* REV Bit Fields */
3875 #define USB_REV_REV_MASK 0xFFu
3876 #define USB_REV_REV_SHIFT 0
3877 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
3878 /* ADDINFO Bit Fields */
3879 #define USB_ADDINFO_IEHOST_MASK 0x1u
3880 #define USB_ADDINFO_IEHOST_SHIFT 0
3881 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
3882 #define USB_ADDINFO_IRQNUM_SHIFT 3
3883 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
3884 /* OTGISTAT Bit Fields */
3885 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
3886 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
3887 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
3888 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
3889 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
3890 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
3891 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
3892 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
3893 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
3894 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
3895 #define USB_OTGISTAT_IDCHG_MASK 0x80u
3896 #define USB_OTGISTAT_IDCHG_SHIFT 7
3897 /* OTGICR Bit Fields */
3898 #define USB_OTGICR_AVBUSEN_MASK 0x1u
3899 #define USB_OTGICR_AVBUSEN_SHIFT 0
3900 #define USB_OTGICR_BSESSEN_MASK 0x4u
3901 #define USB_OTGICR_BSESSEN_SHIFT 2
3902 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
3903 #define USB_OTGICR_SESSVLDEN_SHIFT 3
3904 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
3905 #define USB_OTGICR_LINESTATEEN_SHIFT 5
3906 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
3907 #define USB_OTGICR_ONEMSECEN_SHIFT 6
3908 #define USB_OTGICR_IDEN_MASK 0x80u
3909 #define USB_OTGICR_IDEN_SHIFT 7
3910 /* OTGSTAT Bit Fields */
3911 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
3912 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
3913 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
3914 #define USB_OTGSTAT_BSESSEND_SHIFT 2
3915 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
3916 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
3917 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
3918 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
3919 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
3920 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
3921 #define USB_OTGSTAT_ID_MASK 0x80u
3922 #define USB_OTGSTAT_ID_SHIFT 7
3923 /* OTGCTL Bit Fields */
3924 #define USB_OTGCTL_OTGEN_MASK 0x4u
3925 #define USB_OTGCTL_OTGEN_SHIFT 2
3926 #define USB_OTGCTL_DMLOW_MASK 0x10u
3927 #define USB_OTGCTL_DMLOW_SHIFT 4
3928 #define USB_OTGCTL_DPLOW_MASK 0x20u
3929 #define USB_OTGCTL_DPLOW_SHIFT 5
3930 #define USB_OTGCTL_DPHIGH_MASK 0x80u
3931 #define USB_OTGCTL_DPHIGH_SHIFT 7
3932 /* ISTAT Bit Fields */
3933 #define USB_ISTAT_USBRST_MASK 0x1u
3934 #define USB_ISTAT_USBRST_SHIFT 0
3935 #define USB_ISTAT_ERROR_MASK 0x2u
3936 #define USB_ISTAT_ERROR_SHIFT 1
3937 #define USB_ISTAT_SOFTOK_MASK 0x4u
3938 #define USB_ISTAT_SOFTOK_SHIFT 2
3939 #define USB_ISTAT_TOKDNE_MASK 0x8u
3940 #define USB_ISTAT_TOKDNE_SHIFT 3
3941 #define USB_ISTAT_SLEEP_MASK 0x10u
3942 #define USB_ISTAT_SLEEP_SHIFT 4
3943 #define USB_ISTAT_RESUME_MASK 0x20u
3944 #define USB_ISTAT_RESUME_SHIFT 5
3945 #define USB_ISTAT_ATTACH_MASK 0x40u
3946 #define USB_ISTAT_ATTACH_SHIFT 6
3947 #define USB_ISTAT_STALL_MASK 0x80u
3948 #define USB_ISTAT_STALL_SHIFT 7
3949 /* INTEN Bit Fields */
3950 #define USB_INTEN_USBRSTEN_MASK 0x1u
3951 #define USB_INTEN_USBRSTEN_SHIFT 0
3952 #define USB_INTEN_ERROREN_MASK 0x2u
3953 #define USB_INTEN_ERROREN_SHIFT 1
3954 #define USB_INTEN_SOFTOKEN_MASK 0x4u
3955 #define USB_INTEN_SOFTOKEN_SHIFT 2
3956 #define USB_INTEN_TOKDNEEN_MASK 0x8u
3957 #define USB_INTEN_TOKDNEEN_SHIFT 3
3958 #define USB_INTEN_SLEEPEN_MASK 0x10u
3959 #define USB_INTEN_SLEEPEN_SHIFT 4
3960 #define USB_INTEN_RESUMEEN_MASK 0x20u
3961 #define USB_INTEN_RESUMEEN_SHIFT 5
3962 #define USB_INTEN_ATTACHEN_MASK 0x40u
3963 #define USB_INTEN_ATTACHEN_SHIFT 6
3964 #define USB_INTEN_STALLEN_MASK 0x80u
3965 #define USB_INTEN_STALLEN_SHIFT 7
3966 /* ERRSTAT Bit Fields */
3967 #define USB_ERRSTAT_PIDERR_MASK 0x1u
3968 #define USB_ERRSTAT_PIDERR_SHIFT 0
3969 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
3970 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
3971 #define USB_ERRSTAT_CRC16_MASK 0x4u
3972 #define USB_ERRSTAT_CRC16_SHIFT 2
3973 #define USB_ERRSTAT_DFN8_MASK 0x8u
3974 #define USB_ERRSTAT_DFN8_SHIFT 3
3975 #define USB_ERRSTAT_BTOERR_MASK 0x10u
3976 #define USB_ERRSTAT_BTOERR_SHIFT 4
3977 #define USB_ERRSTAT_DMAERR_MASK 0x20u
3978 #define USB_ERRSTAT_DMAERR_SHIFT 5
3979 #define USB_ERRSTAT_BTSERR_MASK 0x80u
3980 #define USB_ERRSTAT_BTSERR_SHIFT 7
3981 /* ERREN Bit Fields */
3982 #define USB_ERREN_PIDERREN_MASK 0x1u
3983 #define USB_ERREN_PIDERREN_SHIFT 0
3984 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
3985 #define USB_ERREN_CRC5EOFEN_SHIFT 1
3986 #define USB_ERREN_CRC16EN_MASK 0x4u
3987 #define USB_ERREN_CRC16EN_SHIFT 2
3988 #define USB_ERREN_DFN8EN_MASK 0x8u
3989 #define USB_ERREN_DFN8EN_SHIFT 3
3990 #define USB_ERREN_BTOERREN_MASK 0x10u
3991 #define USB_ERREN_BTOERREN_SHIFT 4
3992 #define USB_ERREN_DMAERREN_MASK 0x20u
3993 #define USB_ERREN_DMAERREN_SHIFT 5
3994 #define USB_ERREN_BTSERREN_MASK 0x80u
3995 #define USB_ERREN_BTSERREN_SHIFT 7
3996 /* STAT Bit Fields */
3997 #define USB_STAT_ODD_MASK 0x4u
3998 #define USB_STAT_ODD_SHIFT 2
3999 #define USB_STAT_TX_MASK 0x8u
4000 #define USB_STAT_TX_SHIFT 3
4001 #define USB_STAT_ENDP_MASK 0xF0u
4002 #define USB_STAT_ENDP_SHIFT 4
4003 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
4004 /* CTL Bit Fields */
4005 #define USB_CTL_USBENSOFEN_MASK 0x1u
4006 #define USB_CTL_USBENSOFEN_SHIFT 0
4007 #define USB_CTL_ODDRST_MASK 0x2u
4008 #define USB_CTL_ODDRST_SHIFT 1
4009 #define USB_CTL_RESUME_MASK 0x4u
4010 #define USB_CTL_RESUME_SHIFT 2
4011 #define USB_CTL_HOSTMODEEN_MASK 0x8u
4012 #define USB_CTL_HOSTMODEEN_SHIFT 3
4013 #define USB_CTL_RESET_MASK 0x10u
4014 #define USB_CTL_RESET_SHIFT 4
4015 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
4016 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
4017 #define USB_CTL_SE0_MASK 0x40u
4018 #define USB_CTL_SE0_SHIFT 6
4019 #define USB_CTL_JSTATE_MASK 0x80u
4020 #define USB_CTL_JSTATE_SHIFT 7
4021 /* ADDR Bit Fields */
4022 #define USB_ADDR_ADDR_MASK 0x7Fu
4023 #define USB_ADDR_ADDR_SHIFT 0
4024 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
4025 #define USB_ADDR_LSEN_MASK 0x80u
4026 #define USB_ADDR_LSEN_SHIFT 7
4027 /* BDTPAGE1 Bit Fields */
4028 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
4029 #define USB_BDTPAGE1_BDTBA_SHIFT 1
4030 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
4031 /* FRMNUML Bit Fields */
4032 #define USB_FRMNUML_FRM_MASK 0xFFu
4033 #define USB_FRMNUML_FRM_SHIFT 0
4034 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
4035 /* FRMNUMH Bit Fields */
4036 #define USB_FRMNUMH_FRM_MASK 0x7u
4037 #define USB_FRMNUMH_FRM_SHIFT 0
4038 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
4039 /* TOKEN Bit Fields */
4040 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
4041 #define USB_TOKEN_TOKENENDPT_SHIFT 0
4042 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
4043 #define USB_TOKEN_TOKENPID_MASK 0xF0u
4044 #define USB_TOKEN_TOKENPID_SHIFT 4
4045 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
4046 /* SOFTHLD Bit Fields */
4047 #define USB_SOFTHLD_CNT_MASK 0xFFu
4048 #define USB_SOFTHLD_CNT_SHIFT 0
4049 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
4050 /* BDTPAGE2 Bit Fields */
4051 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
4052 #define USB_BDTPAGE2_BDTBA_SHIFT 0
4053 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
4054 /* BDTPAGE3 Bit Fields */
4055 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
4056 #define USB_BDTPAGE3_BDTBA_SHIFT 0
4057 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
4058 /* ENDPT Bit Fields */
4059 #define USB_ENDPT_EPHSHK_MASK 0x1u
4060 #define USB_ENDPT_EPHSHK_SHIFT 0
4061 #define USB_ENDPT_EPSTALL_MASK 0x2u
4062 #define USB_ENDPT_EPSTALL_SHIFT 1
4063 #define USB_ENDPT_EPTXEN_MASK 0x4u
4064 #define USB_ENDPT_EPTXEN_SHIFT 2
4065 #define USB_ENDPT_EPRXEN_MASK 0x8u
4066 #define USB_ENDPT_EPRXEN_SHIFT 3
4067 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
4068 #define USB_ENDPT_EPCTLDIS_SHIFT 4
4069 #define USB_ENDPT_RETRYDIS_MASK 0x40u
4070 #define USB_ENDPT_RETRYDIS_SHIFT 6
4071 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
4072 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
4073 /* USBCTRL Bit Fields */
4074 #define USB_USBCTRL_PDE_MASK 0x40u
4075 #define USB_USBCTRL_PDE_SHIFT 6
4076 #define USB_USBCTRL_SUSP_MASK 0x80u
4077 #define USB_USBCTRL_SUSP_SHIFT 7
4078 /* OBSERVE Bit Fields */
4079 #define USB_OBSERVE_DMPD_MASK 0x10u
4080 #define USB_OBSERVE_DMPD_SHIFT 4
4081 #define USB_OBSERVE_DPPD_MASK 0x40u
4082 #define USB_OBSERVE_DPPD_SHIFT 6
4083 #define USB_OBSERVE_DPPU_MASK 0x80u
4084 #define USB_OBSERVE_DPPU_SHIFT 7
4085 /* CONTROL Bit Fields */
4086 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
4087 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
4088 /* USBTRC0 Bit Fields */
4089 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
4090 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
4091 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
4092 #define USB_USBTRC0_SYNC_DET_SHIFT 1
4093 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
4094 #define USB_USBTRC0_USBRESMEN_SHIFT 5
4095 #define USB_USBTRC0_USBRESET_MASK 0x80u
4096 #define USB_USBTRC0_USBRESET_SHIFT 7
4097
4098 /**
4099 * @}
4100 */ /* end of group USB_Register_Masks */
4101
4102
4103 /* USB - Peripheral instance base addresses */
4104 /** Peripheral USB0 base address */
4105 #define USB0_BASE (0x40072000u)
4106 /** Peripheral USB0 base pointer */
4107 #define USB0 ((USB_Type *)USB0_BASE)
4108 /** Array initializer of USB peripheral base pointers */
4109 #define USB_BASES { USB0 }
4110
4111 /**
4112 * @}
4113 */ /* end of group USB_Peripheral_Access_Layer */
4114
4115
4116 /*
4117 ** End of section using anonymous unions
4118 */
4119
4120 #if defined(__ARMCC_VERSION)
4121 #pragma pop
4122 #elif defined(__CWCC__)
4123 #pragma pop
4124 #elif defined(__GNUC__)
4125 /* leave anonymous unions enabled */
4126 #elif defined(__IAR_SYSTEMS_ICC__)
4127 #pragma language=default
4128 #else
4129 #error Not supported compiler type
4130 #endif
4131
4132 /**
4133 * @}
4134 */ /* end of group Peripheral_access_layer */
4135
4136
4137 /* ----------------------------------------------------------------------------
4138 -- Backward Compatibility
4139 ---------------------------------------------------------------------------- */
4140
4141 /**
4142 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
4143 * @{
4144 */
4145
4146 /* No backward compatibility issues. */
4147
4148 /**
4149 * @}
4150 */ /* end of group Backward_Compatibility_Symbols */
4151
4152
4153 #endif /* #if !defined(MKL25Z4_H_) */
4154
4155 /* MKL25Z4.h, eof. */
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