2 ** ###################################################################
3 ** Processors: MKL43Z256VLH4
10 ** Compilers: Keil ARM C/C++ Compiler
11 ** Freescale C/C++ for Embedded ARM
13 ** GNU C Compiler - CodeSourcery Sourcery G++
14 ** IAR ANSI C/C++ Compiler for ARM
16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
17 ** Version: rev. 1.4, 2014-09-01
21 ** Provides a system configuration function and a global variable that
22 ** contains the system frequency. It configures the device and initializes
23 ** the oscillator (PLL) that is part of the microcontroller device.
25 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
26 ** All rights reserved.
28 ** Redistribution and use in source and binary forms, with or without modification,
29 ** are permitted provided that the following conditions are met:
31 ** o Redistributions of source code must retain the above copyright notice, this list
32 ** of conditions and the following disclaimer.
34 ** o Redistributions in binary form must reproduce the above copyright notice, this
35 ** list of conditions and the following disclaimer in the documentation and/or
36 ** other materials provided with the distribution.
38 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
39 ** contributors may be used to endorse or promote products derived from this
40 ** software without specific prior written permission.
42 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
43 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
44 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
45 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
46 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
48 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
49 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
51 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 ** http: www.freescale.com
54 ** mail: support@freescale.com
57 ** - rev. 1.0 (2014-03-27)
59 ** - rev. 1.1 (2014-05-26)
60 ** I2S registers TCR2/RCR2 and others were changed.
61 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
62 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
63 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
64 ** Clock configuration for high range external oscillator has been added.
65 ** RFSYS module access has been added.
66 ** - rev. 1.2 (2014-07-10)
67 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
68 ** UART0 - UART0 module renamed to UART2.
69 ** I2S - removed MDR register.
70 ** - rev. 1.3 (2014-08-21)
71 ** UART2 - Removed ED register.
72 ** UART2 - Removed MODEM register.
73 ** UART2 - Removed IR register.
74 ** UART2 - Removed PFIFO register.
75 ** UART2 - Removed CFIFO register.
76 ** UART2 - Removed SFIFO register.
77 ** UART2 - Removed TWFIFO register.
78 ** UART2 - Removed TCFIFO register.
79 ** UART2 - Removed RWFIFO register.
80 ** UART2 - Removed RCFIFO register.
81 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
82 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
83 ** SIM - Removed bitfield DIEID in SDID register.
84 ** - rev. 1.4 (2014-09-01)
85 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
86 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
88 ** ###################################################################
95 * @brief Device specific configuration file for MKL43Z4 (implementation file)
97 * Provides a system configuration function and a global variable that contains
98 * the system frequency. It configures the device and initializes the oscillator
99 * (PLL) that is part of the microcontroller device.
107 /* ----------------------------------------------------------------------------
109 ---------------------------------------------------------------------------- */
111 uint32_t SystemCoreClock
= DEFAULT_SYSTEM_CLOCK
;
113 /* ----------------------------------------------------------------------------
115 ---------------------------------------------------------------------------- */
117 void SystemInit (void) {
120 if(PMC
->REGSC
& PMC_REGSC_ACKISO_MASK
) {
121 PMC
->REGSC
|= PMC_REGSC_ACKISO_MASK
; /* VLLSx recovery */
126 /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
127 SIM
->COPC
= (uint32_t)0x00u
;
128 #endif /* (DISABLE_WDOG) */
130 /* Power mode protection initialization */
131 #ifdef SMC_PMPROT_VALUE
132 SMC
->PMPROT
= SMC_PMPROT_VALUE
;
135 /* System clock initialization */
137 /* Set system prescalers and clock sources */
138 SIM
->CLKDIV1
= SYSTEM_SIM_CLKDIV1_VALUE
; /* Set system prescalers */
139 SIM
->SOPT1
= ((SIM
->SOPT1
) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK
))) | ((SYSTEM_SIM_SOPT1_VALUE
) & (SIM_SOPT1_OSC32KSEL_MASK
)); /* Set 32 kHz clock source (ERCLK32K) */
140 #define SOPT2_WRITE_MASK ((SIM_SOPT2_USBSRC_MASK) | (SIM_SOPT2_TPMSRC_MASK) | (SIM_SOPT2_LPUART0SRC_MASK) | (SIM_SOPT2_LPUART1SRC_MASK)) /* define mask of written bits. */
141 SIM
->SOPT2
= ((SIM
->SOPT2
) & (uint32_t)(~SOPT2_WRITE_MASK
)) | ((SYSTEM_SIM_SOPT2_VALUE
) & SOPT2_WRITE_MASK
); /* Selects the clock source for the TPM counter clock. */
142 #if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC)
143 /* Set MCG and OSC0 */
144 #if (((OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U)
145 /* SIM_SCGC5: PORTA=1 */
146 SIM_SCGC5
|= SIM_SCGC5_PORTA_MASK
;
147 /* PORTA_PCR3: ISF=0,MUX=0 */
148 PORTA_PCR18
&= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK
| PORT_PCR_MUX(0x07)));
149 if (((MCG_C2_VALUE
) & MCG_C2_EREFS0_MASK
) != 0x00U
) {
150 PORTA_PCR19
&= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK
| PORT_PCR_MUX(0x07)));
153 MCG
->SC
= MCG_SC_VALUE
; /* Set SC (internal reference clock divider) */
154 MCG
->MC
= MCG_MC_VALUE
; /* Set MC (high-frequency IRC enable, second LIRC divider) */
155 MCG
->C1
= MCG_C1_VALUE
; /* Set C1 (clock source selection, int. reference enable etc.) */
156 MCG
->C2
= MCG_C2_VALUE
; /* Set C2 (ext. and int. reference clock selection) */
157 OSC0
->CR
= OSC0_CR_VALUE
; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
160 /* Set MCG and OSC0 */
161 /* SIM_SCGC5: PORTA=1 */
162 SIM_SCGC5
|= SIM_SCGC5_PORTA_MASK
;
163 /* PORTA_PCR3: ISF=0,MUX=0 */
164 PORTA_PCR18
&= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK
| PORT_PCR_MUX(0x07)));
165 if (((MCG_C2_VALUE
) & MCG_C2_EREFS0_MASK
) != 0x00U
) {
166 PORTA_PCR19
&= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK
| PORT_PCR_MUX(0x07)));
168 MCG
->SC
= MCG_SC_VALUE
; /* Set SC (internal reference clock divider) */
169 MCG
->C2
= MCG_C2_VALUE
; /* Set C2 (ext. and int. reference clock selection) */
170 OSC0
->CR
= OSC0_CR_VALUE
; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
171 MCG
->C1
= MCG_C1_VALUE
; /* Set C1 (clock source selection, int. reference enable etc.) */
172 MCG
->MC
= MCG_MC_VALUE
; /* Set MC (high-frequency IRC enable, second LIRC divider) */
173 if (((MCG_C2_VALUE
) & MCG_C2_EREFS0_MASK
) != 0U) {
174 while((MCG
->S
& MCG_S_OSCINIT0_MASK
) == 0x00U
) { /* Check that the oscillator is running */
177 #endif /* MCG_MODE */
179 /* Common for all MCG modes */
181 #if (MCG_MODE == MCG_MODE_HIRC)
182 while((MCG
->S
& MCG_S_CLKST_MASK
) != 0x00U
) { /* Wait until high internal reference clock is selected as MCG_Lite output */
184 #elif (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M)
185 while((MCG
->S
& MCG_S_CLKST_MASK
) != 0x04U
) { /* Wait until low internal reference clock is selected as MCG_Lite output */
187 #elif (MCG_MODE == MCG_MODE_EXT)
188 while((MCG
->S
& MCG_S_CLKST_MASK
) != 0x08U
) { /* Wait until external reference clock is selected as MCG_Lite output */
191 if (((SMC_PMCTRL_VALUE
) & SMC_PMCTRL_RUNM_MASK
) == SMC_PMCTRL_RUNM(0x02U
)) {
192 SMC
->PMCTRL
= (uint8_t)((SMC_PMCTRL_VALUE
) & (SMC_PMCTRL_RUNM_MASK
)); /* Enable VLPR mode */
193 while(SMC
->PMSTAT
!= 0x04U
) { /* Wait until the system is in VLPR mode */
199 /* ----------------------------------------------------------------------------
200 -- SystemCoreClockUpdate()
201 ---------------------------------------------------------------------------- */
203 void SystemCoreClockUpdate (void) {
205 uint32_t MCGOUTClock
; /* Variable to store output clock frequency of the MCG module */
208 if ((MCG
->S
& MCG_S_CLKST_MASK
) == 0x00U
) {
209 /* High internal reference clock is selected */
210 MCGOUTClock
= CPU_INT_FAST_CLK_HZ
; /* Fast internal reference clock selected */
211 } else if ((MCG
->S
& MCG_S_CLKST_MASK
) == 0x04U
) {
212 /* Internal reference clock is selected */
213 Divider
= (uint16_t)(0x01LU
<< ((MCG
->SC
& MCG_SC_FCRDIV_MASK
) >> MCG_SC_FCRDIV_SHIFT
));
214 MCGOUTClock
= (uint32_t) (CPU_INT_SLOW_CLK_HZ
/ Divider
); /* Slow internal reference clock 8MHz selected */
215 } else if ((MCG
->S
& MCG_S_CLKST_MASK
) == 0x08U
) {
216 /* External reference clock is selected */
217 MCGOUTClock
= CPU_XTAL_CLK_HZ
;
221 } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
222 SystemCoreClock
= (MCGOUTClock
/ (0x01U
+ ((SIM
->CLKDIV1
& SIM_CLKDIV1_OUTDIV1_MASK
) >> SIM_CLKDIV1_OUTDIV1_SHIFT
)));