tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h

   1 /*******************************************************************************
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   5  * copy of this software and associated documentation files (the "Software"),
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  33
  34 #ifndef _MXC_ADC_REGS_H
  35 #define _MXC_ADC_REGS_H
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  adc_regs.h
  45  * @addtogroup adc ADC
  46  * @{
  47  */
  48
  49 /**
  50  * @brief Defines ADC Modes.
  51  */
  52 typedef enum {
  53     /** Single Mode Full Rate */
  54     MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
  55     /** Single Mode Low Power */
  56     MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
  57     /** Continuous Mode Full Rate */
  58     MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
  59     /** Continuous Mode Low Power */
  60     MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
  61     /** Single Mode Full Rate with Scan Enabled */
  62     MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
  63     /** Single Mode Low Power with Scan Enabled */
  64     MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
  65     /** Continuous Mode Full Rate with Scan Enabled */
  66     MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
  67     /** Continuous Mode Low Power with Scan Enabled */
  68     MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
  69 } mxc_adc_mode_t;
  70
  71 /**
  72  * @brief Defines ADC Range Control.
  73  */
  74 typedef enum {
  75     /** Bi-polar Operation (-Vref/2 -> Vref/2) */
  76     MXC_E_ADC_RANGE_HALF = 0,
  77     /** Bi-polar Operation (-Vref -> Vref) */
  78     MXC_E_ADC_RANGE_FULL
  79 } mxc_adc_range_t;
  80
  81 /**
  82  * @brief Defines ADC Bipolar operation.
  83  */
  84 typedef enum {
  85     /** Uni-polar operation (0 -> Vref) */
  86     MXC_E_ADC_BI_POL_UNIPOLAR = 0,
  87     /** Bi-polar operation see ADC Range Control */
  88     MXC_E_ADC_BI_POL_BIPOLAR
  89 } mxc_adc_bi_pol_t;
  90
  91 /**
  92  * @brief Defines Decimation Filter Modes.
  93  */
  94 typedef enum {
  95     /** Decimation Filter ByPassed */
  96     MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
  97     /** Output Average Only*/
  98     MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
  99     /** Output Average and Raw Data (Test Mode Only) */
 100     MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
 101 } mxc_adc_avg_mode_t;
 102
 103 /**
 104  * @brief Defines ADC StartMode Modes.
 105  */
 106 typedef enum {
 107     /** StarMode via Software */
 108     MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
 109     /** StarMode via PulseTrain */
 110     MXC_E_ADC_STRT_MODE_PULSETRAIN
 111 } mxc_adc_strt_mode_t;
 112
 113 /**
 114  * @brief Defines Mux Channel Select for the Positive Input to the ADC.
 115  */
 116 typedef enum {
 117     /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8-  */
 118     MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
 119     /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9-  */
 120     MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
 121     /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
 122     MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
 123     /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
 124     MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
 125     /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
 126     MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
 127     /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13-  */
 128     MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
 129     /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14-  */
 130     MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
 131     /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15-  */
 132     MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
 133     /** Single Mode Input AIN8+ */
 134     MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
 135     /** Single Mode Input AIN9+ */
 136     MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
 137     /** Single Mode Input AIN10+ */
 138     MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
 139     /** Single Mode Input AIN11+ */
 140     MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
 141     /** Single Mode Input AIN12+ */
 142     MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
 143     /** Single Mode Input AIN13+ */
 144     MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
 145     /** Single Mode Input AIN14+ */
 146     MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
 147     /** Single Mode Input AIN15+ */
 148     MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
 149     /** Positive Input VSSADC */
 150     MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
 151     /** Positive Input TMON_R */
 152     MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
 153     /** Positive Input VDDA/4 */
 154     MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
 155     /** Positive Input PWRMAN_TST */
 156     MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
 157     /** Positive Input Ain0Div */
 158     MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
 159     /** Positive Input OpAmp OUTA */
 160     MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
 161     /** Positive Input OpAmp OUTB */
 162     MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
 163     /** Positive Input OpAmp OUTC */
 164     MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
 165     /** Positive Input OpAmp OUTD */
 166     MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
 167     /** Positive INA+ */
 168     MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
 169     /** Positive SNO_or */
 170     MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
 171     /** Positive SCM_or */
 172     MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
 173     /** Positive TPROBE_sense */
 174     MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
 175     /** Positive VREFDAC */
 176     MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
 177     /** Positive VREFADJ */
 178     MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
 179     /** Positive Vdd3xtal */
 180     MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
 181 } mxc_adc_pga_mux_ch_sel_t;
 182
 183 /**
 184  * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
 185  */
 186 typedef enum {
 187     /** Differential Mode Disabled */
 188     MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
 189     /** Differential Mode Enabled */
 190     MXC_E_ADC_PGA_MUX_DIFF_ENABLE
 191 } mxc_adc_pga_mux_diff_t;
 192
 193 /**
 194  * @brief Defines the PGA Gain Options.
 195  */
 196 typedef enum {
 197     /** PGA Gain = 1 */
 198     MXC_E_ADC_PGA_GAIN_1 = 0,
 199     /** PGA Gain = 2 */
 200     MXC_E_ADC_PGA_GAIN_2,
 201     /** PGA Gain = 4 */
 202     MXC_E_ADC_PGA_GAIN_4,
 203     /** PGA Gain = 8 */
 204     MXC_E_ADC_PGA_GAIN_8,
 205 } mxc_adc_pga_gain_t;
 206
 207 /**
 208  * @brief Defines the Switch Control Mode.
 209  */
 210 typedef enum {
 211     /** Switch Control Mode = Software */
 212     MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
 213     /** Switch Control Mode = Pulse Train */
 214     MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
 215 } mxc_adc_spst_sw_ctrl_t;
 216
 217 /**
 218  * @brief Defines the number of channels to scan when Scan Mode is enabled.
 219  */
 220 typedef enum {
 221     /** Number of Channels to Scan = 1 */
 222     MXC_E_ADC_SCAN_CNT_1 = 0,
 223     /** Number of Channels to Scan = 2 */
 224     MXC_E_ADC_SCAN_CNT_2,
 225     /** Number of Channels to Scan = 3 */
 226     MXC_E_ADC_SCAN_CNT_3,
 227     /** Number of Channels to Scan = 4 */
 228     MXC_E_ADC_SCAN_CNT_4,
 229     /** Number of Channels to Scan = 5 */
 230     MXC_E_ADC_SCAN_CNT_5,
 231     /** Number of Channels to Scan = 6 */
 232     MXC_E_ADC_SCAN_CNT_6,
 233     /** Number of Channels to Scan = 7 */
 234     MXC_E_ADC_SCAN_CNT_7,
 235     /** Number of Channels to Scan = 8 */
 236     MXC_E_ADC_SCAN_CNT_8,
 237 } mxc_adc_scan_cnt_t;
 238
 239 /*                                              Offset   Register Description
 240                                                 ======   =================================================== */
 241 typedef struct {
 242     __IO uint32_t ctrl0;                    /*  0x0000   ADC Control Register 0                              */
 243     __IO uint32_t pga_ctrl;                 /*  0x0004   PGA Control Register                                */
 244     __IO uint32_t tg_ctrl0;                 /*  0x0008   ADC Timing Generator Control 0                      */
 245     __IO uint32_t tg_ctrl1;                 /*  0x000C   ADC Timing Generator Control 1                      */
 246     __IO uint32_t limit;                    /*  0x0010   ADC Limit Settings                                  */
 247     __IO uint32_t intr;                     /*  0x0014   ADC Interrupt Flags and Enable/Disable Controls     */
 248     __IO uint32_t out;                      /*  0x0018   ADC Output Register                                 */
 249 } mxc_adc_regs_t;
 250
 251 /*                                              Offset   Register Description
 252                                                 ======   =================================================== */
 253 typedef struct {
 254     __IO uint32_t ctrl1;                    /*  0x0000   ADC Control Register 1                              */
 255     __IO uint32_t scan1;                    /*  0x0004   ADC Auto-Scan Settings 1                            */
 256     __IO uint32_t scan2;                    /*  0x0008   ADC Auto-Scan Settings 2                            */
 257     __IO uint32_t ro_cal0;                  /*  0x000C   ADC Ring Osc Calibration 0                          */
 258     __IO uint32_t ro_cal1;                  /*  0x0010   ADC Ring Osc Calibration 1                          */
 259 } mxc_adccfg_regs_t;
 260
 261 typedef struct {
 262     __IO uint16_t data;                     /*  0x0000   Read to pull sample data from ADC FIFO              */
 263 } mxc_adc_fifo_regs_t;
 264
 265 /*
 266    Register offsets for module ADC, ADCCFG, ADC_FIFO
 267 */
 268 #define MXC_R_ADC_OFFS_CTRL0                      ((uint32_t)0x00000000UL)
 269 #define MXC_R_ADC_OFFS_PGA_CTRL                   ((uint32_t)0x00000004UL)
 270 #define MXC_R_ADC_OFFS_TG_CTRL0                   ((uint32_t)0x00000008UL)
 271 #define MXC_R_ADC_OFFS_TG_CTRL1                   ((uint32_t)0x0000000CUL)
 272 #define MXC_R_ADC_OFFS_LIMIT                      ((uint32_t)0x00000010UL)
 273 #define MXC_R_ADC_OFFS_INTR                       ((uint32_t)0x00000014UL)
 274 #define MXC_R_ADC_OFFS_OUT                        ((uint32_t)0x00000018UL)
 275
 276 #define MXC_R_ADCCFG_OFFS_CTRL1                   ((uint32_t)0x00000000UL)
 277 #define MXC_R_ADCCFG_OFFS_SCAN1                   ((uint32_t)0x00000004UL)
 278 #define MXC_R_ADCCFG_OFFS_SCAN2                   ((uint32_t)0x00000008UL)
 279 #define MXC_R_ADCCFG_OFFS_RO_CAL0                 ((uint32_t)0x0000000CUL)
 280 #define MXC_R_ADCCFG_OFFS_RO_CAL1                 ((uint32_t)0x00000010UL)
 281 #define MXC_R_ADC_FIFO_OFFS_DATA                  ((uint32_t)0x00000000UL)
 282
 283 /*
 284    Field positions and masks for module ADC.
 285 */
 286 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS                    0
 287 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT                        ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
 288 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS                   5
 289 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
 290 #define MXC_F_ADC_CTRL0_ADC_RANGE_POS                       6
 291 #define MXC_F_ADC_CTRL0_ADC_RANGE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
 292 #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS                      7
 293 #define MXC_F_ADC_CTRL0_ADC_BI_POL                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
 294 #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS                      8
 295 #define MXC_F_ADC_CTRL0_ADC_DV_REG                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
 296 #define MXC_F_ADC_CTRL0_ADC_DV_POS                          9
 297 #define MXC_F_ADC_CTRL0_ADC_DV                              ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
 298 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS                   10
 299 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
 300 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS                     11
 301 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
 302 #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS                      12
 303 #define MXC_F_ADC_CTRL0_ADC_CLK_EN                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
 304 #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS                     13
 305 #define MXC_F_ADC_CTRL0_CPU_ADC_RST                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
 306 #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS                   14
 307 #define MXC_F_ADC_CTRL0_CPU_ADC_START                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
 308 #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS                      15
 309 #define MXC_F_ADC_CTRL0_CPU_ADC_EN                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
 310 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS                   18
 311 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
 312 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS                  19
 313 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
 314 #define MXC_F_ADC_CTRL0_AVG_MODE_POS                        20
 315 #define MXC_F_ADC_CTRL0_AVG_MODE                            ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
 316 #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS                   22
 317 #define MXC_F_ADC_CTRL0_CPU_DAC_START                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
 318 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS                    24
 319 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE                        ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
 320 #define MXC_F_ADC_CTRL0_ADC_MODE_POS                        28
 321 #define MXC_F_ADC_CTRL0_ADC_MODE                            ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
 322
 323 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS                     0
 324 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN                         ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
 325 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS           2
 326 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN               ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
 327 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS                  3
 328 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST                      ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
 329 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS            4
 330 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY                ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
 331 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS                  5
 332 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK                      ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
 333 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS               6
 334 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS                   ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
 335 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS                 8
 336 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT                     ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
 337 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS                   13
 338 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN                       ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
 339 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS                     14
 340 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF                         ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
 341 #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS                     15
 342 #define MXC_F_ADC_PGA_CTRL_MUX_MODE                         ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
 343 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS              20
 344 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT                  ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
 345 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS                   24
 346 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL                       ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
 347
 348 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS                  0
 349 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT                      ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
 350 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS                 16
 351 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT                     ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
 352
 353 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS                  0
 354 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
 355 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS                  4
 356 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
 357 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS                 8
 358 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT                     ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
 359 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS                  12
 360 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
 361 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS                  16
 362 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT                      ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
 363
 364 #define MXC_F_ADC_LIMIT_LO_LIMIT_POS                        0
 365 #define MXC_F_ADC_LIMIT_LO_LIMIT                            ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
 366 #define MXC_F_ADC_LIMIT_HI_LIMIT_POS                        16
 367 #define MXC_F_ADC_LIMIT_HI_LIMIT                            ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
 368
 369 #define MXC_F_ADC_INTR_FIFO_AF_POS                          6
 370 #define MXC_F_ADC_INTR_FIFO_AF                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
 371 #define MXC_F_ADC_INTR_OUT_RNG_IF_POS                       7
 372 #define MXC_F_ADC_INTR_OUT_RNG_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
 373 #define MXC_F_ADC_INTR_HI_RNG_IF_POS                        8
 374 #define MXC_F_ADC_INTR_HI_RNG_IF                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
 375 #define MXC_F_ADC_INTR_LO_RNG_IF_POS                        9
 376 #define MXC_F_ADC_INTR_LO_RNG_IF                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
 377 #define MXC_F_ADC_INTR_DONE_IF_POS                          10
 378 #define MXC_F_ADC_INTR_DONE_IF                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
 379 #define MXC_F_ADC_INTR_FIFO_UF_IF_POS                       11
 380 #define MXC_F_ADC_INTR_FIFO_UF_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
 381 #define MXC_F_ADC_INTR_FIFO_OF_IF_POS                       12
 382 #define MXC_F_ADC_INTR_FIFO_OF_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
 383 #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS                       13
 384 #define MXC_F_ADC_INTR_FIFO_3Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
 385 #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS                       14
 386 #define MXC_F_ADC_INTR_FIFO_2Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
 387 #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS                       15
 388 #define MXC_F_ADC_INTR_FIFO_1Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
 389 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS                  16
 390 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
 391 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS                  17
 392 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
 393 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS                  18
 394 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
 395 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS                  19
 396 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
 397 #define MXC_F_ADC_INTR_OUT_RNG_IE_POS                       23
 398 #define MXC_F_ADC_INTR_OUT_RNG_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
 399 #define MXC_F_ADC_INTR_HI_RNG_IE_POS                        24
 400 #define MXC_F_ADC_INTR_HI_RNG_IE                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
 401 #define MXC_F_ADC_INTR_LO_RNG_IE_POS                        25
 402 #define MXC_F_ADC_INTR_LO_RNG_IE                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
 403 #define MXC_F_ADC_INTR_DONE_IE_POS                          26
 404 #define MXC_F_ADC_INTR_DONE_IE                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
 405 #define MXC_F_ADC_INTR_FIFO_UF_IE_POS                       27
 406 #define MXC_F_ADC_INTR_FIFO_UF_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
 407 #define MXC_F_ADC_INTR_FIFO_OF_IE_POS                       28
 408 #define MXC_F_ADC_INTR_FIFO_OF_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
 409 #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS                       29
 410 #define MXC_F_ADC_INTR_FIFO_3Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
 411 #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS                       30
 412 #define MXC_F_ADC_INTR_FIFO_2Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
 413 #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS                       31
 414 #define MXC_F_ADC_INTR_FIFO_1Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
 415
 416 #define MXC_F_ADC_OUT_DATA_REG_POS                          0
 417 #define MXC_F_ADC_OUT_DATA_REG                              ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
 418
 419 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS                    16
 420 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT                        ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
 421
 422 #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS                       0
 423 #define MXC_F_ADC_SCAN1_ADC_SCAN0                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
 424 #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS                       8
 425 #define MXC_F_ADC_SCAN1_ADC_SCAN1                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
 426 #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS                       16
 427 #define MXC_F_ADC_SCAN1_ADC_SCAN2                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
 428 #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS                       24
 429 #define MXC_F_ADC_SCAN1_ADC_SCAN3                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
 430
 431 #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS                       0
 432 #define MXC_F_ADC_SCAN2_ADC_SCAN4                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
 433 #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS                       8
 434 #define MXC_F_ADC_SCAN2_ADC_SCAN5                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
 435 #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS                       16
 436 #define MXC_F_ADC_SCAN2_ADC_SCAN6                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
 437 #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS                       24
 438 #define MXC_F_ADC_SCAN2_ADC_SCAN7                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
 439
 440 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS                     0
 441 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN                         ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
 442 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS                    1
 443 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN                        ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
 444 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS                   2
 445 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD                       ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
 446 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS                        8
 447 #define MXC_F_ADC_RO_CAL0_TRM_MU                            ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
 448 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS                        23
 449 #define MXC_F_ADC_RO_CAL0_RO_TRM                            ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
 450
 451 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS                      0
 452 #define MXC_F_ADC_RO_CAL1_TRM_INIT                          ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
 453 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS                       10
 454 #define MXC_F_ADC_RO_CAL1_TRM_MIN                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
 455 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS                       20
 456 #define MXC_F_ADC_RO_CAL1_TRM_MAX                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
 457
 458 #ifdef __cplusplus
 459 }
 460 #endif
 461
 462 /**
 463  * @}
 464  */
 465
 466 #endif /* _MXC_ADC_REGS_H */