tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h

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  33
  34 #ifndef _MXC_PMU_REGS_H_
  35 #define _MXC_PMU_REGS_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  pmu_regs.h
  45  * @addtogroup pmu PMU
  46  * @{
  47  */
  48
  49 /*                                     Offset   Register Description
  50                                        ======   ======================================================== */
  51 typedef struct {
  52     __IO uint32_t dscadr;          /*  0x0000   Starting Descriptor Address                              */
  53     __IO uint32_t cfg;             /*  0x0004   Channel Configuration                                    */
  54     __IO uint32_t loop;            /*  0x0008   Channel Loop Counters                                    */
  55     __IO uint32_t op;              /*  0x000C   Current Descriptor DWORD 0 (OP)                          */
  56     __IO uint32_t dsc1;            /*  0x0010   Current Descriptor DWORD 1                               */
  57     __IO uint32_t dsc2;            /*  0x0014   Current Descriptor DWORD 2                               */
  58     __IO uint32_t dsc3;            /*  0x0018   Current Descriptor DWORD 3                               */
  59     __IO uint32_t dsc4;            /*  0x001C   Current Descriptor DWORD 4                               */
  60 } mxc_pmu_regs_t;
  61
  62 /*
  63    Register offsets for module PMU.
  64 */
  65 #define MXC_R_PMU_OFFS_DSCADR                     ((uint32_t)0x00000000UL)
  66 #define MXC_R_PMU_OFFS_CFG                        ((uint32_t)0x00000004UL)
  67 #define MXC_R_PMU_OFFS_LOOP                       ((uint32_t)0x00000008UL)
  68 #define MXC_R_PMU_OFFS_OP                         ((uint32_t)0x0000000CUL)
  69 #define MXC_R_PMU_OFFS_DSC1                       ((uint32_t)0x00000010UL)
  70 #define MXC_R_PMU_OFFS_DSC2                       ((uint32_t)0x00000014UL)
  71 #define MXC_R_PMU_OFFS_DSC3                       ((uint32_t)0x00000018UL)
  72 #define MXC_R_PMU_OFFS_DSC4                       ((uint32_t)0x0000001CUL)
  73
  74 /*
  75    Field positions and masks for module PMU.
  76 */
  77 #define MXC_F_PMU_CFG_ENABLE_POS                            0
  78 #define MXC_F_PMU_CFG_ENABLE                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
  79 #define MXC_F_PMU_CFG_LL_STOPPED_POS                        2
  80 #define MXC_F_PMU_CFG_LL_STOPPED                            ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
  81 #define MXC_F_PMU_CFG_MANUAL_POS                            3
  82 #define MXC_F_PMU_CFG_MANUAL                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
  83 #define MXC_F_PMU_CFG_BUS_ERROR_POS                         4
  84 #define MXC_F_PMU_CFG_BUS_ERROR                             ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
  85 #define MXC_F_PMU_CFG_TO_STAT_POS                           6
  86 #define MXC_F_PMU_CFG_TO_STAT                               ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
  87 #define MXC_F_PMU_CFG_TO_SEL_POS                            11
  88 #define MXC_F_PMU_CFG_TO_SEL                                ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
  89 #define MXC_F_PMU_CFG_PS_SEL_POS                            14
  90 #define MXC_F_PMU_CFG_PS_SEL                                ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
  91 #define MXC_F_PMU_CFG_INTERRUPT_POS                         16
  92 #define MXC_F_PMU_CFG_INTERRUPT                             ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
  93 #define MXC_F_PMU_CFG_INT_EN_POS                            17
  94 #define MXC_F_PMU_CFG_INT_EN                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
  95 #define MXC_F_PMU_CFG_BURST_SIZE_POS                        24
  96 #define MXC_F_PMU_CFG_BURST_SIZE                            ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
  97
  98 #define MXC_F_PMU_LOOP_COUNTER_0_POS                        0
  99 #define MXC_F_PMU_LOOP_COUNTER_0                            ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
 100 #define MXC_F_PMU_LOOP_COUNTER_1_POS                        16
 101 #define MXC_F_PMU_LOOP_COUNTER_1                            ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
 102
 103 #ifdef __cplusplus
 104 }
 105 #endif
 106
 107 /**
 108 * @}
 109 */
 110
 111 #endif   /* _MXC_PMU_REGS_H_ */