tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h

   1 /*******************************************************************************
   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
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  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  26  * The mere transfer of this software does not imply any licenses
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  33
  34 #ifndef _MXC_RTC_REGS_H
  35 #define _MXC_RTC_REGS_H
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  rtc_regs.h
  45  * @addtogroup rtc RTCTMR
  46  * @{
  47  */
  48
  49 /**
  50  * @brief Defines clock divider for 4096Hz input clock.
  51  */
  52 typedef enum {
  53     /** (4kHz) divide input clock by 2^0 = 1 */
  54     MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
  55     /** (2kHz) divide input clock by 2^1 = 2 */
  56     MXC_E_RTC_PRESCALE_DIV_2_1,
  57     /** (1kHz) divide input clock by 2^2 = 4 */
  58     MXC_E_RTC_PRESCALE_DIV_2_2,
  59     /** (512Hz) divide input clock by 2^3 = 8 */
  60     MXC_E_RTC_PRESCALE_DIV_2_3,
  61     /** (256Hz) divide input clock by 2^4 = 16 */
  62     MXC_E_RTC_PRESCALE_DIV_2_4,
  63     /** (128Hz) divide input clock by 2^5 = 32 */
  64     MXC_E_RTC_PRESCALE_DIV_2_5,
  65     /** (64Hz) divide input clock by 2^6 = 64 */
  66     MXC_E_RTC_PRESCALE_DIV_2_6,
  67     /** (32Hz) divide input clock by 2^7 = 128 */
  68     MXC_E_RTC_PRESCALE_DIV_2_7,
  69     /** (16Hz) divide input clock by 2^8 = 256 */
  70     MXC_E_RTC_PRESCALE_DIV_2_8,
  71     /** (8Hz) divide input clock by 2^9 = 512 */
  72     MXC_E_RTC_PRESCALE_DIV_2_9,
  73     /** (4Hz) divide input clock by 2^10 = 1024 */
  74     MXC_E_RTC_PRESCALE_DIV_2_10,
  75     /** (2Hz) divide input clock by 2^11 = 2048 */
  76     MXC_E_RTC_PRESCALE_DIV_2_11,
  77     /** (1Hz) divide input clock by 2^12 = 4096 */
  78     MXC_E_RTC_PRESCALE_DIV_2_12,
  79 } mxc_rtc_prescale_t;
  80
  81 /*                                          Offset   Register Description
  82                                             ======   ========================================= */
  83 typedef struct {
  84     __IO uint32_t ctrl;                 /*  0x0000   RTC Timer Control                         */
  85     __IO uint32_t timer;                /*  0x0004   RTC Timer Count Value                     */
  86     __IO uint32_t comp[2];              /*  0x0008   RTC Alarm (0..1) Compare Registers        */
  87     __IO uint32_t flags;                /*  0x0010   CPU Interrupt and RTC Domain Flags        */
  88     __I uint32_t rsv0014;               /*  0x0014                                             */
  89     __IO uint32_t inten;                /*  0x0018   Interrupt Enable Controls                 */
  90     __IO uint32_t prescale;             /*  0x001C   RTC Timer Prescale Setting                */
  91     __I uint32_t rsv0020;               /*  0x0020                                             */
  92     __IO uint32_t prescale_mask;        /*  0x0024   RTC Timer Prescale Compare Mask           */
  93     __IO uint32_t trim_ctrl;            /*  0x0028   RTC Timer Trim Controls                   */
  94     __IO uint32_t trim_value;           /*  0x002C   RTC Timer Trim Adjustment Interval        */
  95 } mxc_rtctmr_regs_t;
  96
  97 /*
  98    Register offsets for module RTCTMR.
  99 */
 100 #define MXC_R_RTCTMR_OFFS_CTRL                    ((uint32_t)0x00000000UL)
 101 #define MXC_R_RTCTMR_OFFS_TIMER                   ((uint32_t)0x00000004UL)
 102 #define MXC_R_RTCTMR_OFFS_COMP_0                  ((uint32_t)0x00000008UL)
 103 #define MXC_R_RTCTMR_OFFS_COMP_1                  ((uint32_t)0x0000000CUL)
 104 #define MXC_R_RTCTMR_OFFS_FLAGS                   ((uint32_t)0x00000010UL)
 105 #define MXC_R_RTCTMR_OFFS_INTEN                   ((uint32_t)0x00000018UL)
 106 #define MXC_R_RTCTMR_OFFS_PRESCALE                ((uint32_t)0x0000001CUL)
 107 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK           ((uint32_t)0x00000024UL)
 108 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL               ((uint32_t)0x00000028UL)
 109 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE              ((uint32_t)0x0000002CUL)
 110
 111 /*
 112    Field positions and masks for module RTCTMR.
 113 */
 114 #define MXC_F_RTC_CTRL_ENABLE_POS                           0
 115 #define MXC_F_RTC_CTRL_ENABLE                               ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
 116 #define MXC_F_RTC_CTRL_CLEAR_POS                            1
 117 #define MXC_F_RTC_CTRL_CLEAR                                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
 118 #define MXC_F_RTC_CTRL_PENDING_POS                          2
 119 #define MXC_F_RTC_CTRL_PENDING                              ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
 120 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS                  3
 121 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS                      ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
 122 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS                   4
 123 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST                       ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
 124 #define MXC_F_RTC_CTRL_EN_ACTIVE_POS                        16
 125 #define MXC_F_RTC_CTRL_EN_ACTIVE                            ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
 126 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS              17
 127 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE                  ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
 128 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS            18
 129 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
 130 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS               19
 131 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE                   ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
 132 #define MXC_F_RTC_CTRL_SET_ACTIVE_POS                       20
 133 #define MXC_F_RTC_CTRL_SET_ACTIVE                           ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
 134 #define MXC_F_RTC_CTRL_CLR_ACTIVE_POS                       21
 135 #define MXC_F_RTC_CTRL_CLR_ACTIVE                           ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
 136 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS              22
 137 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE                  ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
 138 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS            23
 139 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
 140 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS           24
 141 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE               ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
 142 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS                 25
 143 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE                     ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
 144 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS                 26
 145 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE                     ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
 146
 147 #define MXC_F_RTC_FLAGS_COMP0_POS                           0
 148 #define MXC_F_RTC_FLAGS_COMP0                               ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
 149 #define MXC_F_RTC_FLAGS_COMP1_POS                           1
 150 #define MXC_F_RTC_FLAGS_COMP1                               ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
 151 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS                   2
 152 #define MXC_F_RTC_FLAGS_PRESCALE_COMP                       ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
 153 #define MXC_F_RTC_FLAGS_OVERFLOW_POS                        3
 154 #define MXC_F_RTC_FLAGS_OVERFLOW                            ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
 155 #define MXC_F_RTC_FLAGS_TRIM_POS                            4
 156 #define MXC_F_RTC_FLAGS_TRIM                                ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
 157 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS                    8
 158 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A                        ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
 159 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS                    9
 160 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A                        ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
 161 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS                   10
 162 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A                       ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
 163 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS                 11
 164 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A                     ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
 165 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS                     12
 166 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A                         ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
 167 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS                 31
 168 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS                     ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
 169
 170 #define MXC_F_RTC_INTEN_COMP0_POS                           0
 171 #define MXC_F_RTC_INTEN_COMP0                               ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
 172 #define MXC_F_RTC_INTEN_COMP1_POS                           1
 173 #define MXC_F_RTC_INTEN_COMP1                               ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
 174 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS                   2
 175 #define MXC_F_RTC_INTEN_PRESCALE_COMP                       ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
 176 #define MXC_F_RTC_INTEN_OVERFLOW_POS                        3
 177 #define MXC_F_RTC_INTEN_OVERFLOW                            ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
 178 #define MXC_F_RTC_INTEN_TRIM_POS                            4
 179 #define MXC_F_RTC_INTEN_TRIM                                ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
 180
 181 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS              0
 182 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION                  ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
 183
 184 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS               0
 185 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK                   ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
 186
 187 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS               0
 188 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
 189 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS           1
 190 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R               ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
 191 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS               2
 192 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
 193
 194 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS                 0
 195 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE                     ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
 196 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS               18
 197 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
 198
 199 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS            0
 200 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER                ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
 201
 202 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS                      0
 203 #define MXC_F_RTC_CLK_CTRL_OSC1_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
 204 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS                      1
 205 #define MXC_F_RTC_CLK_CTRL_OSC2_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
 206 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS                      2
 207 #define MXC_F_RTC_CLK_CTRL_NANO_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
 208
 209 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS                0
 210 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE                    ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
 211
 212 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS                   0
 213 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS                       ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
 214 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS                1
 215 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R                    ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
 216 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS              2
 217 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL                  ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
 218 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS                3
 219 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O                    ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
 220
 221 /*                                      Offset   Register Description
 222                                         ======   ===================================================================== */
 223 typedef struct {
 224     __IO uint32_t nano_counter;     /*  0x0000   Nanoring Counter Read Register                                        */
 225     __IO uint32_t clk_ctrl;         /*  0x0004   RTC Clock Control Settings                                            */
 226     __IO uint32_t dsen_ctrl;        /*  0x0008   Dynamic Tamper Sensor Control                                         */
 227     __IO uint32_t osc_ctrl;         /*  0x000C   RTC Oscillator Control                                                */
 228 } mxc_rtccfg_regs_t;
 229
 230 /*
 231    Register offsets for module RTCCFG.
 232 */
 233 #define MXC_R_RTCCFG_OFFS_NANO_COUNTER            ((uint32_t)0x00000000UL)
 234 #define MXC_R_RTCCFG_OFFS_CLK_CTRL                ((uint32_t)0x00000004UL)
 235 #define MXC_R_RTCCFG_OFFS_DSEN_CTRL               ((uint32_t)0x00000008UL)
 236 #define MXC_R_RTCCFG_OFFS_OSC_CTRL                ((uint32_t)0x0000000CUL)
 237
 238 #ifdef __cplusplus
 239 }
 240 #endif
 241
 242 /**
 243 * @}
 244 */
 245
 246 #endif /* _MXC_RTC_REGS_H */