tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h

   1 /*******************************************************************************
   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
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  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  24  * Products, Inc. Branding Policy.
  25  *
  26  * The mere transfer of this software does not imply any licenses
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  32  */
  33
  34 #ifndef _MXC_IOMAN_REGS_H_
  35 #define _MXC_IOMAN_REGS_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  ioman_regs.h
  45  * @addtogroup ioman IO MUX Manager
  46  * @{
  47  */
  48
  49 typedef enum {
  50     /** Pin Mapping 'A' */
  51     MXC_E_IOMAN_MAPPING_A = 0,
  52     /** Pin Mapping 'B' */
  53     MXC_E_IOMAN_MAPPING_B,
  54     /** Pin Mapping 'C' */
  55     MXC_E_IOMAN_MAPPING_C,
  56     /** Pin Mapping 'D' */
  57     MXC_E_IOMAN_MAPPING_D,
  58     /** Pin Mapping 'E' */
  59     MXC_E_IOMAN_MAPPING_E,
  60     /** Pin Mapping 'F' */
  61     MXC_E_IOMAN_MAPPING_F,
  62     /** Pin Mapping 'G' */
  63     MXC_E_IOMAN_MAPPING_G,
  64     /** Pin Mapping 'H' */
  65     MXC_E_IOMAN_MAPPING_H,
  66 } ioman_mapping_t;
  67
  68 /*                                      Offset   Register Description
  69                                         ======   ========================================== */
  70 typedef struct {
  71     __IO uint32_t wud_req0;         /*  0x0000   Wakeup Detect Mode Request Register 0      */
  72     __IO uint32_t wud_req1;         /*  0x0004   Wakeup Detect Mode Request Register 1      */
  73     __IO uint32_t wud_ack0;         /*  0x0008   Wakeup Detect Mode Acknowledge Register 0  */
  74     __IO uint32_t wud_ack1;         /*  0x000C   Wakeup Detect Mode Acknowledge Register 1  */
  75     __IO uint32_t ali_req0;         /*  0x0010   Analog Input Request Register 0            */
  76     __IO uint32_t ali_req1;         /*  0x0014   Analog Input Request Register 1            */
  77     __IO uint32_t ali_ack0;         /*  0x0018   Analog Input Acknowledge Register 0        */
  78     __IO uint32_t ali_ack1;         /*  0x001C   Analog Input Acknowledge Register 1        */
  79     __IO uint32_t spi0_req;         /*  0x0020   SPI0 I/O Mode Request                      */
  80     __IO uint32_t spi0_ack;         /*  0x0024   SPI0 I/O Mode Acknowledge                  */
  81     __IO uint32_t spi1_req;         /*  0x0028   SPI1 I/O Mode Request                      */
  82     __IO uint32_t spi1_ack;         /*  0x002C   SPI1 I/O Mode Acknowledge                  */
  83     __IO uint32_t spi2_req;         /*  0x0030   SPI2 I/O Mode Request                      */
  84     __IO uint32_t spi2_ack;         /*  0x0034   SPI2 I/O Mode Acknowledge                  */
  85     __IO uint32_t uart0_req;        /*  0x0038   UART0 I/O Mode Request                     */
  86     __IO uint32_t uart0_ack;        /*  0x003C   UART0 I/O Mode Acknowledge                 */
  87     __IO uint32_t uart1_req;        /*  0x0040   UART1 I/O Mode Request                     */
  88     __IO uint32_t uart1_ack;        /*  0x0044   UART1 I/O Mode Acknowledge                 */
  89     __IO uint32_t i2cm0_req;        /*  0x0048   I2C Master 0 I/O Request                   */
  90     __IO uint32_t i2cm0_ack;        /*  0x004C   I2C Master 0 I/O Acknowledge               */
  91     __IO uint32_t i2cs0_req;        /*  0x0050   I2C Slave 0 I/O Request                    */
  92     __IO uint32_t i2s0_ack;         /*  0x0054   I2C Slave 0 I/O Acknowledge                */
  93     __IO uint32_t lcd_com_req;      /*  0x0058   LCD COM Driver I/O Request                 */
  94     __IO uint32_t lcd_com_ack;      /*  0x005C   LCD COM Driver I/O Acknowledge             */
  95     __IO uint32_t lcd_seg_req0;     /*  0x0060   LCD SEG Driver I/O Request Register 0      */
  96     __IO uint32_t lcd_seg_req1;     /*  0x0064   LCD SEG Driver I/O Request Register 1      */
  97     __IO uint32_t lcd_seg_ack0;     /*  0x0068   LCD SEG Driver I/O Acknowledge Register 0  */
  98     __IO uint32_t lcd_seg_ack1;     /*  0x006C   LCD SEG Driver I/O Acknowledge Register 1  */
  99     __IO uint32_t crnt_req;         /*  0x0070   Current Drive I/O Request Register         */
 100     __IO uint32_t io_crnt_ack;      /*  0x0074   Current Drive I/O Acknowledge Register     */
 101     __IO uint32_t crnt_mode;        /*  0x0078   Current Drive I/O Mode Control             */
 102     __IO uint32_t ali_connect0;     /*  0x007C   Analog I/O Connection Control Register 0   */
 103     __IO uint32_t ali_connect1;     /*  0x0080   Analog I/O Connection Control Register 1   */
 104     __IO uint32_t i2cm1_req;        /*  0x0084   I2C Master 1 I/O Request                   */
 105     __IO uint32_t i2cm1_ack;        /*  0x0088   I2C Master 1 I/O Acknowledge               */
 106     __IO uint32_t padx_control;     /*  0x008C   PADX Control                               */
 107 } mxc_ioman_regs_t;
 108
 109
 110 /*
 111    Register offsets for module IOMAN.
 112 */
 113 #define MXC_R_IOMAN_OFFS_WUD_REQ0                 ((uint32_t)0x00000000UL)
 114 #define MXC_R_IOMAN_OFFS_WUD_REQ1                 ((uint32_t)0x00000004UL)
 115 #define MXC_R_IOMAN_OFFS_WUD_ACK0                 ((uint32_t)0x00000008UL)
 116 #define MXC_R_IOMAN_OFFS_WUD_ACK1                 ((uint32_t)0x0000000CUL)
 117 #define MXC_R_IOMAN_OFFS_ALI_REQ0                 ((uint32_t)0x00000010UL)
 118 #define MXC_R_IOMAN_OFFS_ALI_REQ1                 ((uint32_t)0x00000014UL)
 119 #define MXC_R_IOMAN_OFFS_ALI_ACK0                 ((uint32_t)0x00000018UL)
 120 #define MXC_R_IOMAN_OFFS_ALI_ACK1                 ((uint32_t)0x0000001CUL)
 121 #define MXC_R_IOMAN_OFFS_SPI0_REQ                 ((uint32_t)0x00000020UL)
 122 #define MXC_R_IOMAN_OFFS_SPI0_ACK                 ((uint32_t)0x00000024UL)
 123 #define MXC_R_IOMAN_OFFS_SPI1_REQ                 ((uint32_t)0x00000028UL)
 124 #define MXC_R_IOMAN_OFFS_SPI1_ACK                 ((uint32_t)0x0000002CUL)
 125 #define MXC_R_IOMAN_OFFS_SPI2_REQ                 ((uint32_t)0x00000030UL)
 126 #define MXC_R_IOMAN_OFFS_SPI2_ACK                 ((uint32_t)0x00000034UL)
 127 #define MXC_R_IOMAN_OFFS_UART0_REQ                ((uint32_t)0x00000038UL)
 128 #define MXC_R_IOMAN_OFFS_UART0_ACK                ((uint32_t)0x0000003CUL)
 129 #define MXC_R_IOMAN_OFFS_UART1_REQ                ((uint32_t)0x00000040UL)
 130 #define MXC_R_IOMAN_OFFS_UART1_ACK                ((uint32_t)0x00000044UL)
 131 #define MXC_R_IOMAN_OFFS_I2CM0_REQ                ((uint32_t)0x00000048UL)
 132 #define MXC_R_IOMAN_OFFS_I2CM0_ACK                ((uint32_t)0x0000004CUL)
 133 #define MXC_R_IOMAN_OFFS_I2CS0_REQ                ((uint32_t)0x00000050UL)
 134 #define MXC_R_IOMAN_OFFS_I2SC0_ACK                ((uint32_t)0x00000054UL)
 135 #define MXC_R_IOMAN_OFFS_LCD_COM_REQ              ((uint32_t)0x00000058UL)
 136 #define MXC_R_IOMAN_OFFS_LCD_COM_ACK              ((uint32_t)0x0000005CUL)
 137 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0             ((uint32_t)0x00000060UL)
 138 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1             ((uint32_t)0x00000064UL)
 139 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0             ((uint32_t)0x00000068UL)
 140 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1             ((uint32_t)0x0000006CUL)
 141 #define MXC_R_IOMAN_OFFS_IO_CRNT_REQ              ((uint32_t)0x00000070UL)
 142 #define MXC_R_IOMAN_OFFS_IO_CRNT_ACK              ((uint32_t)0x00000074UL)
 143 #define MXC_R_IOMAN_OFFS_IO_CRNT_MODE             ((uint32_t)0x00000078UL)
 144 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0             ((uint32_t)0x0000007CUL)
 145 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1             ((uint32_t)0x00000080UL)
 146 #define MXC_R_IOMAN_OFFS_I2CM1_REQ                ((uint32_t)0x00000084UL)
 147 #define MXC_R_IOMAN_OFFS_I2CM1_ACK                ((uint32_t)0x00000088UL)
 148 #define MXC_R_IOMAN_OFFS_PADX_CONTROL             ((uint32_t)0x0000008CUL)
 149
 150
 151 /*
 152    Field positions and masks for module IOMAN.
 153 */
 154 #define MXC_F_IOMAN_WUD_REQ0_PORT0_POS                      0
 155 #define MXC_F_IOMAN_WUD_REQ0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
 156 #define MXC_F_IOMAN_WUD_REQ0_PORT1_POS                      8
 157 #define MXC_F_IOMAN_WUD_REQ0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
 158 #define MXC_F_IOMAN_WUD_REQ0_PORT2_POS                      16
 159 #define MXC_F_IOMAN_WUD_REQ0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
 160 #define MXC_F_IOMAN_WUD_REQ0_PORT3_POS                      24
 161 #define MXC_F_IOMAN_WUD_REQ0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
 162
 163 #define MXC_F_IOMAN_WUD_REQ1_PORT4_POS                      0
 164 #define MXC_F_IOMAN_WUD_REQ1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
 165 #define MXC_F_IOMAN_WUD_REQ1_PORT5_POS                      8
 166 #define MXC_F_IOMAN_WUD_REQ1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
 167 #define MXC_F_IOMAN_WUD_REQ1_PORT6_POS                      16
 168 #define MXC_F_IOMAN_WUD_REQ1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
 169 #define MXC_F_IOMAN_WUD_REQ1_PORT7_POS                      24
 170 #define MXC_F_IOMAN_WUD_REQ1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
 171
 172 #define MXC_F_IOMAN_WUD_ACK0_PORT0_POS                      0
 173 #define MXC_F_IOMAN_WUD_ACK0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
 174 #define MXC_F_IOMAN_WUD_ACK0_PORT1_POS                      8
 175 #define MXC_F_IOMAN_WUD_ACK0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
 176 #define MXC_F_IOMAN_WUD_ACK0_PORT2_POS                      16
 177 #define MXC_F_IOMAN_WUD_ACK0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
 178 #define MXC_F_IOMAN_WUD_ACK0_PORT3_POS                      24
 179 #define MXC_F_IOMAN_WUD_ACK0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
 180
 181 #define MXC_F_IOMAN_WUD_ACK1_PORT4_POS                      0
 182 #define MXC_F_IOMAN_WUD_ACK1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
 183 #define MXC_F_IOMAN_WUD_ACK1_PORT5_POS                      8
 184 #define MXC_F_IOMAN_WUD_ACK1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
 185 #define MXC_F_IOMAN_WUD_ACK1_PORT6_POS                      16
 186 #define MXC_F_IOMAN_WUD_ACK1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
 187 #define MXC_F_IOMAN_WUD_ACK1_PORT7_POS                      24
 188 #define MXC_F_IOMAN_WUD_ACK1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
 189
 190 #define MXC_F_IOMAN_ALI_REQ0_PORT0_POS                      0
 191 #define MXC_F_IOMAN_ALI_REQ0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
 192 #define MXC_F_IOMAN_ALI_REQ0_PORT1_POS                      8
 193 #define MXC_F_IOMAN_ALI_REQ0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
 194 #define MXC_F_IOMAN_ALI_REQ0_PORT2_POS                      16
 195 #define MXC_F_IOMAN_ALI_REQ0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
 196 #define MXC_F_IOMAN_ALI_REQ0_PORT3_POS                      24
 197 #define MXC_F_IOMAN_ALI_REQ0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
 198
 199 #define MXC_F_IOMAN_ALI_REQ1_PORT4_POS                      0
 200 #define MXC_F_IOMAN_ALI_REQ1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
 201 #define MXC_F_IOMAN_ALI_REQ1_PORT5_POS                      8
 202 #define MXC_F_IOMAN_ALI_REQ1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
 203 #define MXC_F_IOMAN_ALI_REQ1_PORT6_POS                      16
 204 #define MXC_F_IOMAN_ALI_REQ1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
 205 #define MXC_F_IOMAN_ALI_REQ1_PORT7_POS                      24
 206 #define MXC_F_IOMAN_ALI_REQ1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
 207
 208 #define MXC_F_IOMAN_ALI_ACK0_PORT0_POS                      0
 209 #define MXC_F_IOMAN_ALI_ACK0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
 210 #define MXC_F_IOMAN_ALI_ACK0_PORT1_POS                      8
 211 #define MXC_F_IOMAN_ALI_ACK0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
 212 #define MXC_F_IOMAN_ALI_ACK0_PORT2_POS                      16
 213 #define MXC_F_IOMAN_ALI_ACK0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
 214 #define MXC_F_IOMAN_ALI_ACK0_PORT3_POS                      24
 215 #define MXC_F_IOMAN_ALI_ACK0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
 216
 217 #define MXC_F_IOMAN_ALI_ACK1_PORT4_POS                      0
 218 #define MXC_F_IOMAN_ALI_ACK1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
 219 #define MXC_F_IOMAN_ALI_ACK1_PORT5_POS                      8
 220 #define MXC_F_IOMAN_ALI_ACK1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
 221 #define MXC_F_IOMAN_ALI_ACK1_PORT6_POS                      16
 222 #define MXC_F_IOMAN_ALI_ACK1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
 223 #define MXC_F_IOMAN_ALI_ACK1_PORT7_POS                      24
 224 #define MXC_F_IOMAN_ALI_ACK1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
 225
 226 #define MXC_F_IOMAN_SPI_MAPPING_POS                         0
 227 #define MXC_F_IOMAN_SPI_MAPPING                             ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
 228 #define MXC_F_IOMAN_SPI_CORE_IO_POS                         4
 229 #define MXC_F_IOMAN_SPI_CORE_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
 230 #define MXC_F_IOMAN_SPI_SS0_IO_POS                          8
 231 #define MXC_F_IOMAN_SPI_SS0_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
 232 #define MXC_F_IOMAN_SPI_SS1_IO_POS                          9
 233 #define MXC_F_IOMAN_SPI_SS1_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
 234 #define MXC_F_IOMAN_SPI_SS2_IO_POS                          10
 235 #define MXC_F_IOMAN_SPI_SS2_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
 236 #define MXC_F_IOMAN_SPI_SS3_IO_POS                          11
 237 #define MXC_F_IOMAN_SPI_SS3_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
 238 #define MXC_F_IOMAN_SPI_SS4_IO_POS                          12
 239 #define MXC_F_IOMAN_SPI_SS4_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
 240 #define MXC_F_IOMAN_SPI_SR0_IO_POS                          16
 241 #define MXC_F_IOMAN_SPI_SR0_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
 242 #define MXC_F_IOMAN_SPI_SR1_IO_POS                          17
 243 #define MXC_F_IOMAN_SPI_SR1_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
 244 #define MXC_F_IOMAN_SPI_QUAD_IO_POS                         20
 245 #define MXC_F_IOMAN_SPI_QUAD_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
 246 #define MXC_F_IOMAN_SPI_FAST_MODE_POS                       24
 247 #define MXC_F_IOMAN_SPI_FAST_MODE                           ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
 248
 249 #define MXC_F_IOMAN_UART_MAPPING_POS                        0
 250 #define MXC_F_IOMAN_UART_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
 251 #define MXC_F_IOMAN_UART_CORE_IO_POS                        4
 252 #define MXC_F_IOMAN_UART_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
 253 #define MXC_F_IOMAN_UART_CTS_IO_POS                         5
 254 #define MXC_F_IOMAN_UART_CTS_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
 255 #define MXC_F_IOMAN_UART_RTS_IO_POS                         6
 256 #define MXC_F_IOMAN_UART_RTS_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
 257
 258 #define MXC_F_IOMAN_I2CM_MAPPING_POS                        0
 259 #define MXC_F_IOMAN_I2CM_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
 260 #define MXC_F_IOMAN_I2CM_CORE_IO_POS                        4
 261 #define MXC_F_IOMAN_I2CM_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
 262
 263 #define MXC_F_IOMAN_I2CS_MAPPING_POS                        0
 264 #define MXC_F_IOMAN_I2CS_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
 265 #define MXC_F_IOMAN_I2CS_CORE_IO_POS                        4
 266 #define MXC_F_IOMAN_I2CS_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
 267
 268 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS                  0
 269 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO                      ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
 270
 271 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS                  0
 272 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO                      ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
 273
 274 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS              0
 275 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
 276 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS              1
 277 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
 278 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS              2
 279 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
 280 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS              3
 281 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
 282 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS              4
 283 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
 284 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS              5
 285 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
 286 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS              6
 287 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
 288 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS              7
 289 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
 290 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS              8
 291 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
 292 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS              9
 293 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
 294 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS              10
 295 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
 296 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS              11
 297 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
 298 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS              12
 299 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
 300 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS              13
 301 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
 302 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS              14
 303 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
 304 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS              15
 305 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
 306 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS              16
 307 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
 308 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS              17
 309 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
 310 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS              18
 311 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
 312 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS              19
 313 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
 314 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS              20
 315 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
 316 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS              21
 317 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
 318 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS              22
 319 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
 320 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS              23
 321 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
 322 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS              24
 323 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
 324 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS              25
 325 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
 326 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS              26
 327 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
 328 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS              27
 329 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
 330 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS              28
 331 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
 332 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS              29
 333 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
 334 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS              30
 335 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
 336 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS              31
 337 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
 338
 339 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS              0
 340 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
 341 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS              1
 342 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
 343 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS              2
 344 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
 345 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS              3
 346 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
 347 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS              4
 348 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
 349 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS              5
 350 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
 351 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS              6
 352 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
 353 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS              7
 354 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
 355
 356 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS              0
 357 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
 358 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS              1
 359 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
 360 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS              2
 361 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
 362 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS              3
 363 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
 364 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS              4
 365 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
 366 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS              5
 367 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
 368 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS              6
 369 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
 370 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS              7
 371 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
 372 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS              8
 373 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
 374 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS              9
 375 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
 376 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS              10
 377 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
 378 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS              11
 379 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
 380 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS              12
 381 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
 382 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS              13
 383 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
 384 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS              14
 385 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
 386 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS              15
 387 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
 388 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS              16
 389 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
 390 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS              17
 391 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
 392 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS              18
 393 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
 394 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS              19
 395 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
 396 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS              20
 397 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
 398 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS              21
 399 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
 400 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS              22
 401 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
 402 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS              23
 403 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
 404 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS              24
 405 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
 406 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS              25
 407 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
 408 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS              26
 409 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
 410 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS              27
 411 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
 412 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS              28
 413 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
 414 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS              29
 415 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
 416 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS              30
 417 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
 418 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS              31
 419 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
 420
 421 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS              0
 422 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
 423 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS              1
 424 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
 425 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS              2
 426 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
 427 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS              3
 428 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
 429 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS              4
 430 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
 431 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS              5
 432 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
 433 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS              6
 434 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
 435 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS              7
 436 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
 437
 438 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS               0
 439 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
 440 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS               1
 441 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
 442 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS               2
 443 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
 444 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS               3
 445 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
 446 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS               4
 447 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
 448 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS               5
 449 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
 450 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS               6
 451 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
 452 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS               7
 453 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
 454
 455 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS               0
 456 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
 457 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS               1
 458 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
 459 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS               2
 460 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
 461 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS               3
 462 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
 463 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS               4
 464 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
 465 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS               5
 466 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
 467 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS               6
 468 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
 469 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS               7
 470 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
 471
 472 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS                  0
 473 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
 474 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS                  4
 475 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
 476 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS                  8
 477 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
 478 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS                  12
 479 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
 480 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS                  16
 481 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
 482 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS                  20
 483 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
 484 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS                  24
 485 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
 486 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS                  28
 487 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
 488
 489 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS     0
 490 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL         ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
 491 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS    4
 492 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE        ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
 493 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
 494 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE     ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
 495 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS    8
 496 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE        ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
 497 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
 498 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE     ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
 499
 500 #ifdef __cplusplus
 501 }
 502 #endif
 503
 504 /**
 505 * @}
 506 */
 507
 508 #endif   /* _MXC_IOMAN_REGS_H_ */