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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_NXP / TARGET_LPC408X / system_LPC407x_8x_177x_8x.c
1 /**********************************************************************
2 * $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16
3 *//**
4 * @file system_LPC407x_8x_177x_8x.c
5 * @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
6 * for the NXP LPC407x_8x_177x_8x Device Series
7 *
8 * ARM Limited (ARM) is supplying this software for use with
9 * Cortex-M processor based microcontrollers. This file can be
10 * freely distributed within development tools that are supporting
11 * such ARM based processors.
12 *
13 * @version 1.2
14 * @date 20. June. 2012
15 * @author NXP MCU SW Application Team
16 *
17 * Copyright(C) 2012, NXP Semiconductor
18 * All rights reserved.
19 *
20 ***********************************************************************
21 * Software that is described herein is for illustrative purposes only
22 * which provides customers with programming information regarding the
23 * products. This software is supplied "AS IS" without any warranties.
24 * NXP Semiconductors assumes no responsibility or liability for the
25 * use of the software, conveys no license or title under any patent,
26 * copyright, or mask work right to the product. NXP Semiconductors
27 * reserves the right to make changes in the software without
28 * notification. NXP Semiconductors also make no representation or
29 * warranty that such application will be suitable for the specified
30 * use without further testing or modification.
31 **********************************************************************/
32
33 #include <stdint.h>
34 #include "LPC407x_8x_177x_8x.h"
35 #include "system_LPC407x_8x_177x_8x.h"
36
37 #define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
38
39 /*
40 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
41 */
42 /*--------------------- Clock Configuration ----------------------------------
43 //
44 // <e> Clock Configuration
45 // <h> System Controls and Status Register (SCS - address 0x400F C1A0)
46 // <o1.0> EMC Shift Control Bit
47 // <i> Controls how addresses are output on the EMC address pins for static memories
48 // <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
49 // <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
50 //
51 // <o1.1> EMC Reset Disable Bit
52 // <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
53 // <i> If 1, EMC is still retained its state through a warm reset
54 // <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
55 // <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
56 //
57 // <o1.2> EMC Burst Control
58 // <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
59 // <0=> Burst enabled (Bit 2 is 0)
60 // <1=> Bust disbled (Bit 2 is 1)
61 //
62 // <o1.3> MCIPWR Active Level
63 // <i> Selects the active level for the SD card interface signal SD_PWR
64 // <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
65 // <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
66 //
67 // <o1.4> Main Oscillator Range Select
68 // <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
69 // <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
70 //
71 // <o1.5> Main Oscillator enable
72 // <i> 0 (zero) means disabled, 1 means enable
73 //
74 // <o1.6> Main Oscillator status (Read-Only)
75 // </h>
76 //
77 // <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
78 // <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
79 // <0=> Internal RC oscillator (Bit 0 is 0)
80 // <1=> Main oscillator (Bit 0 is 1)
81 // </h>
82 //
83 // <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
84 // <i> F_in is in the range of 1 MHz to 25 MHz
85 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
86 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
87 //
88 // <o4.0..4> MSEL: PLL Multiplier Value
89 // <i> M Value
90 // <1-32><#-1>
91 //
92 // <o4.5..6> PSEL: PLL Divider Value
93 // <i> P Value
94 // <0=> 1
95 // <1=> 2
96 // <2=> 4
97 // <3=> 8
98 // </e>
99 //
100 // <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
101 // <i> F_in is in the range of 1 MHz to 25 MHz
102 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
103 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
104 //
105 // <o6.0..4> MSEL: PLL Multiplier Value
106 // <i> M Value
107 // <1-32><#-1>
108 //
109 // <o6.5..6> PSEL: PLL Divider Value
110 // <i> P Value
111 // <0=> 1
112 // <1=> 2
113 // <2=> 4
114 // <3=> 8
115 // </e>
116 //
117 // <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
118 // <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
119 // <i> 0: The divider is turned off. No clock will be provided to the CPU
120 // <i> n: The input clock is divided by n to produce the CPU clock
121 // <0-31>
122 //
123 // <o7.8> CCLKSEL: Select the input to the divider of CPU clock
124 // <0=> sysclk clock is used
125 // <1=> Main PLL0 clock is used
126 // </h>
127 //
128 // <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
129 // <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
130 // <0=> Divider is off and no clock provides to USB subsystem
131 // <4=> Divider value is 4 (The source clock is divided by 4)
132 // <6=> Divider value is 6 (The source clock is divided by 6)
133 //
134 // <o8.8..9> USBSEL: Select the source for USB clock divider
135 // <i> When CPU clock is selected, the USB can be accessed
136 // <i> by software but cannot perform USB functions
137 // <0=> sysclk clock (the clock input to PLL0)
138 // <1=> The clock output from PLL0
139 // <2=> The clock output from PLL1
140 // </h>
141 //
142 // <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
143 // <o9.0> EMCDIV: Set the divider for EMC clock
144 // <0=> Divider value is 1
145 // <1=> Divider value is 2 (EMC clock is equal a half of input clock)
146 // </h>
147 //
148 // <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
149 // <o10.0..4> PCLKDIV: APB Peripheral clock divider
150 // <i> 0: The divider is turned off. No clock will be provided to APB peripherals
151 // <i> n: The input clock is divided by n to produce the APB peripheral clock
152 // <0-31>
153 // </h>
154 //
155 // <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
156 // <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock
157 // <i> 0: The divider is turned off. No clock will be provided to the SPIFI
158 // <i> n: The input clock is divided by n to produce the SPIFI clock
159 // <0-31>
160 //
161 // <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider
162 // <0=> sysclk clock (the clock input to PLL0)
163 // <1=> The clock output from PLL0
164 // <2=> The clock output from PLL1
165 // </h>
166 //
167 // <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
168 // <o12.0> PCLCD: LCD controller power/clock enable (bit 0)
169 // <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
170 // <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
171 // <o12.3> PCUART0: UART 0 power/clock enable (bit 3)
172 // <o12.4> PCUART1: UART 1 power/clock enable (bit 4)
173 // <o12.5> PCPWM0: PWM0 power/clock enable (bit 5)
174 // <o12.6> PCPWM1: PWM1 power/clock enable (bit 6)
175 // <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
176 // <o12.8> PCUART4: UART 4 power/clock enable (bit 8)
177 // <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
178 // <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
179 // <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11)
180 // <o12.12> PCADC: A/D converter power/clock enable (bit 12)
181 // <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
182 // <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
183 // <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
184 // <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
185 // <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
186 // <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
187 // <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
188 // <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
189 // <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22)
190 // <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23)
191 // <o12.24> PCUART2: UART 2 power/clock enable (bit 24)
192 // <o12.25> PCUART3: UART 3 power/clock enable (bit 25)
193 // <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
194 // <o12.27> PCI2S: I2S interface power/clock enable (bit 27)
195 // <o12.28> PCSDC: SD Card interface power/clock enable (bit 28)
196 // <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
197 // <o12.30> PCENET: Ethernet block power/clock enable (bit 30)
198 // <o12.31> PCUSB: USB interface power/clock enable (bit 31)
199 // </h>
200 //
201 // <h> Clock Output Configuration Register (CLKOUTCFG)
202 // <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
203 // <0=> CPU clock
204 // <1=> Main Oscillator
205 // <2=> Internal RC Oscillator
206 // <3=> USB clock
207 // <4=> RTC Oscillator
208 // <5=> unused
209 // <6=> Watchdog Oscillator
210 //
211 // <o13.4..7> CLKOUTDIV: Output Clock Divider
212 // <1-16><#-1>
213 //
214 // <o13.8> CLKOUT_EN: CLKOUT enable
215 // </h>
216 //
217 // </e>
218 */
219
220 #define CLOCK_SETUP 1
221 #define SCS_Val 0x00000020
222 #define CLKSRCSEL_Val 0x00000001
223 #define PLL0_SETUP 1
224 #define PLL0CFG_Val 0x00000009
225 #define PLL1_SETUP 1
226 #define PLL1CFG_Val 0x00000023
227 #define CCLKSEL_Val 0x00000101
228 #define USBCLKSEL_Val 0x00000201
229 #define EMCCLKSEL_Val 0x00000001
230 #define PCLKSEL_Val 0x00000002
231 #define SPIFICLKSEL_Val 0x00000002
232 #define PCONP_Val 0x042887DE
233 #define CLKOUTCFG_Val 0x00000100
234
235 #ifdef CORE_M4
236 #define LPC_CPACR 0xE000ED88
237
238 #define SCB_MVFR0 0xE000EF40
239 #define SCB_MVFR0_RESET 0x10110021
240
241 #define SCB_MVFR1 0xE000EF44
242 #define SCB_MVFR1_RESET 0x11000011
243 #endif
244
245
246 /*--------------------- Flash Accelerator Configuration ----------------------
247 //
248 // <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
249 // <o1.12..15> FLASHTIM: Flash Access Time
250 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
251 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
252 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
253 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
254 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
255 // <5=> 6 CPU clocks (for any CPU clock)
256 // </e>
257 */
258
259 #define FLASH_SETUP 1
260 #define FLASHCFG_Val 0x00005000
261
262 /*----------------------------------------------------------------------------
263 Check the register settings
264 *----------------------------------------------------------------------------*/
265 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
266 #define CHECK_RSVD(val, mask) (val & mask)
267
268 /* Clock Configuration -------------------------------------------------------*/
269 #if (CHECK_RSVD((SCS_Val), ~0x0000003F))
270 #error "SCS: Invalid values of reserved bits!"
271 #endif
272
273 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
274 #error "CLKSRCSEL: Value out of range!"
275 #endif
276
277 #if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
278 #error "PLL0CFG: Invalid values of reserved bits!"
279 #endif
280
281 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
282 #error "PLL1CFG: Invalid values of reserved bits!"
283 #endif
284
285 #if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
286 #error "CCLKSEL: Invalid values of reserved bits!"
287 #endif
288
289 #if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
290 #error "USBCLKSEL: Invalid values of reserved bits!"
291 #endif
292
293 #if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
294 #error "EMCCLKSEL: Invalid values of reserved bits!"
295 #endif
296
297 #if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
298 #error "PCLKSEL: Invalid values of reserved bits!"
299 #endif
300
301 #if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
302 #error "PCONP: Invalid values of reserved bits!"
303 #endif
304
305 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
306 #error "CLKOUTCFG: Invalid values of reserved bits!"
307 #endif
308
309 /* Flash Accelerator Configuration -------------------------------------------*/
310 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
311 #warning "FLASHCFG: Invalid values of reserved bits!"
312 #endif
313
314
315 /*----------------------------------------------------------------------------
316 DEFINES
317 *----------------------------------------------------------------------------*/
318 /* pll_out_clk = F_cco / (2 � P)
319 F_cco = pll_in_clk � M � 2 � P */
320 #define __M ((PLL0CFG_Val & 0x1F) + 1)
321 #define __PLL0_CLK(__F_IN) (__F_IN * __M)
322 #define __CCLK_DIV (CCLKSEL_Val & 0x1F)
323 #define __PCLK_DIV (PCLKSEL_Val & 0x1F)
324 #define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
325
326 /* Determine core clock frequency according to settings */
327 #if (CLOCK_SETUP) /* Clock Setup */
328
329 #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
330 #error "Main Oscillator is selected as clock source but is not enabled!"
331 #endif
332
333 #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
334 #error "Main PLL is selected as clock source but is not enabled!"
335 #endif
336
337 #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
338 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
339 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
340 #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
341 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
342 #else /* sysclk = osc_clk */
343 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
344 #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
345 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
346 #endif
347 #else /* cclk = pll_clk */
348 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
349 #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
350 #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
351 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
352 #else /* sysclk = osc_clk */
353 #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
354 #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
355 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
356 #endif
357 #endif
358
359 #else
360 #define __CORE_CLK (IRC_OSC)
361 #define __PER_CLK (IRC_OSC)
362 #define __EMC_CLK (__CORE_CLK)
363 #endif
364
365 /*----------------------------------------------------------------------------
366 Clock Variable definitions
367 *----------------------------------------------------------------------------*/
368 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
369 uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
370 uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
371 uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
372 be updated after call SystemCoreClockUpdate, should be 48MHz*/
373
374
375 /*----------------------------------------------------------------------------
376 Clock functions
377 *----------------------------------------------------------------------------*/
378 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
379 {
380 /* Determine clock frequency according to clock register values */
381 if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
382 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
383 SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
384 PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
385 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
386 }
387 else { /* sysclk = osc_clk */
388 if ((LPC_SC->SCS & 0x40) == 0) {
389 SystemCoreClock = 0; /* this should never happen! */
390 PeripheralClock = 0;
391 EMCClock = 0;
392 }
393 else {
394 SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
395 PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
396 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
397 }
398 }
399 }
400 else { /* cclk = pll_clk */
401 if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
402 SystemCoreClock = 0; /* this should never happen! */
403 PeripheralClock = 0;
404 EMCClock = 0;
405 }
406 else {
407 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
408 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
409 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
410 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
411 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
412 SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
413 PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
414 EMCClock = SystemCoreClock / emc_div;
415 }
416 else { /* sysclk = osc_clk */
417 if ((LPC_SC->SCS & 0x40) == 0) {
418 SystemCoreClock = 0; /* this should never happen! */
419 PeripheralClock = 0;
420 EMCClock = 0;
421 }
422 else {
423 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
424 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
425 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
426 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
427 SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
428 PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
429 EMCClock = SystemCoreClock / emc_div;
430 }
431 }
432 }
433 }
434 /* ---update USBClock------------------*/
435 if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
436 {
437 switch (LPC_SC->USBCLKSEL & 0x1F)
438 {
439 case 0:
440 USBClock = 0; //no clock will be provided to the USB subsystem
441 break;
442 case 4:
443 case 6:
444 {
445 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
446 uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
447 if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
448 USBClock = OSC_CLK * mul / usb_div;
449 else //pll_clk_in = irc_clk
450 USBClock = IRC_OSC * mul / usb_div;
451 }
452 break;
453 default:
454 USBClock = 0; /* this should never happen! */
455 }
456 }
457 else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
458 {
459 if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
460 USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
461 else //pll1_clk_in = irc_clk
462 USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
463 }
464 else
465 USBClock = 0; /* this should never happen! */
466 }
467
468 /* Determine clock frequency according to clock register values */
469
470 #ifdef CORE_M4
471
472 void fpu_init(void)
473 {
474 // from arm trm manual:
475 // ; CPACR is located at address 0xE000ED88
476 // LDR.W R0, =0xE000ED88
477 // ; Read CPACR
478 // LDR R1, [R0]
479 // ; Set bits 20-23 to enable CP10 and CP11 coprocessors
480 // ORR R1, R1, #(0xF << 20)
481 // ; Write back the modified value to the CPACR
482 // STR R1, [R0]
483
484
485 volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
486 volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
487 volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
488 volatile uint32_t Cpacr;
489 volatile uint32_t Mvfr0;
490 volatile uint32_t Mvfr1;
491 char vfpPresent = 0;
492
493 Mvfr0 = *regMvfr0;
494 Mvfr1 = *regMvfr1;
495
496 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
497
498 if(vfpPresent)
499 {
500 Cpacr = *regCpacr;
501 Cpacr |= (0xF << 20);
502 *regCpacr = Cpacr; // enable CP10 and CP11 for full access
503 }
504
505 }
506 #endif
507
508 /**
509 * Initialize the system
510 *
511 * @param none
512 * @return none
513 *
514 * @brief Setup the microcontroller system.
515 * Initialize the System.
516 */
517 void SystemInit (void)
518 {
519 #ifndef __CODE_RED
520 #ifdef CORE_M4
521 fpu_init();
522 #endif
523 #endif
524
525 #if (CLOCK_SETUP) /* Clock Setup */
526 LPC_SC->SCS = SCS_Val;
527 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
528 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
529 }
530
531 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
532
533 #if (PLL0_SETUP)
534 LPC_SC->PLL0CFG = PLL0CFG_Val;
535 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
536 LPC_SC->PLL0FEED = 0xAA;
537 LPC_SC->PLL0FEED = 0x55;
538 while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
539 #endif
540
541 #if (PLL1_SETUP)
542 LPC_SC->PLL1CFG = PLL1CFG_Val;
543 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
544 LPC_SC->PLL1FEED = 0xAA;
545 LPC_SC->PLL1FEED = 0x55;
546 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
547 #endif
548
549 LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
550 LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
551 LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
552 LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
553 LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
554 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
555 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
556 #endif
557
558 LPC_SC->PBOOST |= 0x03; /* Power Boost control */
559
560 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
561 LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
562 #endif
563 #ifndef __CODE_RED
564 #ifdef __RAM_MODE__
565 SCB->VTOR = 0x10000000 & 0x3FFFFF80;
566 #else
567 SCB->VTOR = 0x00000000 & 0x3FFFFF80;
568 #endif
569 #endif
570 SystemCoreClockUpdate();
571 }
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
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