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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_NXP / TARGET_LPC82X / LPC82x.h
1
2 /****************************************************************************************************//**
3 * @file LPC82x.h
4 *
5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
6 * LPC82x from .
7 *
8 * @version V0.4
9 * @date 17. June 2014
10 *
11 * @note Generated with SVDConv V2.80
12 * from CMSIS SVD File 'LPC82x.svd' Version 0.4,
13 *******************************************************************************************************/
14
15
16
17 /** @addtogroup (null)
18 * @{
19 */
20
21 /** @addtogroup LPC82x
22 * @{
23 */
24
25 #ifndef LPC82X_H
26 #define LPC82X_H
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
32
33 /* ------------------------- Interrupt Number Definition ------------------------ */
34
35 typedef enum {
36 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
37 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
38 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
39 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
40 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
41 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
42 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
43 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
44 /* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */
45 SPI0_IRQn = 0, /*!< 0 SPI0 */
46 SPI1_IRQn = 1, /*!< 1 SPI1 */
47 UART0_IRQn = 3, /*!< 3 UART0 */
48 UART1_IRQn = 4, /*!< 4 UART1 */
49 UART2_IRQn = 5, /*!< 5 UART2 */
50 I2C1_IRQn = 7, /*!< 7 I2C1 */
51 I2C0_IRQn = 8, /*!< 8 I2C0 */
52 SCT_IRQn = 9, /*!< 9 SCT */
53 MRT_IRQn = 10, /*!< 10 MRT */
54 CMP_IRQn = 11, /*!< 11 CMP */
55 WDT_IRQn = 12, /*!< 12 WDT */
56 BOD_IRQn = 13, /*!< 13 BOD */
57 FLASH_IRQn = 14, /*!< 14 FLASH */
58 WKT_IRQn = 15, /*!< 15 WKT */
59 ADC_SEQA_IRQn = 16, /*!< 16 ADC_SEQA */
60 ADC_SEQB_IRQn = 17, /*!< 17 ADC_SEQB */
61 ADC_THCMP_IRQn = 18, /*!< 18 ADC_THCMP */
62 ADC_OVR_IRQn = 19, /*!< 19 ADC_OVR */
63 DMA_IRQn = 20, /*!< 20 DMA */
64 I2C2_IRQn = 21, /*!< 21 I2C2 */
65 I2C3_IRQn = 22, /*!< 22 I2C3 */
66 PIN_INT0_IRQn = 24, /*!< 24 PIN_INT0 */
67 PIN_INT1_IRQn = 25, /*!< 25 PIN_INT1 */
68 PIN_INT2_IRQn = 26, /*!< 26 PIN_INT2 */
69 PIN_INT3_IRQn = 27, /*!< 27 PIN_INT3 */
70 PIN_INT4_IRQn = 28, /*!< 28 PIN_INT4 */
71 PIN_INT5_IRQn = 29, /*!< 29 PIN_INT5 */
72 PIN_INT6_IRQn = 30, /*!< 30 PIN_INT6 */
73 PIN_INT7_IRQn = 31 /*!< 31 PIN_INT7 */
74 } IRQn_Type;
75
76
77 /** @addtogroup Configuration_of_CMSIS
78 * @{
79 */
80
81
82 /* ================================================================================ */
83 /* ================ Processor and Core Peripheral Section ================ */
84 /* ================================================================================ */
85
86 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
87 #define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */
88 #define __MPU_PRESENT 0 /*!< MPU present or not */
89 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
90 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
91 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
92 /** @} */ /* End of group Configuration_of_CMSIS */
93
94 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
95 #include "system_LPC82x.h" /*!< LPC82x System */
96
97
98 /* ================================================================================ */
99 /* ================ Device Specific Peripheral Section ================ */
100 /* ================================================================================ */
101
102
103 /** @addtogroup Device_Peripheral_Registers
104 * @{
105 */
106
107
108 /* ------------------- Start of section using anonymous unions ------------------ */
109 #if defined(__CC_ARM)
110 #pragma push
111 #pragma anon_unions
112 #elif defined(__ICCARM__)
113 #pragma language=extended
114 #elif defined(__GNUC__)
115 /* anonymous unions are enabled by default */
116 #elif defined(__TMS470__)
117 /* anonymous unions are enabled by default */
118 #elif defined(__TASKING__)
119 #pragma warning 586
120 #else
121 #warning Not supported compiler type
122 #endif
123
124
125
126 /* ================================================================================ */
127 /* ================ WWDT ================ */
128 /* ================================================================================ */
129
130
131 /**
132 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
133 */
134
135 typedef struct { /*!< (@ 0x40000000) WWDT Structure */
136 __IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains
137 the basic mode and status of the Watchdog Timer. */
138 __IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit
139 register determines the time-out value. */
140 __O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA
141 followed by 0x55 to this register reloads the Watchdog timer
142 with the value contained in WDTC. */
143 __I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register
144 reads out the current value of the Watchdog timer. */
145 __I uint32_t RESERVED0;
146 __IO uint32_t WARNINT; /*!< (@ 0x40000014) Watchdog Warning Interrupt compare value. */
147 __IO uint32_t WINDOW; /*!< (@ 0x40000018) Watchdog Window compare value. */
148 } LPC_WWDT_Type;
149
150
151 /* ================================================================================ */
152 /* ================ MRT ================ */
153 /* ================================================================================ */
154
155
156 /**
157 * @brief Multi-Rate Timer (MRT) (MRT)
158 */
159
160 typedef struct { /*!< (@ 0x40004000) MRT Structure */
161 __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
162 is loaded into the TIMER0 register. */
163 __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
164 value of the down-counter. */
165 __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
166 the MRT0 modes. */
167 __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
168 __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
169 is loaded into the TIMER0 register. */
170 __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
171 value of the down-counter. */
172 __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
173 the MRT0 modes. */
174 __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
175 __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
176 is loaded into the TIMER0 register. */
177 __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
178 value of the down-counter. */
179 __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
180 the MRT0 modes. */
181 __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
182 __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
183 is loaded into the TIMER0 register. */
184 __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
185 value of the down-counter. */
186 __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
187 the MRT0 modes. */
188 __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
189 __I uint32_t RESERVED0[45];
190 __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
191 the number of the first idle channel. */
192 __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
193 } LPC_MRT_Type;
194
195
196 /* ================================================================================ */
197 /* ================ WKT ================ */
198 /* ================================================================================ */
199
200
201 /**
202 * @brief Self wake-up timer (WKT) (WKT)
203 */
204
205 typedef struct { /*!< (@ 0x40008000) WKT Structure */
206 __IO uint32_t CTRL; /*!< (@ 0x40008000) Self wake-up timer control register. */
207 __I uint32_t RESERVED0[2];
208 __IO uint32_t COUNT; /*!< (@ 0x4000800C) Counter register. */
209 } LPC_WKT_Type;
210
211
212 /* ================================================================================ */
213 /* ================ SWM ================ */
214 /* ================================================================================ */
215
216
217 /**
218 * @brief Switch matrix (SWM) (SWM)
219 */
220
221 typedef struct { /*!< (@ 0x4000C000) SWM Structure */
222 union {
223 __IO uint32_t PINASSIGN[12];
224 struct {
225 __IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions
226 U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
227 __IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions
228 U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
229 __IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions
230 U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
231 __IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function
232 U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
233 __IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions
234 SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
235 __IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions
236 SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
237 __IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions
238 SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
239 __IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions
240 SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
241 __IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions
242 SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
243 __IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions
244 SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
245 __IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions
246 I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
247 __IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions
248 ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
249 };
250 };
251 __I uint32_t RESERVED0[100];
252 __IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions
253 ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN,
254 VDDCMP. */
255 } LPC_SWM_Type;
256
257
258 /* ================================================================================ */
259 /* ================ ADC ================ */
260 /* ================================================================================ */
261
262
263 /**
264 * @brief 12-bit Analog-to-Digital Converter (ADC) (ADC)
265 */
266
267 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
268 __IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide
269 value, enable bits for each sequence and the A/D power-down
270 bit. */
271 __I uint32_t RESERVED0;
272 __IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls
273 triggering and channel selection for conversion sequence-A.
274 Also specifies interrupt mode for sequence-A. */
275 __IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls
276 triggering and channel selection for conversion sequence-B.
277 Also specifies interrupt mode for sequence-B. */
278 __IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register
279 contains the result of the most recent A/D conversion performed
280 under sequence-A */
281 __IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register
282 contains the result of the most recent A/D conversion performed
283 under sequence-B */
284 __I uint32_t RESERVED1[2];
285 __I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains
286 the result of the most recent conversion completed on channel
287 0. */
288 __I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains
289 the result of the most recent conversion completed on channel
290 0. */
291 __I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains
292 the result of the most recent conversion completed on channel
293 0. */
294 __I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains
295 the result of the most recent conversion completed on channel
296 0. */
297 __I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains
298 the result of the most recent conversion completed on channel
299 0. */
300 __I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains
301 the result of the most recent conversion completed on channel
302 0. */
303 __I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains
304 the result of the most recent conversion completed on channel
305 0. */
306 __I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains
307 the result of the most recent conversion completed on channel
308 0. */
309 __I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains
310 the result of the most recent conversion completed on channel
311 0. */
312 __I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains
313 the result of the most recent conversion completed on channel
314 0. */
315 __I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains
316 the result of the most recent conversion completed on channel
317 0. */
318 __I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains
319 the result of the most recent conversion completed on channel
320 0. */
321 __IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains
322 the lower threshold level for automatic threshold comparison
323 for any channels linked to threshold pair 0. */
324 __IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains
325 the lower threshold level for automatic threshold comparison
326 for any channels linked to threshold pair 1. */
327 __IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains
328 the upper threshold level for automatic threshold comparison
329 for any channels linked to threshold pair 0. */
330 __IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains
331 the upper threshold level for automatic threshold comparison
332 for any channels linked to threshold pair 1. */
333 __IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies
334 which set of threshold compare registers are to be used for
335 each channel */
336 __IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register
337 contains enable bits that enable the sequence-A, sequence-B,
338 threshold compare and data overrun interrupts to be generated. */
339 __IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt
340 request flags and the individual component overrun and threshold-compare
341 flags. (The overrun bits replicate information stored in the
342 result registers). */
343 __IO uint32_t TRM; /*!< (@ 0x4001C06C) ADC trim register. */
344 } LPC_ADC_Type;
345
346
347 /* ================================================================================ */
348 /* ================ PMU ================ */
349 /* ================================================================================ */
350
351
352 /**
353 * @brief Power Management Unit (PMU) (PMU)
354 */
355
356 typedef struct { /*!< (@ 0x40020000) PMU Structure */
357 __IO uint32_t PCON; /*!< (@ 0x40020000) Power control register */
358 __IO uint32_t GPREG0; /*!< (@ 0x40020004) General purpose register 0 */
359 __IO uint32_t GPREG1; /*!< (@ 0x40020008) General purpose register 0 */
360 __IO uint32_t GPREG2; /*!< (@ 0x4002000C) General purpose register 0 */
361 __IO uint32_t GPREG3; /*!< (@ 0x40020010) General purpose register 0 */
362 __IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes
363 bits for general purpose storage. */
364 } LPC_PMU_Type;
365
366
367 /* ================================================================================ */
368 /* ================ CMP ================ */
369 /* ================================================================================ */
370
371
372 /**
373 * @brief Analog comparator (CMP)
374 */
375
376 typedef struct { /*!< (@ 0x40024000) CMP Structure */
377 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
378 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
379 } LPC_CMP_Type;
380
381
382 /* ================================================================================ */
383 /* ================ DMATRIGMUX ================ */
384 /* ================================================================================ */
385
386
387 /**
388 * @brief DMA trigger mux (DMATRIGMUX)
389 */
390
391 typedef struct { /*!< (@ 0x40028000) DMATRIGMUX Structure */
392 __IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23
393 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
394 interrupts, and DMA requests. */
395 __IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23
396 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
397 interrupts, and DMA requests. */
398 __IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23
399 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
400 interrupts, and DMA requests. */
401 __IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23
402 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
403 interrupts, and DMA requests. */
404 __IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23
405 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
406 interrupts, and DMA requests. */
407 __IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23
408 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
409 interrupts, and DMA requests. */
410 __IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23
411 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
412 interrupts, and DMA requests. */
413 __IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23
414 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
415 interrupts, and DMA requests. */
416 __IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23
417 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
418 interrupts, and DMA requests. */
419 __IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23
420 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
421 interrupts, and DMA requests. */
422 __IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23
423 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
424 interrupts, and DMA requests. */
425 __IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23
426 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
427 interrupts, and DMA requests. */
428 __IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23
429 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
430 interrupts, and DMA requests. */
431 __IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23
432 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
433 interrupts, and DMA requests. */
434 __IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23
435 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
436 interrupts, and DMA requests. */
437 __IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23
438 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
439 interrupts, and DMA requests. */
440 __IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23
441 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
442 interrupts, and DMA requests. */
443 __IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23
444 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
445 interrupts, and DMA requests. */
446 } LPC_DMATRIGMUX_Type;
447
448
449 /* ================================================================================ */
450 /* ================ INPUTMUX ================ */
451 /* ================================================================================ */
452
453
454 /**
455 * @brief Input multiplexing (INPUTMUX)
456 */
457
458 typedef struct { /*!< (@ 0x4002C000) INPUTMUX Structure */
459 __IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20.
460 Selects from 18 DMA trigger outputs. */
461 __IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20.
462 Selects from 18 DMA trigger outputs. */
463 __I uint32_t RESERVED0[6];
464 __IO uint32_t SCT0_INMUX0; /*!< (@ 0x4002C020) Input mux register for SCT input 0 */
465 __IO uint32_t SCT0_INMUX1; /*!< (@ 0x4002C024) Input mux register for SCT input 0 */
466 __IO uint32_t SCT0_INMUX2; /*!< (@ 0x4002C028) Input mux register for SCT input 0 */
467 __IO uint32_t SCT0_INMUX3; /*!< (@ 0x4002C02C) Input mux register for SCT input 0 */
468 } LPC_INPUTMUX_Type;
469
470
471 /* ================================================================================ */
472 /* ================ FLASHCTRL ================ */
473 /* ================================================================================ */
474
475
476 /**
477 * @brief Flash controller (FLASHCTRL)
478 */
479
480 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
481 __I uint32_t RESERVED0[4];
482 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
483 __I uint32_t RESERVED1[3];
484 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
485 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
486 __I uint32_t RESERVED2;
487 __I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */
488 } LPC_FLASHCTRL_Type;
489
490
491 /* ================================================================================ */
492 /* ================ IOCON ================ */
493 /* ================================================================================ */
494
495
496 /**
497 * @brief I/O configuration (IOCON) (IOCON)
498 */
499
500 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
501 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
502 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
503 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
504 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET */
505 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
506 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK */
507 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO */
508 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the
509 pin configuration for the true open-drain pin. */
510 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the
511 pin configuration for the true open-drain pin. */
512 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
513 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
514 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_17 */
515 __I uint32_t RESERVED0;
516 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT */
517 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN */
518 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
519 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP */
520 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 */
521 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
522 __I uint32_t RESERVED1;
523 __IO uint32_t PIO0_28; /*!< (@ 0x40044050) I/O configuration for pin PIO0_28 */
524 __IO uint32_t PIO0_27; /*!< (@ 0x40044054) I/O configuration for pin PIO0_27 */
525 __IO uint32_t PIO0_26; /*!< (@ 0x40044058) I/O configuration for pin PIO0_26 */
526 __IO uint32_t PIO0_25; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_25 */
527 __IO uint32_t PIO0_24; /*!< (@ 0x40044060) I/O configuration for pin PIO0_24 */
528 __IO uint32_t PIO0_23; /*!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 */
529 __IO uint32_t PIO0_22; /*!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 */
530 __IO uint32_t PIO0_21; /*!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 */
531 __IO uint32_t PIO0_20; /*!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 */
532 __IO uint32_t PIO0_19; /*!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 */
533 __IO uint32_t PIO0_18; /*!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 */
534 } LPC_IOCON_Type;
535
536
537 /* ================================================================================ */
538 /* ================ SYSCON ================ */
539 /* ================================================================================ */
540
541
542 /**
543 * @brief System configuration (SYSCON) (SYSCON)
544 */
545
546 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
547 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
548 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
549 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
550 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
551 __I uint32_t RESERVED0[4];
552 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
553 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
554 __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */
555 __I uint32_t RESERVED1;
556 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
557 __I uint32_t RESERVED2[3];
558 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
559 __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
560 __I uint32_t RESERVED3[10];
561 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
562 __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
563 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
564 __I uint32_t RESERVED4;
565 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
566 __I uint32_t RESERVED5[4];
567 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048094) USART clock divider */
568 __I uint32_t RESERVED6[18];
569 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
570 __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
571 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
572 __I uint32_t RESERVED7;
573 __IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator
574 divider value */
575 __IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator
576 multiplier value */
577 __I uint32_t RESERVED8;
578 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
579 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
580 __I uint32_t RESERVED9[12];
581 __IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable
582 glitch filter */
583 __I uint32_t RESERVED10[6];
584 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
585 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
586 __I uint32_t RESERVED11[6];
587 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt
588 latency and determinism. */
589 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
590 union {
591 __IO uint32_t PINTSEL[8];
592 struct {
593 __IO uint32_t PINTSEL0; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
594 __IO uint32_t PINTSEL1; /*!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 */
595 __IO uint32_t PINTSEL2; /*!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 */
596 __IO uint32_t PINTSEL3; /*!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 */
597 __IO uint32_t PINTSEL4; /*!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 */
598 __IO uint32_t PINTSEL5; /*!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 */
599 __IO uint32_t PINTSEL6; /*!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 */
600 __IO uint32_t PINTSEL7; /*!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 */
601 };
602 };
603 __I uint32_t RESERVED12[27];
604 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 pin wake-up enable register */
605 __I uint32_t RESERVED13[3];
606 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register */
607 __I uint32_t RESERVED14[6];
608 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
609 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
610 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
611 __I uint32_t RESERVED15[111];
612 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
613 } LPC_SYSCON_Type;
614
615
616 /* ================================================================================ */
617 /* ================ I2C0 ================ */
618 /* ================================================================================ */
619
620
621 /**
622 * @brief I2C0-bus interface (I2C0)
623 */
624
625 typedef struct { /*!< (@ 0x40050000) I2C0 Structure */
626 __IO uint32_t CFG; /*!< (@ 0x40050000) Configuration for shared functions. */
627 __IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor
628 functions. */
629 __IO uint32_t INTENSET; /*!< (@ 0x40050008) Interrupt Enable Set and read register. */
630 __O uint32_t INTENCLR; /*!< (@ 0x4005000C) Interrupt Enable Clear register. */
631 __IO uint32_t TIMEOUT; /*!< (@ 0x40050010) Time-out value register. */
632 __IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This
633 determines what time increments are used for the MSTTIME and
634 SLVTIME registers. */
635 __I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave,
636 and Monitor functions. */
637 __I uint32_t RESERVED0;
638 __IO uint32_t MSTCTL; /*!< (@ 0x40050020) Master control register. */
639 __IO uint32_t MSTTIME; /*!< (@ 0x40050024) Master timing configuration. */
640 __IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data
641 register. */
642 __I uint32_t RESERVED1[5];
643 __IO uint32_t SLVCTL; /*!< (@ 0x40050040) Slave control register. */
644 __IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data
645 register. */
646 union {
647 __IO uint32_t SLVADR[4];
648 struct {
649 __IO uint32_t SLVADR0; /*!< (@ 0x40050048) Slave address 0. */
650 __IO uint32_t SLVADR1; /*!< (@ 0x4005004C) Slave address 0. */
651 __IO uint32_t SLVADR2; /*!< (@ 0x40050050) Slave address 0. */
652 __IO uint32_t SLVADR3; /*!< (@ 0x40050054) Slave address 0. */
653 };
654 };
655 __IO uint32_t SLVQUAL0; /*!< (@ 0x40050058) Slave Qualification for address 0. */
656 __I uint32_t RESERVED2[9];
657 __I uint32_t MONRXDAT; /*!< (@ 0x40050080) Monitor receiver data register. */
658 } LPC_I2C0_Type;
659
660
661 /* ================================================================================ */
662 /* ================ SPI0 ================ */
663 /* ================================================================================ */
664
665
666 /**
667 * @brief SPI0 (SPI0)
668 */
669
670 typedef struct { /*!< (@ 0x40058000) SPI0 Structure */
671 __IO uint32_t CFG; /*!< (@ 0x40058000) SPI Configuration register */
672 __IO uint32_t DLY; /*!< (@ 0x40058004) SPI Delay register */
673 __IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared
674 by writing a 1 to that bit position */
675 __IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete
676 value may be read from this register. Writing a 1 to any implemented
677 bit position causes that bit to be set. */
678 __O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any
679 implemented bit position causes the corresponding bit in INTENSET
680 to be cleared. */
681 __I uint32_t RXDAT; /*!< (@ 0x40058014) SPI Receive Data */
682 __IO uint32_t TXDATCTL; /*!< (@ 0x40058018) SPI Transmit Data with Control */
683 __IO uint32_t TXDAT; /*!< (@ 0x4005801C) SPI Transmit Data */
684 __IO uint32_t TXCTL; /*!< (@ 0x40058020) SPI Transmit Control */
685 __IO uint32_t DIV; /*!< (@ 0x40058024) SPI clock Divider */
686 __I uint32_t INTSTAT; /*!< (@ 0x40058028) SPI Interrupt Status */
687 } LPC_SPI0_Type;
688
689
690 /* ================================================================================ */
691 /* ================ USART0 ================ */
692 /* ================================================================================ */
693
694
695 /**
696 * @brief USART0 (USART0)
697 */
698
699 typedef struct { /*!< (@ 0x40064000) USART0 Structure */
700 __IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration
701 settings that typically are not changed during operation. */
702 __IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings
703 that are more likely to change during operation. */
704 __IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value
705 can be read here. Writing ones clears some bits in the register.
706 Some bits can be cleared by writing a 1 to them. */
707 __IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains
708 an individual interrupt enable bit for each potential USART
709 interrupt. A complete value may be read from this register.
710 Writing a 1 to any implemented bit position causes that bit
711 to be set. */
712 __O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing
713 any combination of bits in the INTENSET register. Writing a
714 1 to any implemented bit position causes the corresponding bit
715 to be cleared. */
716 __I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character
717 received. */
718 __I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines
719 the last character received with the current USART receive status.
720 Allows DMA or software to recover incoming data and status together. */
721 __IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted
722 is written here. */
723 __IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer
724 baud rate divisor value. */
725 __I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts
726 that are currently enabled. */
727 __IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous
728 communication. */
729 __IO uint32_t ADDR; /*!< (@ 0x4006402C) Address register for automatic address matching. */
730 } LPC_USART0_Type;
731
732
733 /* ================================================================================ */
734 /* ================ CRC ================ */
735 /* ================================================================================ */
736
737
738 /**
739 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
740 */
741
742 typedef struct { /*!< (@ 0x50000000) CRC Structure */
743 __IO uint32_t MODE; /*!< (@ 0x50000000) CRC mode register */
744 __IO uint32_t SEED; /*!< (@ 0x50000004) CRC seed register */
745
746 union {
747 __O uint32_t WR_DATA; /*!< (@ 0x50000008) CRC data register */
748 __I uint32_t SUM; /*!< (@ 0x50000008) CRC checksum register */
749 };
750 } LPC_CRC_Type;
751
752
753 /* ================================================================================ */
754 /* ================ SCT ================ */
755 /* ================================================================================ */
756
757
758 /**
759 * @brief State Configurable Timer (SCT) (SCT)
760 */
761
762 typedef struct { /*!< (@ 0x50004000) SCT Structure */
763 __IO uint32_t CONFIG; /*!< (@ 0x50004000) SCT configuration register */
764 __IO uint32_t CTRL; /*!< (@ 0x50004004) SCT control register */
765 __IO uint32_t LIMIT; /*!< (@ 0x50004008) SCT limit register */
766 __IO uint32_t HALT; /*!< (@ 0x5000400C) SCT halt condition register */
767 __IO uint32_t STOP; /*!< (@ 0x50004010) SCT stop condition register */
768 __IO uint32_t START; /*!< (@ 0x50004014) SCT start condition register */
769 __I uint32_t RESERVED0[10];
770 __IO uint32_t COUNT; /*!< (@ 0x50004040) SCT counter register */
771 __IO uint32_t STATE; /*!< (@ 0x50004044) SCT state register */
772 __I uint32_t INPUT; /*!< (@ 0x50004048) SCT input register */
773 __IO uint32_t REGMODE; /*!< (@ 0x5000404C) SCT match/capture registers mode register */
774 __IO uint32_t OUTPUT; /*!< (@ 0x50004050) SCT output register */
775 __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x50004054) SCT output counter direction control register */
776 __IO uint32_t RES; /*!< (@ 0x50004058) SCT conflict resolution register */
777 __IO uint32_t DMAREQ0; /*!< (@ 0x5000405C) SCT DMA request 0 register */
778 __IO uint32_t DMAREQ1; /*!< (@ 0x50004060) SCT DMA request 1 register */
779 __I uint32_t RESERVED1[35];
780 __IO uint32_t EVEN; /*!< (@ 0x500040F0) SCT event enable register */
781 __IO uint32_t EVFLAG; /*!< (@ 0x500040F4) SCT event flag register */
782 __IO uint32_t CONEN; /*!< (@ 0x500040F8) SCT conflict enable register */
783 __IO uint32_t CONFLAG; /*!< (@ 0x500040FC) SCT conflict flag register */
784
785 union {
786 union {
787 __IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to
788 7; REGMOD0 to REGMODE7 = 1 */
789 __IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0
790 to 7; REGMOD0 to REGMODE7 = 0 */
791 };
792
793 union {
794 __IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to
795 7; REGMOD0 to REGMODE7 = 1 */
796 __IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0
797 to 7; REGMOD0 to REGMODE7 = 0 */
798 };
799
800 union {
801 __IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to
802 7; REGMOD0 to REGMODE7 = 1 */
803 __IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0
804 to 7; REGMOD0 to REGMODE7 = 0 */
805 };
806
807 union {
808 __IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0
809 to 7; REGMOD0 to REGMODE7 = 0 */
810 __IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to
811 7; REGMOD0 to REGMODE7 = 1 */
812 };
813
814 union {
815 __IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to
816 7; REGMOD0 to REGMODE7 = 1 */
817 __IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0
818 to 7; REGMOD0 to REGMODE7 = 0 */
819 };
820
821 union {
822 __IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0
823 to 7; REGMOD0 to REGMODE7 = 0 */
824 __IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to
825 7; REGMOD0 to REGMODE7 = 1 */
826 };
827
828 union {
829 __IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to
830 7; REGMOD0 to REGMODE7 = 1 */
831 __IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0
832 to 7; REGMOD0 to REGMODE7 = 0 */
833 };
834
835 union {
836 __IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to
837 7; REGMOD0 to REGMODE7 = 1 */
838 __IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0
839 to 7; REGMOD0 to REGMODE7 = 0 */
840 };
841 __IO uint32_t CAP[8];
842 __IO uint32_t MATCH[8];
843 };
844 __I uint32_t RESERVED2[56];
845
846 union {
847 struct {
848 union {
849 __IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0
850 = 1 to REGMODE7 = 1 */
851 __IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0
852 = 0 to REGMODE7 = 0 */
853 };
854
855 union {
856 __IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0
857 = 1 to REGMODE7 = 1 */
858 __IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0
859 = 0 to REGMODE7 = 0 */
860 };
861
862 union {
863 __IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0
864 = 1 to REGMODE7 = 1 */
865 __IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0
866 = 0 to REGMODE7 = 0 */
867 };
868
869 union {
870 __IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0
871 = 0 to REGMODE7 = 0 */
872 __IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0
873 = 1 to REGMODE7 = 1 */
874 };
875
876 union {
877 __IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0
878 = 1 to REGMODE7 = 1 */
879 __IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0
880 = 0 to REGMODE7 = 0 */
881 };
882
883 union {
884 __IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0
885 = 1 to REGMODE7 = 1 */
886 __IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0
887 = 0 to REGMODE7 = 0 */
888 };
889
890 union {
891 __IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0
892 = 1 to REGMODE7 = 1 */
893 __IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0
894 = 0 to REGMODE7 = 0 */
895 };
896
897 union {
898 __IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0
899 = 1 to REGMODE7 = 1 */
900 __IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0
901 = 0 to REGMODE7 = 0 */
902 };
903 };
904 __IO uint32_t MATCHREL[8];
905 };
906 __I uint32_t RESERVED3[56];
907
908 union {
909 struct {
910 __IO uint32_t EV0_STATE; /*!< (@ 0x50004300) SCT event state register 0 */
911 __IO uint32_t EV0_CTRL; /*!< (@ 0x50004304) SCT event control register 0 */
912 __IO uint32_t EV1_STATE; /*!< (@ 0x50004308) SCT event state register 0 */
913 __IO uint32_t EV1_CTRL; /*!< (@ 0x5000430C) SCT event control register 0 */
914 __IO uint32_t EV2_STATE; /*!< (@ 0x50004310) SCT event state register 0 */
915 __IO uint32_t EV2_CTRL; /*!< (@ 0x50004314) SCT event control register 0 */
916 __IO uint32_t EV3_STATE; /*!< (@ 0x50004318) SCT event state register 0 */
917 __IO uint32_t EV3_CTRL; /*!< (@ 0x5000431C) SCT event control register 0 */
918 __IO uint32_t EV4_STATE; /*!< (@ 0x50004320) SCT event state register 0 */
919 __IO uint32_t EV4_CTRL; /*!< (@ 0x50004324) SCT event control register 0 */
920 __IO uint32_t EV5_STATE; /*!< (@ 0x50004328) SCT event state register 0 */
921 __IO uint32_t EV5_CTRL; /*!< (@ 0x5000432C) SCT event control register 0 */
922 __IO uint32_t EV6_STATE; /*!< (@ 0x50004330) SCT event state register 0 */
923 __IO uint32_t EV6_CTRL; /*!< (@ 0x50004334) SCT event control register 0 */
924 __IO uint32_t EV7_STATE; /*!< (@ 0x50004338) SCT event state register 0 */
925 __IO uint32_t EV7_CTRL; /*!< (@ 0x5000433C) SCT event control register 0 */
926 };
927 __IO struct {
928 uint32_t STATE;
929 uint32_t CTRL;
930 } EVENT[8];
931 };
932
933 __I uint32_t RESERVED4[112];
934
935 union {
936 struct {
937 __IO uint32_t OUT0_SET; /*!< (@ 0x50004500) SCT output 0 set register */
938 __IO uint32_t OUT0_CLR; /*!< (@ 0x50004504) SCT output 0 clear register */
939 __IO uint32_t OUT1_SET; /*!< (@ 0x50004508) SCT output 0 set register */
940 __IO uint32_t OUT1_CLR; /*!< (@ 0x5000450C) SCT output 0 clear register */
941 __IO uint32_t OUT2_SET; /*!< (@ 0x50004510) SCT output 0 set register */
942 __IO uint32_t OUT2_CLR; /*!< (@ 0x50004514) SCT output 0 clear register */
943 __IO uint32_t OUT3_SET; /*!< (@ 0x50004518) SCT output 0 set register */
944 __IO uint32_t OUT3_CLR; /*!< (@ 0x5000451C) SCT output 0 clear register */
945 __IO uint32_t OUT4_SET; /*!< (@ 0x50004520) SCT output 0 set register */
946 __IO uint32_t OUT4_CLR; /*!< (@ 0x50004524) SCT output 0 clear register */
947 __IO uint32_t OUT5_SET; /*!< (@ 0x50004528) SCT output 0 set register */
948 __IO uint32_t OUT5_CLR; /*!< (@ 0x5000452C) SCT output 0 clear register */
949 };
950 __IO struct {
951 uint32_t SET;
952 uint32_t CLR;
953 } OUT[6];
954 };
955
956 } LPC_SCT_Type;
957
958
959 /* ================================================================================ */
960 /* ================ DMA ================ */
961 /* ================================================================================ */
962
963
964 /**
965 * @brief DMA controller (DMA)
966 */
967
968 typedef struct { /*!< (@ 0x50008000) DMA Structure */
969 __IO uint32_t CTRL; /*!< (@ 0x50008000) DMA control. */
970 __I uint32_t INTSTAT; /*!< (@ 0x50008004) Interrupt status. */
971 __IO uint32_t SRAMBASE; /*!< (@ 0x50008008) SRAM address of the channel configuration table. */
972 __I uint32_t RESERVED0[5];
973 __IO uint32_t ENABLESET0; /*!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. */
974 __I uint32_t RESERVED1;
975 __O uint32_t ENABLECLR0; /*!< (@ 0x50008028) Channel Enable Clear for all DMA channels. */
976 __I uint32_t RESERVED2;
977 __I uint32_t ACTIVE0; /*!< (@ 0x50008030) Channel Active status for all DMA channels. */
978 __I uint32_t RESERVED3;
979 __I uint32_t BUSY0; /*!< (@ 0x50008038) Channel Busy status for all DMA channels. */
980 __I uint32_t RESERVED4;
981 __IO uint32_t ERRINT0; /*!< (@ 0x50008040) Error Interrupt status for all DMA channels. */
982 __I uint32_t RESERVED5;
983 __IO uint32_t INTENSET0; /*!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. */
984 __I uint32_t RESERVED6;
985 __O uint32_t INTENCLR0; /*!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. */
986 __I uint32_t RESERVED7;
987 __IO uint32_t INTA0; /*!< (@ 0x50008058) Interrupt A status for all DMA channels. */
988 __I uint32_t RESERVED8;
989 __IO uint32_t INTB0; /*!< (@ 0x50008060) Interrupt B status for all DMA channels. */
990 __I uint32_t RESERVED9;
991 __O uint32_t SETVALID0; /*!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. */
992 __I uint32_t RESERVED10;
993 __O uint32_t SETTRIG0; /*!< (@ 0x50008070) Set Trigger control bits for all DMA channels. */
994 __I uint32_t RESERVED11;
995 __O uint32_t ABORT0; /*!< (@ 0x50008078) Channel Abort control for all DMA channels. */
996 __I uint32_t RESERVED12[225];
997 __IO uint32_t CFG0; /*!< (@ 0x50008400) Configuration register for DMA channel 0. */
998 __I uint32_t CTLSTAT0; /*!< (@ 0x50008404) Control and status register for DMA channel 0. */
999 __IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel
1000 0. */
1001 __I uint32_t RESERVED13;
1002 __IO uint32_t CFG1; /*!< (@ 0x50008410) Configuration register for DMA channel 0. */
1003 __I uint32_t CTLSTAT1; /*!< (@ 0x50008414) Control and status register for DMA channel 0. */
1004 __IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel
1005 0. */
1006 __I uint32_t RESERVED14;
1007 __IO uint32_t CFG2; /*!< (@ 0x50008420) Configuration register for DMA channel 0. */
1008 __I uint32_t CTLSTAT2; /*!< (@ 0x50008424) Control and status register for DMA channel 0. */
1009 __IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel
1010 0. */
1011 __I uint32_t RESERVED15;
1012 __IO uint32_t CFG3; /*!< (@ 0x50008430) Configuration register for DMA channel 0. */
1013 __I uint32_t CTLSTAT3; /*!< (@ 0x50008434) Control and status register for DMA channel 0. */
1014 __IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel
1015 0. */
1016 __I uint32_t RESERVED16;
1017 __IO uint32_t CFG4; /*!< (@ 0x50008440) Configuration register for DMA channel 0. */
1018 __I uint32_t CTLSTAT4; /*!< (@ 0x50008444) Control and status register for DMA channel 0. */
1019 __IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel
1020 0. */
1021 __I uint32_t RESERVED17;
1022 __IO uint32_t CFG5; /*!< (@ 0x50008450) Configuration register for DMA channel 0. */
1023 __I uint32_t CTLSTAT5; /*!< (@ 0x50008454) Control and status register for DMA channel 0. */
1024 __IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel
1025 0. */
1026 __I uint32_t RESERVED18;
1027 __IO uint32_t CFG6; /*!< (@ 0x50008460) Configuration register for DMA channel 0. */
1028 __I uint32_t CTLSTAT6; /*!< (@ 0x50008464) Control and status register for DMA channel 0. */
1029 __IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel
1030 0. */
1031 __I uint32_t RESERVED19;
1032 __IO uint32_t CFG7; /*!< (@ 0x50008470) Configuration register for DMA channel 0. */
1033 __I uint32_t CTLSTAT7; /*!< (@ 0x50008474) Control and status register for DMA channel 0. */
1034 __IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel
1035 0. */
1036 __I uint32_t RESERVED20;
1037 __IO uint32_t CFG8; /*!< (@ 0x50008480) Configuration register for DMA channel 0. */
1038 __I uint32_t CTLSTAT8; /*!< (@ 0x50008484) Control and status register for DMA channel 0. */
1039 __IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel
1040 0. */
1041 __I uint32_t RESERVED21;
1042 __IO uint32_t CFG9; /*!< (@ 0x50008490) Configuration register for DMA channel 0. */
1043 __I uint32_t CTLSTAT9; /*!< (@ 0x50008494) Control and status register for DMA channel 0. */
1044 __IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel
1045 0. */
1046 __I uint32_t RESERVED22;
1047 __IO uint32_t CFG10; /*!< (@ 0x500084A0) Configuration register for DMA channel 0. */
1048 __I uint32_t CTLSTAT10; /*!< (@ 0x500084A4) Control and status register for DMA channel 0. */
1049 __IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel
1050 0. */
1051 __I uint32_t RESERVED23;
1052 __IO uint32_t CFG11; /*!< (@ 0x500084B0) Configuration register for DMA channel 0. */
1053 __I uint32_t CTLSTAT11; /*!< (@ 0x500084B4) Control and status register for DMA channel 0. */
1054 __IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel
1055 0. */
1056 __I uint32_t RESERVED24;
1057 __IO uint32_t CFG12; /*!< (@ 0x500084C0) Configuration register for DMA channel 0. */
1058 __I uint32_t CTLSTAT12; /*!< (@ 0x500084C4) Control and status register for DMA channel 0. */
1059 __IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel
1060 0. */
1061 __I uint32_t RESERVED25;
1062 __IO uint32_t CFG13; /*!< (@ 0x500084D0) Configuration register for DMA channel 0. */
1063 __I uint32_t CTLSTAT13; /*!< (@ 0x500084D4) Control and status register for DMA channel 0. */
1064 __IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel
1065 0. */
1066 __I uint32_t RESERVED26;
1067 __IO uint32_t CFG14; /*!< (@ 0x500084E0) Configuration register for DMA channel 0. */
1068 __I uint32_t CTLSTAT14; /*!< (@ 0x500084E4) Control and status register for DMA channel 0. */
1069 __IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel
1070 0. */
1071 __I uint32_t RESERVED27;
1072 __IO uint32_t CFG15; /*!< (@ 0x500084F0) Configuration register for DMA channel 0. */
1073 __I uint32_t CTLSTAT15; /*!< (@ 0x500084F4) Control and status register for DMA channel 0. */
1074 __IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel
1075 0. */
1076 __I uint32_t RESERVED28;
1077 __IO uint32_t CFG16; /*!< (@ 0x50008500) Configuration register for DMA channel 0. */
1078 __I uint32_t CTLSTAT16; /*!< (@ 0x50008504) Control and status register for DMA channel 0. */
1079 __IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel
1080 0. */
1081 __I uint32_t RESERVED29;
1082 __IO uint32_t CFG17; /*!< (@ 0x50008510) Configuration register for DMA channel 0. */
1083 __I uint32_t CTLSTAT17; /*!< (@ 0x50008514) Control and status register for DMA channel 0. */
1084 __IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel
1085 0. */
1086 } LPC_DMA_Type;
1087
1088
1089 /* ================================================================================ */
1090 /* ================ GPIO_PORT ================ */
1091 /* ================================================================================ */
1092
1093
1094 /**
1095 * @brief General Purpose I/O port (GPIO) (GPIO_PORT)
1096 */
1097
1098 typedef struct { /*!< (@ 0xA0000000) GPIO_PORT Structure */
1099 __IO uint8_t B0; /*!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1100 __IO uint8_t B1; /*!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1101 __IO uint8_t B2; /*!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1102 __IO uint8_t B3; /*!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1103 __IO uint8_t B4; /*!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1104 __IO uint8_t B5; /*!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1105 __IO uint8_t B6; /*!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1106 __IO uint8_t B7; /*!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1107 __IO uint8_t B8; /*!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1108 __IO uint8_t B9; /*!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1109 __IO uint8_t B10; /*!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1110 __IO uint8_t B11; /*!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1111 __IO uint8_t B12; /*!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1112 __IO uint8_t B13; /*!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1113 __IO uint8_t B14; /*!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1114 __IO uint8_t B15; /*!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1115 __IO uint8_t B16; /*!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1116 __IO uint8_t B17; /*!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1117 __IO uint8_t B18; /*!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1118 __IO uint8_t B19; /*!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1119 __IO uint8_t B20; /*!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1120 __IO uint8_t B21; /*!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1121 __IO uint8_t B22; /*!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1122 __IO uint8_t B23; /*!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1123 __IO uint8_t B24; /*!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1124 __IO uint8_t B25; /*!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1125 __IO uint8_t B26; /*!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1126 __IO uint8_t B27; /*!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1127 __IO uint8_t B28; /*!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
1128 __I uint8_t RESERVED0[4067];
1129 __IO uint32_t W0; /*!< (@ 0xA0001000) Word pin registers port 0 */
1130 __IO uint32_t W1; /*!< (@ 0xA0001004) Word pin registers port 0 */
1131 __IO uint32_t W2; /*!< (@ 0xA0001008) Word pin registers port 0 */
1132 __IO uint32_t W3; /*!< (@ 0xA000100C) Word pin registers port 0 */
1133 __IO uint32_t W4; /*!< (@ 0xA0001010) Word pin registers port 0 */
1134 __IO uint32_t W5; /*!< (@ 0xA0001014) Word pin registers port 0 */
1135 __IO uint32_t W6; /*!< (@ 0xA0001018) Word pin registers port 0 */
1136 __IO uint32_t W7; /*!< (@ 0xA000101C) Word pin registers port 0 */
1137 __IO uint32_t W8; /*!< (@ 0xA0001020) Word pin registers port 0 */
1138 __IO uint32_t W9; /*!< (@ 0xA0001024) Word pin registers port 0 */
1139 __IO uint32_t W10; /*!< (@ 0xA0001028) Word pin registers port 0 */
1140 __IO uint32_t W11; /*!< (@ 0xA000102C) Word pin registers port 0 */
1141 __IO uint32_t W12; /*!< (@ 0xA0001030) Word pin registers port 0 */
1142 __IO uint32_t W13; /*!< (@ 0xA0001034) Word pin registers port 0 */
1143 __IO uint32_t W14; /*!< (@ 0xA0001038) Word pin registers port 0 */
1144 __IO uint32_t W15; /*!< (@ 0xA000103C) Word pin registers port 0 */
1145 __IO uint32_t W16; /*!< (@ 0xA0001040) Word pin registers port 0 */
1146 __IO uint32_t W17; /*!< (@ 0xA0001044) Word pin registers port 0 */
1147 __IO uint32_t W18; /*!< (@ 0xA0001048) Word pin registers port 0 */
1148 __IO uint32_t W19; /*!< (@ 0xA000104C) Word pin registers port 0 */
1149 __IO uint32_t W20; /*!< (@ 0xA0001050) Word pin registers port 0 */
1150 __IO uint32_t W21; /*!< (@ 0xA0001054) Word pin registers port 0 */
1151 __IO uint32_t W22; /*!< (@ 0xA0001058) Word pin registers port 0 */
1152 __IO uint32_t W23; /*!< (@ 0xA000105C) Word pin registers port 0 */
1153 __IO uint32_t W24; /*!< (@ 0xA0001060) Word pin registers port 0 */
1154 __IO uint32_t W25; /*!< (@ 0xA0001064) Word pin registers port 0 */
1155 __IO uint32_t W26; /*!< (@ 0xA0001068) Word pin registers port 0 */
1156 __IO uint32_t W27; /*!< (@ 0xA000106C) Word pin registers port 0 */
1157 __IO uint32_t W28; /*!< (@ 0xA0001070) Word pin registers port 0 */
1158 __I uint32_t RESERVED1[995];
1159 __IO uint32_t DIR0; /*!< (@ 0xA0002000) Direction registers port 0 */
1160 __I uint32_t RESERVED2[31];
1161 __IO uint32_t MASK0; /*!< (@ 0xA0002080) Mask register port 0 */
1162 __I uint32_t RESERVED3[31];
1163 __IO uint32_t PIN0; /*!< (@ 0xA0002100) Port pin register port 0 */
1164 __I uint32_t RESERVED4[31];
1165 __IO uint32_t MPIN0; /*!< (@ 0xA0002180) Masked port register port 0 */
1166 __I uint32_t RESERVED5[31];
1167 __IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits
1168 for port 0 */
1169 __I uint32_t RESERVED6[31];
1170 __O uint32_t CLR0; /*!< (@ 0xA0002280) Clear port 0 */
1171 __I uint32_t RESERVED7[31];
1172 __O uint32_t NOT0; /*!< (@ 0xA0002300) Toggle port 0 */
1173 __I uint32_t RESERVED8[31];
1174 __O uint32_t DIRSET0; /*!< (@ 0xA0002380) Set pin direction bits for port 0. */
1175 __I uint32_t RESERVED9[31];
1176 __O uint32_t DIRCLR0; /*!< (@ 0xA0002400) Clear pin direction bits for port 0. */
1177 __I uint32_t RESERVED10[31];
1178 __O uint32_t DIRNOT0; /*!< (@ 0xA0002480) Toggle pin direction bits for port 0. */
1179 } LPC_GPIO_PORT_Type;
1180
1181
1182 /* ================================================================================ */
1183 /* ================ PIN_INT ================ */
1184 /* ================================================================================ */
1185
1186
1187 /**
1188 * @brief Pin interrupt and pattern match engine (PIN_INT)
1189 */
1190
1191 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
1192 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
1193 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt
1194 enable register */
1195 __O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set
1196 register */
1197 __O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt
1198 clear register */
1199 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt
1200 enable register */
1201 __O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt
1202 set register */
1203 __O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt
1204 clear register */
1205 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin interrupt rising edge register */
1206 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin interrupt falling edge register */
1207 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin interrupt status register */
1208 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
1209 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source
1210 register */
1211 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration
1212 register */
1213 } LPC_PIN_INT_Type;
1214
1215
1216 /* -------------------- End of section using anonymous unions ------------------- */
1217 #if defined(__CC_ARM)
1218 #pragma pop
1219 #elif defined(__ICCARM__)
1220 /* leave anonymous unions enabled */
1221 #elif defined(__GNUC__)
1222 /* anonymous unions are enabled by default */
1223 #elif defined(__TMS470__)
1224 /* anonymous unions are enabled by default */
1225 #elif defined(__TASKING__)
1226 #pragma warning restore
1227 #else
1228 #warning Not supported compiler type
1229 #endif
1230
1231
1232
1233
1234 /* ================================================================================ */
1235 /* ================ Peripheral memory map ================ */
1236 /* ================================================================================ */
1237
1238 #define LPC_WWDT_BASE 0x40000000UL
1239 #define LPC_MRT_BASE 0x40004000UL
1240 #define LPC_WKT_BASE 0x40008000UL
1241 #define LPC_SWM_BASE 0x4000C000UL
1242 #define LPC_ADC_BASE 0x4001C000UL
1243 #define LPC_PMU_BASE 0x40020000UL
1244 #define LPC_CMP_BASE 0x40024000UL
1245 #define LPC_DMATRIGMUX_BASE 0x40028000UL
1246 #define LPC_INPUTMUX_BASE 0x4002C000UL
1247 #define LPC_FLASHCTRL_BASE 0x40040000UL
1248 #define LPC_IOCON_BASE 0x40044000UL
1249 #define LPC_SYSCON_BASE 0x40048000UL
1250 #define LPC_I2C0_BASE 0x40050000UL
1251 #define LPC_I2C1_BASE 0x40054000UL
1252 #define LPC_SPI0_BASE 0x40058000UL
1253 #define LPC_SPI1_BASE 0x4005C000UL
1254 #define LPC_USART0_BASE 0x40064000UL
1255 #define LPC_USART1_BASE 0x40068000UL
1256 #define LPC_USART2_BASE 0x4006C000UL
1257 #define LPC_I2C2_BASE 0x40070000UL
1258 #define LPC_I2C3_BASE 0x40074000UL
1259 #define LPC_CRC_BASE 0x50000000UL
1260 #define LPC_SCT_BASE 0x50004000UL
1261 #define LPC_DMA_BASE 0x50008000UL
1262 #define LPC_GPIO_PORT_BASE 0xA0000000UL
1263 #define LPC_PIN_INT_BASE 0xA0004000UL
1264
1265
1266 /* ================================================================================ */
1267 /* ================ Peripheral declaration ================ */
1268 /* ================================================================================ */
1269
1270 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
1271 #define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
1272 #define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE)
1273 #define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
1274 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
1275 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
1276 #define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE)
1277 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
1278 #define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE)
1279 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
1280 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
1281 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
1282 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
1283 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
1284 #define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
1285 #define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
1286 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
1287 #define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
1288 #define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
1289 #define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE)
1290 #define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE)
1291 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
1292 #define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
1293 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
1294 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
1295 #define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE)
1296
1297
1298 /** @} */ /* End of group Device_Peripheral_Registers */
1299 /** @} */ /* End of group LPC82x */
1300 /** @} */ /* End of group (null) */
1301
1302 #ifdef __cplusplus
1303 }
1304 #endif
1305
1306
1307 #endif /* LPC82x_H */
1308
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