tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f0xx_hal_adc.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    11-December-2014
   7   * @brief   Header file containing functions prototypes of ADC HAL library.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
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  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F0xx_HAL_ADC_H
  40 #define __STM32F0xx_HAL_ADC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f0xx_hal_def.h"
  48
  49 /** @addtogroup STM32F0xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup ADC
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup ADC_Exported_Types ADC Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  Structure definition of ADC initialization and regular group
  64   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
  65   *         ADC state can be either:
  66   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler')
  67    *         - For all parameters except 'ClockPrescaler': ADC enabled without conversion on going on regular group.
  68   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
  69   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
  70   */
  71 typedef struct
  72 {
  73   uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler.
  74                                        This parameter can be a value of @ref ADC_ClockPrescaler
  75                                        Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
  76                                        Note: This parameter can be modified only if the ADC is disabled */
  77   uint32_t Resolution;            /*!< Configures the ADC resolution.
  78                                        This parameter can be a value of @ref ADC_Resolution */
  79   uint32_t DataAlign;             /*!< Specifies whether the ADC data  alignment is left or right.
  80                                        This parameter can be a value of @ref ADC_Data_align */
  81   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular group.
  82                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
  83                                        Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
  84                                        If only 1 channel is set: Conversion is performed in single mode.
  85                                        If several channels are set:  Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
  86                                                                      Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
  87                                        This parameter can be a value of @ref ADC_Scan_mode */
  88   uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
  89                                        This parameter can be a value of @ref ADC_EOCSelection. */
  90   uint32_t LowPowerAutoWait;      /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
  91                                        conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
  92                                        This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
  93                                        This parameter can be set to ENABLE or DISABLE.
  94                                        Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
  95                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
  96                                              and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */
  97   uint32_t LowPowerAutoPowerOff;  /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
  98                                        This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
  99                                        This parameter can be set to ENABLE or DISABLE.
 100                                        Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
 101   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
 102                                        after the selected trigger occurred (software start or external trigger).
 103                                        This parameter can be set to ENABLE or DISABLE. */
 104   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
 105                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
 106                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
 107                                        This parameter can be set to ENABLE or DISABLE
 108                                        Note: Number of discontinuous ranks increment is fixed to one-by-one. */
 109   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
 110                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
 111                                        This parameter can be a value of @ref ADC_External_trigger_source_Regular */
 112   uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
 113                                        If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
 114                                        This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
 115   uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
 116                                        or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
 117                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
 118                                        This parameter can be set to ENABLE or DISABLE. */
 119   uint32_t Overrun;               /*!< Select the behaviour in case of overrun: data preserved or overwritten
 120                                        This parameter has an effect on regular group only, including in DMA mode.
 121                                        This parameter can be a value of @ref ADC_Overrun */
 122 }ADC_InitTypeDef;
 123
 124 /**
 125   * @brief  Structure definition of ADC channel for regular group
 126   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
 127   *         ADC state can be either:
 128   *          - For all parameters: ADC disabled or enabled without conversion on going on regular group.
 129   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
 130   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
 131   */
 132 typedef struct
 133 {
 134   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
 135                                         This parameter can be a value of @ref ADC_channels
 136                                         Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
 137   uint32_t Rank;                   /*!< Add or remove the channel from ADC regular group sequencer.
 138                                         On STM32F0 devices, rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
 139                                         Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
 140                                         This parameter can be a value of @ref ADC_rank */
 141   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
 142                                         Unit: ADC clock cycles
 143                                         Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
 144                                         This parameter can be a value of @ref ADC_sampling_times
 145                                         Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set.
 146                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
 147                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
 148                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
 149 }ADC_ChannelConfTypeDef;
 150
 151 /**
 152   * @brief  Structure definition of ADC analog watchdog
 153   * @note   The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
 154   *         ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group.
 155   */
 156 typedef struct
 157 {
 158   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode: single/all/none channels.
 159                                    This parameter can be a value of @ref ADC_analog_watchdog_mode. */
 160   uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
 161                                    This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
 162                                    This parameter can be a value of @ref ADC_channels. */
 163   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
 164                                    This parameter can be set to ENABLE or DISABLE */
 165   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
 166                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
 167   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
 168                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
 169 }ADC_AnalogWDGConfTypeDef;
 170
 171 /**
 172   * @brief  HAL ADC state machine: ADC States structure definition
 173   */
 174 typedef enum
 175 {
 176   HAL_ADC_STATE_RESET                   = 0x00,    /*!< ADC not yet initialized or disabled */
 177   HAL_ADC_STATE_READY                   = 0x01,    /*!< ADC peripheral ready for use */
 178   HAL_ADC_STATE_BUSY                    = 0x02,    /*!< An internal process is ongoing */
 179   HAL_ADC_STATE_BUSY_REG                = 0x12,    /*!< Regular conversion is ongoing */
 180   HAL_ADC_STATE_BUSY_INJ                = 0x22,    /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
 181   HAL_ADC_STATE_BUSY_INJ_REG            = 0x32,    /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
 182   HAL_ADC_STATE_TIMEOUT                 = 0x03,    /*!< Timeout state */
 183   HAL_ADC_STATE_ERROR                   = 0x04,    /*!< ADC state error */
 184   HAL_ADC_STATE_EOC                     = 0x05,    /*!< Conversion is completed */
 185   HAL_ADC_STATE_EOC_REG                 = 0x15,    /*!< Regular conversion is completed */
 186   HAL_ADC_STATE_EOC_INJ                 = 0x25,    /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
 187   HAL_ADC_STATE_EOC_INJ_REG             = 0x35,    /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
 188   HAL_ADC_STATE_AWD                     = 0x06,    /*!< ADC state analog watchdog */
 189   HAL_ADC_STATE_AWD2                    = 0x07,    /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */
 190   HAL_ADC_STATE_AWD3                    = 0x08,    /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */
 191 }HAL_ADC_StateTypeDef;
 192
 193 /**
 194   * @brief  ADC handle Structure definition
 195   */
 196 typedef struct
 197 {
 198   ADC_TypeDef                   *Instance;              /*!< Register base address */
 199
 200   ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
 201
 202   __IO uint32_t                 NbrOfConversionRank ;   /*!< ADC conversion rank counter */
 203
 204   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
 205
 206   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
 207
 208   __IO HAL_ADC_StateTypeDef     State;                  /*!< ADC communication state */
 209
 210   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
 211 }ADC_HandleTypeDef;
 212 /**
 213   * @}
 214   */
 215
 216
 217
 218 /* Exported constants --------------------------------------------------------*/
 219
 220 /** @defgroup ADC_Exported_Constants ADC Exported Constants
 221   * @{
 222   */
 223
 224 /** @defgroup ADC_Error_Code ADC Error Code
 225   * @{
 226   */
 227 #define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
 228 #define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking,
 229                                                           enable/disable, erroneous state                       */
 230 #define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
 231 #define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
 232
 233 /**
 234   * @}
 235   */
 236
 237 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
 238   * @{
 239   */
 240 #define ADC_CLOCK_ASYNC               ((uint32_t)0x00000000)          /*!< ADC asynchronous clock derived from ADC dedicated HSI */
 241
 242 #define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC_CFGR2_CKMODE_0)  /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
 243 #define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC_CFGR2_CKMODE_1)  /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
 244
 245 #define ADC_CLOCKPRESCALER_PCLK_DIV2   ADC_CLOCK_SYNC_PCLK_DIV2   /* Obsolete naming, kept for compatibility with some other devices */
 246 #define ADC_CLOCKPRESCALER_PCLK_DIV4   ADC_CLOCK_SYNC_PCLK_DIV4   /* Obsolete naming, kept for compatibility with some other devices */
 247
 248 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC)          || \
 249                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
 250                                           ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4)   )
 251
 252 /**
 253   * @}
 254   */
 255
 256 /** @defgroup ADC_Resolution ADC Resolution
 257   * @{
 258   */
 259 #define ADC_RESOLUTION12b      ((uint32_t)0x00000000)           /*!<  ADC 12-bit resolution */
 260 #define ADC_RESOLUTION10b      ((uint32_t)ADC_CFGR1_RES_0)      /*!<  ADC 10-bit resolution */
 261 #define ADC_RESOLUTION8b       ((uint32_t)ADC_CFGR1_RES_1)      /*!<  ADC 8-bit resolution */
 262 #define ADC_RESOLUTION6b       ((uint32_t)ADC_CFGR1_RES)        /*!<  ADC 6-bit resolution */
 263
 264 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
 265                                        ((RESOLUTION) == ADC_RESOLUTION10b) || \
 266                                        ((RESOLUTION) == ADC_RESOLUTION8b)  || \
 267                                        ((RESOLUTION) == ADC_RESOLUTION6b)    )
 268 /**
 269   * @}
 270   */
 271
 272 /** @defgroup ADC_Data_align ADC Data_align
 273   * @{
 274   */
 275 #define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
 276 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CFGR1_ALIGN)
 277
 278 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
 279                                   ((ALIGN) == ADC_DATAALIGN_LEFT)    )
 280 /**
 281   * @}
 282   */
 283
 284 /** @defgroup ADC_Scan_mode ADC Scan mode
 285   * @{
 286   */
 287 /* Note: Scan mode values must be compatible with other STM32 devices having  */
 288 /*       a configurable sequencer.                                            */
 289 /*       Scan direction setting values are defined by taking in account       */
 290 /*       already defined values for other STM32 devices:                      */
 291 /*         ADC_SCAN_DISABLE         ((uint32_t)0x00000000)                    */
 292 /*         ADC_SCAN_ENABLE          ((uint32_t)0x00000001)                    */
 293 /*       Scan direction forward is considered as default setting equivalent   */
 294 /*       to scan enable.                                                      */
 295 /*       Scan direction backward is considered as additional setting.         */
 296 /*       In case of migration from another STM32 device, the user will be     */
 297 /*       warned of change of setting choices with assert check.               */
 298 #define ADC_SCAN_DIRECTION_FORWARD        ((uint32_t)0x00000001)        /*!< Scan direction forward: from channel 0 to channel 18 */
 299 #define ADC_SCAN_DIRECTION_BACKWARD       ((uint32_t)0x00000002)        /*!< Scan direction backward: from channel 18 to channel 0 */
 300
 301 #define ADC_SCAN_ENABLE         ADC_SCAN_DIRECTION_FORWARD       /* For compatibility with other STM32 devices */
 302
 303 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
 304                                      ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD)  )
 305 /**
 306   * @}
 307   */
 308
 309 /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
 310   * @{
 311   */
 312 #define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
 313 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR1_EXTEN_0)
 314 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR1_EXTEN_1)
 315 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR1_EXTEN)
 316
 317 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
 318                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
 319                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
 320                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
 321 /**
 322   * @}
 323   */
 324
 325 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
 326   * @{
 327   */
 328 /* List of external triggers with generic trigger name, sorted by trigger     */
 329 /* name:                                                                      */
 330
 331 /* External triggers of regular group for ADC1 */
 332 #define ADC_EXTERNALTRIGCONV_T1_TRGO        ADC1_2_EXTERNALTRIG_T1_TRGO
 333 #define ADC_EXTERNALTRIGCONV_T1_CC4         ADC1_2_EXTERNALTRIG_T1_CC4
 334 #define ADC_EXTERNALTRIGCONV_T2_TRGO        ADC1_2_EXTERNALTRIG_T2_TRGO
 335 #define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
 336 #define ADC_EXTERNALTRIGCONV_T15_TRGO       ADC1_2_EXTERNALTRIG_T15_TRGO
 337 #define ADC_SOFTWARE_START                  ((uint32_t)0x00000010)
 338
 339 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
 340                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4)   || \
 341                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
 342                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
 343                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
 344                                  ((REGTRIG) == ADC_SOFTWARE_START)              )
 345 /**
 346   * @}
 347   */
 348
 349 /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
 350   * @{
 351   */
 352
 353 /* List of external triggers of regular group for ADC1:                       */
 354 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
 355 #define ADC1_2_EXTERNALTRIG_T1_TRGO           ((uint32_t)0x00000000)
 356 #define ADC1_2_EXTERNALTRIG_T1_CC4            ((uint32_t)ADC_CFGR1_EXTSEL_0)
 357 #define ADC1_2_EXTERNALTRIG_T2_TRGO           ((uint32_t)ADC_CFGR1_EXTSEL_1)
 358 #define ADC1_2_EXTERNALTRIG_T3_TRGO           ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0))
 359 #define ADC1_2_EXTERNALTRIG_T15_TRGO          ((uint32_t)ADC_CFGR1_EXTSEL_2)
 360
 361 /**
 362   * @}
 363   */
 364
 365 /** @defgroup ADC_EOCSelection ADC EOCSelection
 366   * @{
 367   */
 368 #define EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)
 369 #define EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)
 370 #define EOC_SINGLE_SEQ_CONV     ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))  /*!< reserved for future use */
 371
 372 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV)    || \
 373                                              ((EOC_SELECTION) == EOC_SEQ_CONV)       || \
 374                                              ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV)  )
 375 /**
 376   * @}
 377   */
 378
 379 /** @defgroup ADC_Overrun ADC Overrun
 380   * @{
 381   */
 382 #define OVR_DATA_OVERWRITTEN            ((uint32_t)0x00000000)
 383 #define OVR_DATA_PRESERVED              ((uint32_t)0x00000001)
 384
 385 #define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED)  || \
 386                              ((OVR) == OVR_DATA_OVERWRITTEN)  )
 387 /**
 388   * @}
 389   */
 390
 391 /** @defgroup ADC_channels ADC channels
 392   * @{
 393   */
 394 /* Note: Depending on devices, some channels may not be available on package  */
 395 /*       pins. Refer to device datasheet for channels availability.           */
 396 /* Note: Channels are used by bitfields for setting of channel selection      */
 397 /* (register ADC_CHSELR) and used by number for setting of analog watchdog    */
 398 /* channel (bits AWDCH in register ADC_CFGR1).                                */
 399 /* Channels are defined with decimal numbers and converted them to bitfields  */
 400 /* when needed.                                                               */
 401 #define ADC_CHANNEL_0           ((uint32_t) 0x00000000)
 402 #define ADC_CHANNEL_1           ((uint32_t) 0x00000001)
 403 #define ADC_CHANNEL_2           ((uint32_t) 0x00000002)
 404 #define ADC_CHANNEL_3           ((uint32_t) 0x00000003)
 405 #define ADC_CHANNEL_4           ((uint32_t) 0x00000004)
 406 #define ADC_CHANNEL_5           ((uint32_t) 0x00000005)
 407 #define ADC_CHANNEL_6           ((uint32_t) 0x00000006)
 408 #define ADC_CHANNEL_7           ((uint32_t) 0x00000007)
 409 #define ADC_CHANNEL_8           ((uint32_t) 0x00000008)
 410 #define ADC_CHANNEL_9           ((uint32_t) 0x00000009)
 411 #define ADC_CHANNEL_10          ((uint32_t) 0x0000000A)
 412 #define ADC_CHANNEL_11          ((uint32_t) 0x0000000B)
 413 #define ADC_CHANNEL_12          ((uint32_t) 0x0000000C)
 414 #define ADC_CHANNEL_13          ((uint32_t) 0x0000000D)
 415 #define ADC_CHANNEL_14          ((uint32_t) 0x0000000E)
 416 #define ADC_CHANNEL_15          ((uint32_t) 0x0000000F)
 417 #define ADC_CHANNEL_16          ((uint32_t) 0x00000010)
 418 #define ADC_CHANNEL_17          ((uint32_t) 0x00000011)
 419 #define ADC_CHANNEL_18          ((uint32_t) 0x00000012)
 420
 421 #define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16
 422 #define ADC_CHANNEL_VREFINT     ADC_CHANNEL_17
 423 #define ADC_CHANNEL_VBAT        ADC_CHANNEL_18
 424
 425 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
 426                                  ((CHANNEL) == ADC_CHANNEL_1)           || \
 427                                  ((CHANNEL) == ADC_CHANNEL_2)           || \
 428                                  ((CHANNEL) == ADC_CHANNEL_3)           || \
 429                                  ((CHANNEL) == ADC_CHANNEL_4)           || \
 430                                  ((CHANNEL) == ADC_CHANNEL_5)           || \
 431                                  ((CHANNEL) == ADC_CHANNEL_6)           || \
 432                                  ((CHANNEL) == ADC_CHANNEL_7)           || \
 433                                  ((CHANNEL) == ADC_CHANNEL_8)           || \
 434                                  ((CHANNEL) == ADC_CHANNEL_9)           || \
 435                                  ((CHANNEL) == ADC_CHANNEL_10)          || \
 436                                  ((CHANNEL) == ADC_CHANNEL_11)          || \
 437                                  ((CHANNEL) == ADC_CHANNEL_12)          || \
 438                                  ((CHANNEL) == ADC_CHANNEL_13)          || \
 439                                  ((CHANNEL) == ADC_CHANNEL_14)          || \
 440                                  ((CHANNEL) == ADC_CHANNEL_15)          || \
 441                                  ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
 442                                  ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
 443                                  ((CHANNEL) == ADC_CHANNEL_VBAT)          )
 444 /**
 445   * @}
 446   */
 447
 448 /** @defgroup ADC_rank ADC rank
 449   * @{
 450   */
 451 #define ADC_RANK_CHANNEL_NUMBER                 ((uint32_t)0x00001000)  /*!< Enable the rank of the selected channels. Rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
 452 #define ADC_RANK_NONE                           ((uint32_t)0x00001001)  /*!< Disable the selected rank (selected channel) from sequencer */
 453
 454 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
 455                                ((WATCHDOG) == ADC_RANK_NONE)             )
 456 /**
 457   * @}
 458   */
 459
 460 /** @defgroup ADC_sampling_times ADC sampling times
 461   * @{
 462   */
 463 #define ADC_SAMPLETIME_1CYCLE_5       ((uint32_t)0x00000000)                        /*!< Sampling time 1.5 ADC clock cycle */
 464 #define ADC_SAMPLETIME_7CYCLES_5      ((uint32_t) ADC_SMPR_SMP_0)                   /*!< Sampling time 7.5 ADC clock cycles */
 465 #define ADC_SAMPLETIME_13CYCLES_5     ((uint32_t) ADC_SMPR_SMP_1)                   /*!< Sampling time 13.5 ADC clock cycles */
 466 #define ADC_SAMPLETIME_28CYCLES_5     ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */
 467 #define ADC_SAMPLETIME_41CYCLES_5     ((uint32_t) ADC_SMPR_SMP_2)                   /*!< Sampling time 41.5 ADC clock cycles */
 468 #define ADC_SAMPLETIME_55CYCLES_5     ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */
 469 #define ADC_SAMPLETIME_71CYCLES_5     ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */
 470 #define ADC_SAMPLETIME_239CYCLES_5    ((uint32_t) ADC_SMPR_SMP)                     /*!< Sampling time 239.5 ADC clock cycles */
 471
 472 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
 473                                   ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
 474                                   ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
 475                                   ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
 476                                   ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
 477                                   ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
 478                                   ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
 479                                   ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )
 480 /**
 481   * @}
 482   */
 483
 484 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
 485   * @{
 486   */
 487 #define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t) 0x00000000)
 488 #define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
 489 #define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CFGR1_AWDEN)
 490
 491
 492 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
 493                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
 494                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)            )
 495 /**
 496   * @}
 497   */
 498
 499 /** @defgroup ADC_Event_type ADC Event type
 500   * @{
 501   */
 502 #define AWD_EVENT              ((uint32_t)ADC_FLAG_AWD)  /*!< ADC Analog watchdog 1 event */
 503 #define OVR_EVENT              ((uint32_t)ADC_FLAG_OVR)  /*!< ADC overrun event */
 504
 505 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
 506                                   ((EVENT) == OVR_EVENT)   )
 507 /**
 508   * @}
 509   */
 510
 511 /** @defgroup ADC_interrupts_definition ADC interrupts definition
 512   * @{
 513   */
 514 #define ADC_IT_AWD           ADC_IER_AWDIE      /*!< ADC Analog watchdog interrupt source */
 515 #define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
 516 #define ADC_IT_EOS           ADC_IER_EOSEQIE    /*!< ADC End of Regular sequence of Conversions interrupt source */
 517 #define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of Regular Conversion interrupt source */
 518 #define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of Sampling interrupt source */
 519 #define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
 520 /**
 521   * @}
 522   */
 523
 524 /** @defgroup ADC_flags_definition ADC flags definition
 525   * @{
 526   */
 527 #define ADC_FLAG_AWD           ADC_ISR_AWD      /*!< ADC Analog watchdog flag */
 528 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
 529 #define ADC_FLAG_EOS           ADC_ISR_EOSEQ    /*!< ADC End of Regular sequence of Conversions flag */
 530 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
 531 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
 532 #define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
 533
 534 #define ADC_FLAG_ALL    (ADC_FLAG_AWD   | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC | \
 535                          ADC_FLAG_EOSMP | ADC_FLAG_RDY                                )
 536
 537 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
 538 #define ADC_FLAG_POSTCONV_ALL    (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
 539 /**
 540   * @}
 541   */
 542
 543 /** @defgroup ADC_range_verification ADC range verification
 544   * in function of ADC resolution selected (12, 10, 8 or 6 bits)
 545   * @{
 546   */
 547 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                         \
 548    ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
 549     (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
 550     (((RESOLUTION) == ADC_RESOLUTION8b)  && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
 551     (((RESOLUTION) == ADC_RESOLUTION6b)  && ((ADC_VALUE) <= ((uint32_t)0x003F)))   )
 552 /**
 553   * @}
 554   */
 555
 556 /** @defgroup ADC_regular_rank_verification ADC regular rank verification
 557   * @{
 558   */
 559 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
 560 /**
 561   * @}
 562   */
 563
 564 /**
 565   * @}
 566   */
 567
 568 /* Exported macros -----------------------------------------------------------*/
 569
 570 /** @defgroup ADC_Exported_Macros ADC Exported Macros
 571   * @{
 572   */
 573 /** @brief  Reset ADC handle state
 574   * @param  __HANDLE__: ADC handle
 575   * @retval None
 576   */
 577 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
 578
 579 /* Macro for internal HAL driver usage, and possibly can be used into code of */
 580 /* final user.                                                                */
 581
 582 /**
 583   * @brief Verification of ADC state: enabled or disabled
 584   * @param __HANDLE__: ADC handle
 585   * @retval SET (ADC enabled) or RESET (ADC disabled)
 586   */
 587 /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are   */
 588 /*       performed automatically by hardware and flag ADC_FLAG_RDY is not     */
 589 /*       set.                                                                 */
 590 #define __HAL_ADC_IS_ENABLED(__HANDLE__)                                                     \
 591        (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN)  && \
 592           (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)          ||      \
 593            ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF)  )     \
 594         ) ? SET : RESET)
 595
 596 /**
 597   * @brief Test if conversion trigger of regular group is software start
 598   *        or external trigger.
 599   * @param __HANDLE__: ADC handle
 600   * @retval SET (software start) or RESET (external trigger)
 601   */
 602 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                        \
 603        (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
 604
 605 /**
 606   * @brief Check if no conversion on going on regular group
 607   * @param __HANDLE__: ADC handle
 608   * @retval SET (conversion is on going) or RESET (no conversion is on going)
 609   */
 610 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                    \
 611        (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET             \
 612         ) ? RESET : SET)
 613
 614 /**
 615   * @brief Returns resolution bits in CFGR1 register: RES[1:0].
 616   *        Returned value is among parameters to @ref ADC_Resolution.
 617   * @param __HANDLE__: ADC handle
 618   * @retval None
 619   */
 620 #define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
 621
 622 /**
 623   * @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
 624   *        Returned value is among parameters to @ref ADC_Resolution.
 625   * @param __HANDLE__: ADC handle
 626   * @retval None
 627   */
 628 #define __HAL_ADC_GET_SAMPLINGTIME(__HANDLE__) (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP)
 629
 630 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
 631   * @param __HANDLE__: ADC handle
 632   * @param __INTERRUPT__: ADC interrupt source to check
 633   * @retval State ofinterruption (SET or RESET)
 634   */
 635 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
 636     (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)      \
 637      )? SET : RESET                                                            \
 638     )
 639
 640 /**
 641   * @brief Enable the ADC end of conversion interrupt.
 642   * @param __HANDLE__: ADC handle
 643   * @param __INTERRUPT__: ADC Interrupt
 644   * @retval None
 645   */
 646 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
 647
 648 /**
 649   * @brief Disable the ADC end of conversion interrupt.
 650   * @param __HANDLE__: ADC handle
 651   * @param __INTERRUPT__: ADC Interrupt
 652   * @retval None
 653   */
 654 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
 655
 656 /**
 657   * @brief Get the selected ADC's flag status.
 658   * @param __HANDLE__: ADC handle
 659   * @param __FLAG__: ADC flag
 660   * @retval None
 661   */
 662 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
 663
 664 /**
 665   * @brief Clear the ADC's pending flags
 666   * @param __HANDLE__: ADC handle
 667   * @param __FLAG__: ADC flag
 668   * @retval None
 669   */
 670 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
 671 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
 672
 673 /**
 674   * @brief Clear ADC error code (set it to error code: "no error")
 675   * @param __HANDLE__: ADC handle
 676   * @retval None
 677   */
 678 #define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
 679
 680
 681 /**
 682   * @brief Configure the channel number into channel selection register
 683   * @param _CHANNEL_: ADC Channel
 684   * @retval None
 685   */
 686 /* This function converts ADC channels from numbers (see defgroup ADC_channels)
 687    to bitfields, to get the equivalence of CMSIS channels:
 688         ADC_CHANNEL_0           ((uint32_t) ADC_CHSELR_CHSEL0)
 689         ADC_CHANNEL_1           ((uint32_t) ADC_CHSELR_CHSEL1)
 690         ADC_CHANNEL_2           ((uint32_t) ADC_CHSELR_CHSEL2)
 691         ADC_CHANNEL_3           ((uint32_t) ADC_CHSELR_CHSEL3)
 692         ADC_CHANNEL_4           ((uint32_t) ADC_CHSELR_CHSEL4)
 693         ADC_CHANNEL_5           ((uint32_t) ADC_CHSELR_CHSEL5)
 694         ADC_CHANNEL_6           ((uint32_t) ADC_CHSELR_CHSEL6)
 695         ADC_CHANNEL_7           ((uint32_t) ADC_CHSELR_CHSEL7)
 696         ADC_CHANNEL_8           ((uint32_t) ADC_CHSELR_CHSEL8)
 697         ADC_CHANNEL_9           ((uint32_t) ADC_CHSELR_CHSEL9)
 698         ADC_CHANNEL_10          ((uint32_t) ADC_CHSELR_CHSEL10)
 699         ADC_CHANNEL_11          ((uint32_t) ADC_CHSELR_CHSEL11)
 700         ADC_CHANNEL_12          ((uint32_t) ADC_CHSELR_CHSEL12)
 701         ADC_CHANNEL_13          ((uint32_t) ADC_CHSELR_CHSEL13)
 702         ADC_CHANNEL_14          ((uint32_t) ADC_CHSELR_CHSEL14)
 703         ADC_CHANNEL_15          ((uint32_t) ADC_CHSELR_CHSEL15)
 704         ADC_CHANNEL_16          ((uint32_t) ADC_CHSELR_CHSEL16)
 705         ADC_CHANNEL_17          ((uint32_t) ADC_CHSELR_CHSEL17)
 706         ADC_CHANNEL_18          ((uint32_t) ADC_CHSELR_CHSEL18)
 707 */
 708 #define __HAL_ADC_CHSELR_CHANNEL(_CHANNEL_) ( 1U << (_CHANNEL_))
 709
 710 /**
 711   * @}
 712   */
 713
 714 /** @defgroup ADC_Exported_Macro_internal_HAL_driver ADC Exported Macro internal HAL driver
 715   * @{
 716   */
 717 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
 718 /* code of final user.                                                        */
 719
 720 /**
 721   * @brief Set the Analog Watchdog 1 channel.
 722   * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
 723   * @retval None
 724   */
 725 #define __HAL_ADC_CFGR_AWDCH(_CHANNEL_) ((_CHANNEL_) << 26)
 726
 727 /**
 728   * @brief Enable ADC discontinuous conversion mode for regular group
 729   * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
 730   * @retval None
 731   */
 732 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16)
 733
 734 /**
 735   * @brief Enable the ADC auto off mode.
 736   * @param _AUTOOFF_: Auto off bit enable or disable.
 737   * @retval None
 738   */
 739 #define __HAL_ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15)
 740
 741 /**
 742   * @brief Enable the ADC auto delay mode.
 743   * @param _AUTOWAIT_: Auto delay bit enable or disable.
 744   * @retval None
 745   */
 746 #define __HAL_ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14)
 747
 748 /**
 749   * @brief Enable ADC continuous conversion mode.
 750   * @param _CONTINUOUS_MODE_: Continuous mode.
 751   * @retval None
 752   */
 753 #define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
 754
 755 /**
 756   * @brief Enable ADC overrun mode.
 757   * @param _OVERRUN_MODE_: Overrun mode.
 758   * @retval Overun bit setting to be programmed into CFGR register
 759   */
 760 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant                   */
 761 /* "OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it as the */
 762 /* default case to be compliant with other STM32 devices.                     */
 763 #define __HAL_ADC_CFGR1_OVERRUN(_OVERRUN_MODE_)                                \
 764   ( ( (_OVERRUN_MODE_) != (OVR_DATA_PRESERVED)                                 \
 765     )? (ADC_CFGR1_OVRMOD) : (0x00000000)                                       \
 766   )
 767
 768 /**
 769   * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
 770   * @param _SCAN_MODE_: Scan conversion mode.
 771   * @retval None
 772   */
 773 #define __HAL_ADC_CFGR1_SCANDIR(_SCAN_MODE_)                                   \
 774   ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD)                           \
 775     )? (ADC_CFGR1_SCANDIR) : (0x00000000)                                      \
 776   )
 777
 778 /**
 779   * @brief Enable the ADC DMA continuous request.
 780   * @param _DMACONTREQ_MODE_: DMA continuous request mode.
 781   * @retval None
 782   */
 783 #define __HAL_ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1)
 784
 785 /**
 786   * @brief Configure the analog watchdog high threshold into register TR.
 787   * @param _Threshold_: Threshold value
 788   * @retval None
 789   */
 790 #define __HAL_ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
 791
 792 /**
 793   * @brief Enable the ADC peripheral
 794   * @param __HANDLE__: ADC handle
 795   * @retval None
 796   */
 797 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
 798
 799 /**
 800   * @brief Verification of hardware constraints before ADC can be enabled
 801   * @param __HANDLE__: ADC handle
 802   * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
 803   */
 804 #define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__)                             \
 805        (( ( ((__HANDLE__)->Instance->CR) &                                    \
 806             (ADC_CR_ADCAL | ADC_CR_ADSTP |                                    \
 807              ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN                    ) \
 808            ) == RESET                                                         \
 809         ) ? SET : RESET)
 810
 811 /**
 812   * @brief Disable the ADC peripheral
 813   * @param __HANDLE__: ADC handle
 814   * @retval None
 815   */
 816 #define __HAL_ADC_DISABLE(__HANDLE__)                                          \
 817   do{                                                                          \
 818          (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
 819           __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
 820   } while(0)
 821
 822 /**
 823   * @brief Verification of hardware constraints before ADC can be disabled
 824   * @param __HANDLE__: ADC handle
 825   * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
 826   */
 827 #define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__)                             \
 828        (( ( ((__HANDLE__)->Instance->CR) &                                     \
 829             (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
 830         ) ? SET : RESET)
 831
 832 /**
 833   * @brief Shift the AWD threshold in function of the selected ADC resolution.
 834   *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
 835   *        If resolution 12 bits, no shift.
 836   *        If resolution 10 bits, shift of 2 ranks on the left.
 837   *        If resolution 8 bits, shift of 4 ranks on the left.
 838   *        If resolution 6 bits, shift of 6 ranks on the left.
 839   *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
 840   * @param __HANDLE__: ADC handle
 841   * @param _Threshold_: Value to be shifted
 842   * @retval None
 843   */
 844 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
 845         ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
 846
 847 /**
 848   * @}
 849   */
 850
 851 /* Include ADC HAL Extension module */
 852 #include "stm32f0xx_hal_adc_ex.h"
 853
 854 /* Exported functions --------------------------------------------------------*/
 855 /** @addtogroup ADC_Exported_Functions
 856   * @{
 857   */
 858
 859 /** @addtogroup ADC_Exported_Functions_Group1
 860   * @{
 861   */
 862
 863
 864 /* Initialization and de-initialization functions  **********************************/
 865 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
 866 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
 867 void              HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
 868 void              HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
 869 /**
 870   * @}
 871   */
 872
 873 /* IO operation functions  *****************************************************/
 874
 875 /** @addtogroup ADC_Exported_Functions_Group2
 876   * @{
 877   */
 878
 879
 880 /* Blocking mode: Polling */
 881 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
 882 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
 883 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
 884 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
 885
 886 /* Non-blocking mode: Interruption */
 887 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
 888 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
 889
 890 /* Non-blocking mode: DMA */
 891 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
 892 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
 893
 894 /* ADC retrieve conversion value intended to be used with polling or interruption */
 895 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
 896
 897 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
 898 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
 899 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
 900 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
 901 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
 902 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
 903 /**
 904   * @}
 905   */
 906
 907
 908 /* Peripheral Control functions ***********************************************/
 909 /** @addtogroup ADC_Exported_Functions_Group3
 910   * @{
 911   */
 912 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
 913 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
 914 /**
 915   * @}
 916   */
 917
 918
 919 /* Peripheral State functions *************************************************/
 920 /** @addtogroup ADC_Exported_Functions_Group4
 921   * @{
 922   */
 923 HAL_ADC_StateTypeDef    HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
 924 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 925 /**
 926   * @}
 927   */
 928
 929
 930 /**
 931   * @}
 932   */
 933
 934
 935 /**
 936   * @}
 937   */
 938
 939 /**
 940   * @}
 941   */
 942
 943 #ifdef __cplusplus
 944 }
 945 #endif
 946
 947
 948 #endif /* __STM32F0xx_HAL_ADC_H */
 949
 950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 951