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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / TARGET_NUCLEO_F334R8 / TOOLCHAIN_ARM_MICRO / startup_stm32f334x8.s
1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2 ;* File Name : startup_stm32f334x8.s
3 ;* Author : MCD Application Team
4 ;* Version : V2.1.0
5 ;* Date : 12-Sept-2014
6 ;* Description : STM32F334x4/x6/x8 devices vector table for MDK-ARM_MICRO toolchain.
7 ;* This module performs:
8 ;* - Set the initial SP
9 ;* - Set the initial PC == Reset_Handler
10 ;* - Set the vector table entries with the exceptions ISR address
11 ;* - Branches to __main in the C library (which eventually
12 ;* calls main()).
13 ;* After Reset the CortexM4 processor is in Thread mode,
14 ;* priority is Privileged, and the Stack is set to Main.
15 ;* <<< Use Configuration Wizard in Context Menu >>>
16 ;*******************************************************************************
17 ;
18 ;* Redistribution and use in source and binary forms, with or without modification,
19 ;* are permitted provided that the following conditions are met:
20 ;* 1. Redistributions of source code must retain the above copyright notice,
21 ;* this list of conditions and the following disclaimer.
22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
23 ;* this list of conditions and the following disclaimer in the documentation
24 ;* and/or other materials provided with the distribution.
25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
26 ;* may be used to endorse or promote products derived from this software
27 ;* without specific prior written permission.
28 ;*
29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 ;
40 ;*******************************************************************************
41
42 ; Amount of memory (in bytes) allocated for Stack
43 ; Tailor this value to your application needs
44 ; <h> Stack Configuration
45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46 ; </h>
47
48 Stack_Size EQU 0x00000400
49
50 AREA STACK, NOINIT, READWRITE, ALIGN=3
51 EXPORT __initial_sp
52
53 Stack_Mem SPACE Stack_Size
54 __initial_sp EQU 0x20003000 ; Top of RAM
55
56
57 ; <h> Heap Configuration
58 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
59 ; </h>
60
61 Heap_Size EQU 0x00000400
62
63 AREA HEAP, NOINIT, READWRITE, ALIGN=3
64 EXPORT __heap_base
65 EXPORT __heap_limit
66
67 __heap_base
68 Heap_Mem SPACE Heap_Size
69 __heap_limit EQU (__initial_sp - Stack_Size)
70
71 PRESERVE8
72 THUMB
73
74
75 ; Vector Table Mapped to Address 0 at Reset
76 AREA RESET, DATA, READONLY
77 EXPORT __Vectors
78 EXPORT __Vectors_End
79 EXPORT __Vectors_Size
80
81 __Vectors DCD __initial_sp ; Top of Stack
82 DCD Reset_Handler ; Reset Handler
83 DCD NMI_Handler ; NMI Handler
84 DCD HardFault_Handler ; Hard Fault Handler
85 DCD MemManage_Handler ; MPU Fault Handler
86 DCD BusFault_Handler ; Bus Fault Handler
87 DCD UsageFault_Handler ; Usage Fault Handler
88 DCD 0 ; Reserved
89 DCD 0 ; Reserved
90 DCD 0 ; Reserved
91 DCD 0 ; Reserved
92 DCD SVC_Handler ; SVCall Handler
93 DCD DebugMon_Handler ; Debug Monitor Handler
94 DCD 0 ; Reserved
95 DCD PendSV_Handler ; PendSV Handler
96 DCD SysTick_Handler ; SysTick Handler
97
98 ; External Interrupts
99 DCD WWDG_IRQHandler ; Window WatchDog
100 DCD PVD_IRQHandler ; PVD through EXTI Line detection
101 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
102 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
103 DCD FLASH_IRQHandler ; FLASH
104 DCD RCC_IRQHandler ; RCC
105 DCD EXTI0_IRQHandler ; EXTI Line0
106 DCD EXTI1_IRQHandler ; EXTI Line1
107 DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
108 DCD EXTI3_IRQHandler ; EXTI Line3
109 DCD EXTI4_IRQHandler ; EXTI Line4
110 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
111 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
112 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
113 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
114 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
115 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
116 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
117 DCD ADC1_2_IRQHandler ; ADC1 and ADC2
118 DCD CAN_TX_IRQHandler ; CAN TX
119 DCD CAN_RX0_IRQHandler ; CAN RX0
120 DCD CAN_RX1_IRQHandler ; CAN RX1
121 DCD CAN_SCE_IRQHandler ; CAN SCE
122 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
123 DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
124 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
125 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
126 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
127 DCD TIM2_IRQHandler ; TIM2
128 DCD TIM3_IRQHandler ; TIM3
129 DCD 0 ; Reserved
130 DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
131 DCD I2C1_ER_IRQHandler ; I2C1 Error
132 DCD 0 ; Reserved
133 DCD 0 ; Reserved
134 DCD SPI1_IRQHandler ; SPI1
135 DCD 0 ; Reserved
136 DCD USART1_IRQHandler ; USART1 and EXTI Line 25
137 DCD USART2_IRQHandler ; USART2 and EXTI Line 26
138 DCD USART3_IRQHandler ; USART3 and EXTI Line 28
139 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
140 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
141 DCD 0 ; Reserved
142 DCD 0 ; Reserved
143 DCD 0 ; Reserved
144 DCD 0 ; Reserved
145 DCD 0 ; Reserved
146 DCD 0 ; Reserved
147 DCD 0 ; Reserved
148 DCD 0 ; Reserved
149 DCD 0 ; Reserved
150 DCD 0 ; Reserved
151 DCD 0 ; Reserved
152 DCD 0 ; Reserved
153 DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
154 DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
155 DCD 0 ; Reserved
156 DCD 0 ; Reserved
157 DCD 0 ; Reserved
158 DCD 0 ; Reserved
159 DCD 0 ; Reserved
160 DCD 0 ; Reserved
161 DCD 0 ; Reserved
162 DCD 0 ; Reserved
163 DCD COMP2_IRQHandler ; COMP2
164 DCD COMP4_6_IRQHandler ; COMP4 and COMP6
165 DCD 0 ; Reserved
166 DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
167 DCD HRTIM1_TIMA_IRQHandler ; HRTIM1 timer A
168 DCD HRTIM1_TIMB_IRQHandler ; HRTIM1 timer B
169 DCD HRTIM1_TIMC_IRQHandler ; HRTIM1 timer C
170 DCD HRTIM1_TIMD_IRQHandler ; HRTIM1 timer D
171 DCD HRTIM1_TIME_IRQHandler ; HRTIM1 timer E
172 DCD HRTIM1_FLT_IRQHandler ; HRTIM1 fault
173 DCD 0 ; Reserved
174 DCD 0 ; Reserved
175 DCD 0 ; Reserved
176 DCD 0 ; Reserved
177 DCD 0 ; Reserved
178 DCD 0 ; Reserved
179 DCD 0 ; Reserved
180 DCD FPU_IRQHandler ; FPU
181
182 __Vectors_End
183
184 __Vectors_Size EQU __Vectors_End - __Vectors
185
186 AREA |.text|, CODE, READONLY
187
188 ; Reset handler
189 Reset_Handler PROC
190 EXPORT Reset_Handler [WEAK]
191 IMPORT SystemInit
192 IMPORT __main
193
194 LDR R0, =SystemInit
195 BLX R0
196 LDR R0, =__main
197 BX R0
198 ENDP
199
200 ; Dummy Exception Handlers (infinite loops which can be modified)
201
202 NMI_Handler PROC
203 EXPORT NMI_Handler [WEAK]
204 B .
205 ENDP
206 HardFault_Handler\
207 PROC
208 EXPORT HardFault_Handler [WEAK]
209 B .
210 ENDP
211 MemManage_Handler\
212 PROC
213 EXPORT MemManage_Handler [WEAK]
214 B .
215 ENDP
216 BusFault_Handler\
217 PROC
218 EXPORT BusFault_Handler [WEAK]
219 B .
220 ENDP
221 UsageFault_Handler\
222 PROC
223 EXPORT UsageFault_Handler [WEAK]
224 B .
225 ENDP
226 SVC_Handler PROC
227 EXPORT SVC_Handler [WEAK]
228 B .
229 ENDP
230 DebugMon_Handler\
231 PROC
232 EXPORT DebugMon_Handler [WEAK]
233 B .
234 ENDP
235 PendSV_Handler PROC
236 EXPORT PendSV_Handler [WEAK]
237 B .
238 ENDP
239 SysTick_Handler PROC
240 EXPORT SysTick_Handler [WEAK]
241 B .
242 ENDP
243
244 Default_Handler PROC
245
246 EXPORT WWDG_IRQHandler [WEAK]
247 EXPORT PVD_IRQHandler [WEAK]
248 EXPORT TAMP_STAMP_IRQHandler [WEAK]
249 EXPORT RTC_WKUP_IRQHandler [WEAK]
250 EXPORT FLASH_IRQHandler [WEAK]
251 EXPORT RCC_IRQHandler [WEAK]
252 EXPORT EXTI0_IRQHandler [WEAK]
253 EXPORT EXTI1_IRQHandler [WEAK]
254 EXPORT EXTI2_TSC_IRQHandler [WEAK]
255 EXPORT EXTI3_IRQHandler [WEAK]
256 EXPORT EXTI4_IRQHandler [WEAK]
257 EXPORT DMA1_Channel1_IRQHandler [WEAK]
258 EXPORT DMA1_Channel2_IRQHandler [WEAK]
259 EXPORT DMA1_Channel3_IRQHandler [WEAK]
260 EXPORT DMA1_Channel4_IRQHandler [WEAK]
261 EXPORT DMA1_Channel5_IRQHandler [WEAK]
262 EXPORT DMA1_Channel6_IRQHandler [WEAK]
263 EXPORT DMA1_Channel7_IRQHandler [WEAK]
264 EXPORT ADC1_2_IRQHandler [WEAK]
265 EXPORT CAN_TX_IRQHandler [WEAK]
266 EXPORT CAN_RX0_IRQHandler [WEAK]
267 EXPORT CAN_RX1_IRQHandler [WEAK]
268 EXPORT CAN_SCE_IRQHandler [WEAK]
269 EXPORT EXTI9_5_IRQHandler [WEAK]
270 EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
271 EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
272 EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
273 EXPORT TIM1_CC_IRQHandler [WEAK]
274 EXPORT TIM2_IRQHandler [WEAK]
275 EXPORT TIM3_IRQHandler [WEAK]
276 EXPORT I2C1_EV_IRQHandler [WEAK]
277 EXPORT I2C1_ER_IRQHandler [WEAK]
278 EXPORT SPI1_IRQHandler [WEAK]
279 EXPORT USART1_IRQHandler [WEAK]
280 EXPORT USART2_IRQHandler [WEAK]
281 EXPORT USART3_IRQHandler [WEAK]
282 EXPORT EXTI15_10_IRQHandler [WEAK]
283 EXPORT RTC_Alarm_IRQHandler [WEAK]
284 EXPORT TIM6_DAC1_IRQHandler [WEAK]
285 EXPORT TIM7_DAC2_IRQHandler [WEAK]
286 EXPORT COMP2_IRQHandler [WEAK]
287 EXPORT COMP4_6_IRQHandler [WEAK]
288 EXPORT HRTIM1_Master_IRQHandler [WEAK]
289 EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
290 EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
291 EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
292 EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
293 EXPORT HRTIM1_TIME_IRQHandler [WEAK]
294 EXPORT HRTIM1_FLT_IRQHandler [WEAK]
295 EXPORT FPU_IRQHandler [WEAK]
296
297 WWDG_IRQHandler
298 PVD_IRQHandler
299 TAMP_STAMP_IRQHandler
300 RTC_WKUP_IRQHandler
301 FLASH_IRQHandler
302 RCC_IRQHandler
303 EXTI0_IRQHandler
304 EXTI1_IRQHandler
305 EXTI2_TSC_IRQHandler
306 EXTI3_IRQHandler
307 EXTI4_IRQHandler
308 DMA1_Channel1_IRQHandler
309 DMA1_Channel2_IRQHandler
310 DMA1_Channel3_IRQHandler
311 DMA1_Channel4_IRQHandler
312 DMA1_Channel5_IRQHandler
313 DMA1_Channel6_IRQHandler
314 DMA1_Channel7_IRQHandler
315 ADC1_2_IRQHandler
316 CAN_TX_IRQHandler
317 CAN_RX0_IRQHandler
318 CAN_RX1_IRQHandler
319 CAN_SCE_IRQHandler
320 EXTI9_5_IRQHandler
321 TIM1_BRK_TIM15_IRQHandler
322 TIM1_UP_TIM16_IRQHandler
323 TIM1_TRG_COM_TIM17_IRQHandler
324 TIM1_CC_IRQHandler
325 TIM2_IRQHandler
326 TIM3_IRQHandler
327 I2C1_EV_IRQHandler
328 I2C1_ER_IRQHandler
329 SPI1_IRQHandler
330 USART1_IRQHandler
331 USART2_IRQHandler
332 USART3_IRQHandler
333 EXTI15_10_IRQHandler
334 RTC_Alarm_IRQHandler
335 TIM6_DAC1_IRQHandler
336 TIM7_DAC2_IRQHandler
337 COMP2_IRQHandler
338 COMP4_6_IRQHandler
339 HRTIM1_Master_IRQHandler
340 HRTIM1_TIMA_IRQHandler
341 HRTIM1_TIMB_IRQHandler
342 HRTIM1_TIMC_IRQHandler
343 HRTIM1_TIMD_IRQHandler
344 HRTIM1_TIME_IRQHandler
345 HRTIM1_FLT_IRQHandler
346 FPU_IRQHandler
347
348 B .
349
350 ENDP
351
352 ALIGN
353 END
354
355 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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