tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_CRC_REGISTERS_H__
  78 #define __HW_CRC_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 CRC
  85  *
  86  * Cyclic Redundancy Check
  87  *
  88  * Registers defined in this header file:
  89  * - HW_CRC_DATAL - CRC_DATAL register.
  90  * - HW_CRC_DATAH - CRC_DATAH register.
  91  * - HW_CRC_DATALL - CRC_DATALL register.
  92  * - HW_CRC_DATALU - CRC_DATALU register.
  93  * - HW_CRC_DATAHL - CRC_DATAHL register.
  94  * - HW_CRC_DATAHU - CRC_DATAHU register.
  95  * - HW_CRC_DATA - CRC Data register
  96  * - HW_CRC_GPOLY - CRC Polynomial register
  97  * - HW_CRC_GPOLYL - CRC_GPOLYL register.
  98  * - HW_CRC_GPOLYH - CRC_GPOLYH register.
  99  * - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
 100  * - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
 101  * - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
 102  * - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
 103  * - HW_CRC_CTRL - CRC Control register
 104  * - HW_CRC_CTRLHU - CRC_CTRLHU register.
 105  *
 106  * - hw_crc_t - Struct containing all module registers.
 107  */
 108
 109 #define HW_CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
 110
 111 /*******************************************************************************
 112  * HW_CRC_DATAL - CRC_DATAL register.
 113  ******************************************************************************/
 114
 115 /*!
 116  * @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
 117  *
 118  * Reset value: 0xFFFFU
 119  */
 120 typedef union _hw_crc_datal
 121 {
 122     uint16_t U;
 123     struct _hw_crc_datal_bitfields
 124     {
 125         uint16_t DATAL : 16;           /*!< [15:0] DATAL stores the lower 16 bits of
 126                                         * the 16/32 bit CRC */
 127     } B;
 128 } hw_crc_datal_t;
 129
 130 /*!
 131  * @name Constants and macros for entire CRC_DATAL register
 132  */
 133 /*@{*/
 134 #define HW_CRC_DATAL_ADDR(x)     ((x) + 0x0U)
 135
 136 #define HW_CRC_DATAL(x)          (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR(x))
 137 #define HW_CRC_DATAL_RD(x)       (HW_CRC_DATAL(x).U)
 138 #define HW_CRC_DATAL_WR(x, v)    (HW_CRC_DATAL(x).U = (v))
 139 #define HW_CRC_DATAL_SET(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) |  (v)))
 140 #define HW_CRC_DATAL_CLR(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) & ~(v)))
 141 #define HW_CRC_DATAL_TOG(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) ^  (v)))
 142 /*@}*/
 143
 144 /*
 145  * Constants & macros for individual CRC_DATAL bitfields
 146  */
 147
 148 /*!
 149  * @name Register CRC_DATAL, field DATAL[15:0] (RW)
 150  */
 151 /*@{*/
 152 #define BP_CRC_DATAL_DATAL   (0U)          /*!< Bit position for CRC_DATAL_DATAL. */
 153 #define BM_CRC_DATAL_DATAL   (0xFFFFU)     /*!< Bit mask for CRC_DATAL_DATAL. */
 154 #define BS_CRC_DATAL_DATAL   (16U)         /*!< Bit field size in bits for CRC_DATAL_DATAL. */
 155
 156 /*! @brief Read current value of the CRC_DATAL_DATAL field. */
 157 #define BR_CRC_DATAL_DATAL(x) (HW_CRC_DATAL(x).U)
 158
 159 /*! @brief Format value for bitfield CRC_DATAL_DATAL. */
 160 #define BF_CRC_DATAL_DATAL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAL_DATAL) & BM_CRC_DATAL_DATAL)
 161
 162 /*! @brief Set the DATAL field to a new value. */
 163 #define BW_CRC_DATAL_DATAL(x, v) (HW_CRC_DATAL_WR(x, v))
 164 /*@}*/
 165 /*******************************************************************************
 166  * HW_CRC_DATAH - CRC_DATAH register.
 167  ******************************************************************************/
 168
 169 /*!
 170  * @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
 171  *
 172  * Reset value: 0xFFFFU
 173  */
 174 typedef union _hw_crc_datah
 175 {
 176     uint16_t U;
 177     struct _hw_crc_datah_bitfields
 178     {
 179         uint16_t DATAH : 16;           /*!< [15:0] DATAH stores the high 16 bits of the
 180                                         * 16/32 bit CRC */
 181     } B;
 182 } hw_crc_datah_t;
 183
 184 /*!
 185  * @name Constants and macros for entire CRC_DATAH register
 186  */
 187 /*@{*/
 188 #define HW_CRC_DATAH_ADDR(x)     ((x) + 0x2U)
 189
 190 #define HW_CRC_DATAH(x)          (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR(x))
 191 #define HW_CRC_DATAH_RD(x)       (HW_CRC_DATAH(x).U)
 192 #define HW_CRC_DATAH_WR(x, v)    (HW_CRC_DATAH(x).U = (v))
 193 #define HW_CRC_DATAH_SET(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) |  (v)))
 194 #define HW_CRC_DATAH_CLR(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) & ~(v)))
 195 #define HW_CRC_DATAH_TOG(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) ^  (v)))
 196 /*@}*/
 197
 198 /*
 199  * Constants & macros for individual CRC_DATAH bitfields
 200  */
 201
 202 /*!
 203  * @name Register CRC_DATAH, field DATAH[15:0] (RW)
 204  */
 205 /*@{*/
 206 #define BP_CRC_DATAH_DATAH   (0U)          /*!< Bit position for CRC_DATAH_DATAH. */
 207 #define BM_CRC_DATAH_DATAH   (0xFFFFU)     /*!< Bit mask for CRC_DATAH_DATAH. */
 208 #define BS_CRC_DATAH_DATAH   (16U)         /*!< Bit field size in bits for CRC_DATAH_DATAH. */
 209
 210 /*! @brief Read current value of the CRC_DATAH_DATAH field. */
 211 #define BR_CRC_DATAH_DATAH(x) (HW_CRC_DATAH(x).U)
 212
 213 /*! @brief Format value for bitfield CRC_DATAH_DATAH. */
 214 #define BF_CRC_DATAH_DATAH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAH_DATAH) & BM_CRC_DATAH_DATAH)
 215
 216 /*! @brief Set the DATAH field to a new value. */
 217 #define BW_CRC_DATAH_DATAH(x, v) (HW_CRC_DATAH_WR(x, v))
 218 /*@}*/
 219 /*******************************************************************************
 220  * HW_CRC_DATALL - CRC_DATALL register.
 221  ******************************************************************************/
 222
 223 /*!
 224  * @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
 225  *
 226  * Reset value: 0xFFU
 227  */
 228 typedef union _hw_crc_datall
 229 {
 230     uint8_t U;
 231     struct _hw_crc_datall_bitfields
 232     {
 233         uint8_t DATALL : 8;            /*!< [7:0] CRCLL stores the first 8 bits of the
 234                                         * 32 bit DATA */
 235     } B;
 236 } hw_crc_datall_t;
 237
 238 /*!
 239  * @name Constants and macros for entire CRC_DATALL register
 240  */
 241 /*@{*/
 242 #define HW_CRC_DATALL_ADDR(x)    ((x) + 0x0U)
 243
 244 #define HW_CRC_DATALL(x)         (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR(x))
 245 #define HW_CRC_DATALL_RD(x)      (HW_CRC_DATALL(x).U)
 246 #define HW_CRC_DATALL_WR(x, v)   (HW_CRC_DATALL(x).U = (v))
 247 #define HW_CRC_DATALL_SET(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) |  (v)))
 248 #define HW_CRC_DATALL_CLR(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) & ~(v)))
 249 #define HW_CRC_DATALL_TOG(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) ^  (v)))
 250 /*@}*/
 251
 252 /*
 253  * Constants & macros for individual CRC_DATALL bitfields
 254  */
 255
 256 /*!
 257  * @name Register CRC_DATALL, field DATALL[7:0] (RW)
 258  */
 259 /*@{*/
 260 #define BP_CRC_DATALL_DATALL (0U)          /*!< Bit position for CRC_DATALL_DATALL. */
 261 #define BM_CRC_DATALL_DATALL (0xFFU)       /*!< Bit mask for CRC_DATALL_DATALL. */
 262 #define BS_CRC_DATALL_DATALL (8U)          /*!< Bit field size in bits for CRC_DATALL_DATALL. */
 263
 264 /*! @brief Read current value of the CRC_DATALL_DATALL field. */
 265 #define BR_CRC_DATALL_DATALL(x) (HW_CRC_DATALL(x).U)
 266
 267 /*! @brief Format value for bitfield CRC_DATALL_DATALL. */
 268 #define BF_CRC_DATALL_DATALL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALL_DATALL) & BM_CRC_DATALL_DATALL)
 269
 270 /*! @brief Set the DATALL field to a new value. */
 271 #define BW_CRC_DATALL_DATALL(x, v) (HW_CRC_DATALL_WR(x, v))
 272 /*@}*/
 273 /*******************************************************************************
 274  * HW_CRC_DATALU - CRC_DATALU register.
 275  ******************************************************************************/
 276
 277 /*!
 278  * @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
 279  *
 280  * Reset value: 0xFFU
 281  */
 282 typedef union _hw_crc_datalu
 283 {
 284     uint8_t U;
 285     struct _hw_crc_datalu_bitfields
 286     {
 287         uint8_t DATALU : 8;            /*!< [7:0] DATALL stores the second 8 bits of the
 288                                         * 32 bit CRC */
 289     } B;
 290 } hw_crc_datalu_t;
 291
 292 /*!
 293  * @name Constants and macros for entire CRC_DATALU register
 294  */
 295 /*@{*/
 296 #define HW_CRC_DATALU_ADDR(x)    ((x) + 0x1U)
 297
 298 #define HW_CRC_DATALU(x)         (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR(x))
 299 #define HW_CRC_DATALU_RD(x)      (HW_CRC_DATALU(x).U)
 300 #define HW_CRC_DATALU_WR(x, v)   (HW_CRC_DATALU(x).U = (v))
 301 #define HW_CRC_DATALU_SET(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) |  (v)))
 302 #define HW_CRC_DATALU_CLR(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) & ~(v)))
 303 #define HW_CRC_DATALU_TOG(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) ^  (v)))
 304 /*@}*/
 305
 306 /*
 307  * Constants & macros for individual CRC_DATALU bitfields
 308  */
 309
 310 /*!
 311  * @name Register CRC_DATALU, field DATALU[7:0] (RW)
 312  */
 313 /*@{*/
 314 #define BP_CRC_DATALU_DATALU (0U)          /*!< Bit position for CRC_DATALU_DATALU. */
 315 #define BM_CRC_DATALU_DATALU (0xFFU)       /*!< Bit mask for CRC_DATALU_DATALU. */
 316 #define BS_CRC_DATALU_DATALU (8U)          /*!< Bit field size in bits for CRC_DATALU_DATALU. */
 317
 318 /*! @brief Read current value of the CRC_DATALU_DATALU field. */
 319 #define BR_CRC_DATALU_DATALU(x) (HW_CRC_DATALU(x).U)
 320
 321 /*! @brief Format value for bitfield CRC_DATALU_DATALU. */
 322 #define BF_CRC_DATALU_DATALU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALU_DATALU) & BM_CRC_DATALU_DATALU)
 323
 324 /*! @brief Set the DATALU field to a new value. */
 325 #define BW_CRC_DATALU_DATALU(x, v) (HW_CRC_DATALU_WR(x, v))
 326 /*@}*/
 327 /*******************************************************************************
 328  * HW_CRC_DATAHL - CRC_DATAHL register.
 329  ******************************************************************************/
 330
 331 /*!
 332  * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
 333  *
 334  * Reset value: 0xFFU
 335  */
 336 typedef union _hw_crc_datahl
 337 {
 338     uint8_t U;
 339     struct _hw_crc_datahl_bitfields
 340     {
 341         uint8_t DATAHL : 8;            /*!< [7:0] DATAHL stores the third 8 bits of the
 342                                         * 32 bit CRC */
 343     } B;
 344 } hw_crc_datahl_t;
 345
 346 /*!
 347  * @name Constants and macros for entire CRC_DATAHL register
 348  */
 349 /*@{*/
 350 #define HW_CRC_DATAHL_ADDR(x)    ((x) + 0x2U)
 351
 352 #define HW_CRC_DATAHL(x)         (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR(x))
 353 #define HW_CRC_DATAHL_RD(x)      (HW_CRC_DATAHL(x).U)
 354 #define HW_CRC_DATAHL_WR(x, v)   (HW_CRC_DATAHL(x).U = (v))
 355 #define HW_CRC_DATAHL_SET(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) |  (v)))
 356 #define HW_CRC_DATAHL_CLR(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) & ~(v)))
 357 #define HW_CRC_DATAHL_TOG(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) ^  (v)))
 358 /*@}*/
 359
 360 /*
 361  * Constants & macros for individual CRC_DATAHL bitfields
 362  */
 363
 364 /*!
 365  * @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
 366  */
 367 /*@{*/
 368 #define BP_CRC_DATAHL_DATAHL (0U)          /*!< Bit position for CRC_DATAHL_DATAHL. */
 369 #define BM_CRC_DATAHL_DATAHL (0xFFU)       /*!< Bit mask for CRC_DATAHL_DATAHL. */
 370 #define BS_CRC_DATAHL_DATAHL (8U)          /*!< Bit field size in bits for CRC_DATAHL_DATAHL. */
 371
 372 /*! @brief Read current value of the CRC_DATAHL_DATAHL field. */
 373 #define BR_CRC_DATAHL_DATAHL(x) (HW_CRC_DATAHL(x).U)
 374
 375 /*! @brief Format value for bitfield CRC_DATAHL_DATAHL. */
 376 #define BF_CRC_DATAHL_DATAHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHL_DATAHL) & BM_CRC_DATAHL_DATAHL)
 377
 378 /*! @brief Set the DATAHL field to a new value. */
 379 #define BW_CRC_DATAHL_DATAHL(x, v) (HW_CRC_DATAHL_WR(x, v))
 380 /*@}*/
 381 /*******************************************************************************
 382  * HW_CRC_DATAHU - CRC_DATAHU register.
 383  ******************************************************************************/
 384
 385 /*!
 386  * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
 387  *
 388  * Reset value: 0xFFU
 389  */
 390 typedef union _hw_crc_datahu
 391 {
 392     uint8_t U;
 393     struct _hw_crc_datahu_bitfields
 394     {
 395         uint8_t DATAHU : 8;            /*!< [7:0] DATAHU stores the fourth 8 bits of the
 396                                         * 32 bit CRC */
 397     } B;
 398 } hw_crc_datahu_t;
 399
 400 /*!
 401  * @name Constants and macros for entire CRC_DATAHU register
 402  */
 403 /*@{*/
 404 #define HW_CRC_DATAHU_ADDR(x)    ((x) + 0x3U)
 405
 406 #define HW_CRC_DATAHU(x)         (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR(x))
 407 #define HW_CRC_DATAHU_RD(x)      (HW_CRC_DATAHU(x).U)
 408 #define HW_CRC_DATAHU_WR(x, v)   (HW_CRC_DATAHU(x).U = (v))
 409 #define HW_CRC_DATAHU_SET(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) |  (v)))
 410 #define HW_CRC_DATAHU_CLR(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) & ~(v)))
 411 #define HW_CRC_DATAHU_TOG(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) ^  (v)))
 412 /*@}*/
 413
 414 /*
 415  * Constants & macros for individual CRC_DATAHU bitfields
 416  */
 417
 418 /*!
 419  * @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
 420  */
 421 /*@{*/
 422 #define BP_CRC_DATAHU_DATAHU (0U)          /*!< Bit position for CRC_DATAHU_DATAHU. */
 423 #define BM_CRC_DATAHU_DATAHU (0xFFU)       /*!< Bit mask for CRC_DATAHU_DATAHU. */
 424 #define BS_CRC_DATAHU_DATAHU (8U)          /*!< Bit field size in bits for CRC_DATAHU_DATAHU. */
 425
 426 /*! @brief Read current value of the CRC_DATAHU_DATAHU field. */
 427 #define BR_CRC_DATAHU_DATAHU(x) (HW_CRC_DATAHU(x).U)
 428
 429 /*! @brief Format value for bitfield CRC_DATAHU_DATAHU. */
 430 #define BF_CRC_DATAHU_DATAHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHU_DATAHU) & BM_CRC_DATAHU_DATAHU)
 431
 432 /*! @brief Set the DATAHU field to a new value. */
 433 #define BW_CRC_DATAHU_DATAHU(x, v) (HW_CRC_DATAHU_WR(x, v))
 434 /*@}*/
 435 /*******************************************************************************
 436  * HW_CRC_DATA - CRC Data register
 437  ******************************************************************************/
 438
 439 /*!
 440  * @brief HW_CRC_DATA - CRC Data register (RW)
 441  *
 442  * Reset value: 0xFFFFFFFFU
 443  *
 444  * The CRC Data register contains the value of the seed, data, and checksum.
 445  * When CTRL[WAS] is set, any write to the data register is regarded as the seed
 446  * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
 447  * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
 448  * not used for programming the seed value, and reads of these fields return an
 449  * indeterminate value. In 32-bit CRC mode, all fields are used for programming
 450  * the seed value. When programming data values, the values can be written 8 bits,
 451  * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
 452  * data value written first. After all data values are written, the CRC result
 453  * can be read from this data register. In 16-bit CRC mode, the CRC result is
 454  * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
 455  * result. Reads of this register at any time return the intermediate CRC value,
 456  * provided the CRC module is configured.
 457  */
 458 typedef union _hw_crc_data
 459 {
 460     uint32_t U;
 461     struct _hw_crc_data_bitfields
 462     {
 463         uint32_t LL : 8;               /*!< [7:0] CRC Low Lower Byte */
 464         uint32_t LU : 8;               /*!< [15:8] CRC Low Upper Byte */
 465         uint32_t HL : 8;               /*!< [23:16] CRC High Lower Byte */
 466         uint32_t HU : 8;               /*!< [31:24] CRC High Upper Byte */
 467     } B;
 468 } hw_crc_data_t;
 469
 470 /*!
 471  * @name Constants and macros for entire CRC_DATA register
 472  */
 473 /*@{*/
 474 #define HW_CRC_DATA_ADDR(x)      ((x) + 0x0U)
 475
 476 #define HW_CRC_DATA(x)           (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR(x))
 477 #define HW_CRC_DATA_RD(x)        (HW_CRC_DATA(x).U)
 478 #define HW_CRC_DATA_WR(x, v)     (HW_CRC_DATA(x).U = (v))
 479 #define HW_CRC_DATA_SET(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) |  (v)))
 480 #define HW_CRC_DATA_CLR(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) & ~(v)))
 481 #define HW_CRC_DATA_TOG(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) ^  (v)))
 482 /*@}*/
 483
 484 /*
 485  * Constants & macros for individual CRC_DATA bitfields
 486  */
 487
 488 /*!
 489  * @name Register CRC_DATA, field LL[7:0] (RW)
 490  *
 491  * When CTRL[WAS] is 1, values written to this field are part of the seed value.
 492  * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
 493  * generation.
 494  */
 495 /*@{*/
 496 #define BP_CRC_DATA_LL       (0U)          /*!< Bit position for CRC_DATA_LL. */
 497 #define BM_CRC_DATA_LL       (0x000000FFU) /*!< Bit mask for CRC_DATA_LL. */
 498 #define BS_CRC_DATA_LL       (8U)          /*!< Bit field size in bits for CRC_DATA_LL. */
 499
 500 /*! @brief Read current value of the CRC_DATA_LL field. */
 501 #define BR_CRC_DATA_LL(x)    (HW_CRC_DATA(x).B.LL)
 502
 503 /*! @brief Format value for bitfield CRC_DATA_LL. */
 504 #define BF_CRC_DATA_LL(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LL) & BM_CRC_DATA_LL)
 505
 506 /*! @brief Set the LL field to a new value. */
 507 #define BW_CRC_DATA_LL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v)))
 508 /*@}*/
 509
 510 /*!
 511  * @name Register CRC_DATA, field LU[15:8] (RW)
 512  *
 513  * When CTRL[WAS] is 1, values written to this field are part of the seed value.
 514  * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
 515  * generation.
 516  */
 517 /*@{*/
 518 #define BP_CRC_DATA_LU       (8U)          /*!< Bit position for CRC_DATA_LU. */
 519 #define BM_CRC_DATA_LU       (0x0000FF00U) /*!< Bit mask for CRC_DATA_LU. */
 520 #define BS_CRC_DATA_LU       (8U)          /*!< Bit field size in bits for CRC_DATA_LU. */
 521
 522 /*! @brief Read current value of the CRC_DATA_LU field. */
 523 #define BR_CRC_DATA_LU(x)    (HW_CRC_DATA(x).B.LU)
 524
 525 /*! @brief Format value for bitfield CRC_DATA_LU. */
 526 #define BF_CRC_DATA_LU(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LU) & BM_CRC_DATA_LU)
 527
 528 /*! @brief Set the LU field to a new value. */
 529 #define BW_CRC_DATA_LU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v)))
 530 /*@}*/
 531
 532 /*!
 533  * @name Register CRC_DATA, field HL[23:16] (RW)
 534  *
 535  * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
 536  * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
 537  * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
 538  * written to this field is used for CRC checksum generation in both 16-bit and
 539  * 32-bit CRC modes.
 540  */
 541 /*@{*/
 542 #define BP_CRC_DATA_HL       (16U)         /*!< Bit position for CRC_DATA_HL. */
 543 #define BM_CRC_DATA_HL       (0x00FF0000U) /*!< Bit mask for CRC_DATA_HL. */
 544 #define BS_CRC_DATA_HL       (8U)          /*!< Bit field size in bits for CRC_DATA_HL. */
 545
 546 /*! @brief Read current value of the CRC_DATA_HL field. */
 547 #define BR_CRC_DATA_HL(x)    (HW_CRC_DATA(x).B.HL)
 548
 549 /*! @brief Format value for bitfield CRC_DATA_HL. */
 550 #define BF_CRC_DATA_HL(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HL) & BM_CRC_DATA_HL)
 551
 552 /*! @brief Set the HL field to a new value. */
 553 #define BW_CRC_DATA_HL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v)))
 554 /*@}*/
 555
 556 /*!
 557  * @name Register CRC_DATA, field HU[31:24] (RW)
 558  *
 559  * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
 560  * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
 561  * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
 562  * written to this field is used for CRC checksum generation in both 16-bit and
 563  * 32-bit CRC modes.
 564  */
 565 /*@{*/
 566 #define BP_CRC_DATA_HU       (24U)         /*!< Bit position for CRC_DATA_HU. */
 567 #define BM_CRC_DATA_HU       (0xFF000000U) /*!< Bit mask for CRC_DATA_HU. */
 568 #define BS_CRC_DATA_HU       (8U)          /*!< Bit field size in bits for CRC_DATA_HU. */
 569
 570 /*! @brief Read current value of the CRC_DATA_HU field. */
 571 #define BR_CRC_DATA_HU(x)    (HW_CRC_DATA(x).B.HU)
 572
 573 /*! @brief Format value for bitfield CRC_DATA_HU. */
 574 #define BF_CRC_DATA_HU(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HU) & BM_CRC_DATA_HU)
 575
 576 /*! @brief Set the HU field to a new value. */
 577 #define BW_CRC_DATA_HU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v)))
 578 /*@}*/
 579
 580 /*******************************************************************************
 581  * HW_CRC_GPOLY - CRC Polynomial register
 582  ******************************************************************************/
 583
 584 /*!
 585  * @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
 586  *
 587  * Reset value: 0x00001021U
 588  *
 589  * This register contains the value of the polynomial for the CRC calculation.
 590  * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
 591  * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
 592  * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
 593  * used in both 16- and 32-bit CRC modes.
 594  */
 595 typedef union _hw_crc_gpoly
 596 {
 597     uint32_t U;
 598     struct _hw_crc_gpoly_bitfields
 599     {
 600         uint32_t LOW : 16;             /*!< [15:0] Low Polynominal Half-word */
 601         uint32_t HIGH : 16;            /*!< [31:16] High Polynominal Half-word */
 602     } B;
 603 } hw_crc_gpoly_t;
 604
 605 /*!
 606  * @name Constants and macros for entire CRC_GPOLY register
 607  */
 608 /*@{*/
 609 #define HW_CRC_GPOLY_ADDR(x)     ((x) + 0x4U)
 610
 611 #define HW_CRC_GPOLY(x)          (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR(x))
 612 #define HW_CRC_GPOLY_RD(x)       (HW_CRC_GPOLY(x).U)
 613 #define HW_CRC_GPOLY_WR(x, v)    (HW_CRC_GPOLY(x).U = (v))
 614 #define HW_CRC_GPOLY_SET(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) |  (v)))
 615 #define HW_CRC_GPOLY_CLR(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) & ~(v)))
 616 #define HW_CRC_GPOLY_TOG(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) ^  (v)))
 617 /*@}*/
 618
 619 /*
 620  * Constants & macros for individual CRC_GPOLY bitfields
 621  */
 622
 623 /*!
 624  * @name Register CRC_GPOLY, field LOW[15:0] (RW)
 625  *
 626  * Writable and readable in both 32-bit and 16-bit CRC modes.
 627  */
 628 /*@{*/
 629 #define BP_CRC_GPOLY_LOW     (0U)          /*!< Bit position for CRC_GPOLY_LOW. */
 630 #define BM_CRC_GPOLY_LOW     (0x0000FFFFU) /*!< Bit mask for CRC_GPOLY_LOW. */
 631 #define BS_CRC_GPOLY_LOW     (16U)         /*!< Bit field size in bits for CRC_GPOLY_LOW. */
 632
 633 /*! @brief Read current value of the CRC_GPOLY_LOW field. */
 634 #define BR_CRC_GPOLY_LOW(x)  (HW_CRC_GPOLY(x).B.LOW)
 635
 636 /*! @brief Format value for bitfield CRC_GPOLY_LOW. */
 637 #define BF_CRC_GPOLY_LOW(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_LOW) & BM_CRC_GPOLY_LOW)
 638
 639 /*! @brief Set the LOW field to a new value. */
 640 #define BW_CRC_GPOLY_LOW(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v)))
 641 /*@}*/
 642
 643 /*!
 644  * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
 645  *
 646  * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
 647  * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
 648  */
 649 /*@{*/
 650 #define BP_CRC_GPOLY_HIGH    (16U)         /*!< Bit position for CRC_GPOLY_HIGH. */
 651 #define BM_CRC_GPOLY_HIGH    (0xFFFF0000U) /*!< Bit mask for CRC_GPOLY_HIGH. */
 652 #define BS_CRC_GPOLY_HIGH    (16U)         /*!< Bit field size in bits for CRC_GPOLY_HIGH. */
 653
 654 /*! @brief Read current value of the CRC_GPOLY_HIGH field. */
 655 #define BR_CRC_GPOLY_HIGH(x) (HW_CRC_GPOLY(x).B.HIGH)
 656
 657 /*! @brief Format value for bitfield CRC_GPOLY_HIGH. */
 658 #define BF_CRC_GPOLY_HIGH(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_HIGH) & BM_CRC_GPOLY_HIGH)
 659
 660 /*! @brief Set the HIGH field to a new value. */
 661 #define BW_CRC_GPOLY_HIGH(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v)))
 662 /*@}*/
 663 /*******************************************************************************
 664  * HW_CRC_GPOLYL - CRC_GPOLYL register.
 665  ******************************************************************************/
 666
 667 /*!
 668  * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
 669  *
 670  * Reset value: 0xFFFFU
 671  */
 672 typedef union _hw_crc_gpolyl
 673 {
 674     uint16_t U;
 675     struct _hw_crc_gpolyl_bitfields
 676     {
 677         uint16_t GPOLYL : 16;          /*!< [15:0] POLYL stores the lower 16 bits of
 678                                         * the 16/32 bit CRC polynomial value */
 679     } B;
 680 } hw_crc_gpolyl_t;
 681
 682 /*!
 683  * @name Constants and macros for entire CRC_GPOLYL register
 684  */
 685 /*@{*/
 686 #define HW_CRC_GPOLYL_ADDR(x)    ((x) + 0x4U)
 687
 688 #define HW_CRC_GPOLYL(x)         (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR(x))
 689 #define HW_CRC_GPOLYL_RD(x)      (HW_CRC_GPOLYL(x).U)
 690 #define HW_CRC_GPOLYL_WR(x, v)   (HW_CRC_GPOLYL(x).U = (v))
 691 #define HW_CRC_GPOLYL_SET(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) |  (v)))
 692 #define HW_CRC_GPOLYL_CLR(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) & ~(v)))
 693 #define HW_CRC_GPOLYL_TOG(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) ^  (v)))
 694 /*@}*/
 695
 696 /*
 697  * Constants & macros for individual CRC_GPOLYL bitfields
 698  */
 699
 700 /*!
 701  * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
 702  */
 703 /*@{*/
 704 #define BP_CRC_GPOLYL_GPOLYL (0U)          /*!< Bit position for CRC_GPOLYL_GPOLYL. */
 705 #define BM_CRC_GPOLYL_GPOLYL (0xFFFFU)     /*!< Bit mask for CRC_GPOLYL_GPOLYL. */
 706 #define BS_CRC_GPOLYL_GPOLYL (16U)         /*!< Bit field size in bits for CRC_GPOLYL_GPOLYL. */
 707
 708 /*! @brief Read current value of the CRC_GPOLYL_GPOLYL field. */
 709 #define BR_CRC_GPOLYL_GPOLYL(x) (HW_CRC_GPOLYL(x).U)
 710
 711 /*! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. */
 712 #define BF_CRC_GPOLYL_GPOLYL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYL_GPOLYL) & BM_CRC_GPOLYL_GPOLYL)
 713
 714 /*! @brief Set the GPOLYL field to a new value. */
 715 #define BW_CRC_GPOLYL_GPOLYL(x, v) (HW_CRC_GPOLYL_WR(x, v))
 716 /*@}*/
 717 /*******************************************************************************
 718  * HW_CRC_GPOLYH - CRC_GPOLYH register.
 719  ******************************************************************************/
 720
 721 /*!
 722  * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
 723  *
 724  * Reset value: 0xFFFFU
 725  */
 726 typedef union _hw_crc_gpolyh
 727 {
 728     uint16_t U;
 729     struct _hw_crc_gpolyh_bitfields
 730     {
 731         uint16_t GPOLYH : 16;          /*!< [15:0] POLYH stores the high 16 bits of
 732                                         * the 16/32 bit CRC polynomial value */
 733     } B;
 734 } hw_crc_gpolyh_t;
 735
 736 /*!
 737  * @name Constants and macros for entire CRC_GPOLYH register
 738  */
 739 /*@{*/
 740 #define HW_CRC_GPOLYH_ADDR(x)    ((x) + 0x6U)
 741
 742 #define HW_CRC_GPOLYH(x)         (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR(x))
 743 #define HW_CRC_GPOLYH_RD(x)      (HW_CRC_GPOLYH(x).U)
 744 #define HW_CRC_GPOLYH_WR(x, v)   (HW_CRC_GPOLYH(x).U = (v))
 745 #define HW_CRC_GPOLYH_SET(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) |  (v)))
 746 #define HW_CRC_GPOLYH_CLR(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) & ~(v)))
 747 #define HW_CRC_GPOLYH_TOG(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) ^  (v)))
 748 /*@}*/
 749
 750 /*
 751  * Constants & macros for individual CRC_GPOLYH bitfields
 752  */
 753
 754 /*!
 755  * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
 756  */
 757 /*@{*/
 758 #define BP_CRC_GPOLYH_GPOLYH (0U)          /*!< Bit position for CRC_GPOLYH_GPOLYH. */
 759 #define BM_CRC_GPOLYH_GPOLYH (0xFFFFU)     /*!< Bit mask for CRC_GPOLYH_GPOLYH. */
 760 #define BS_CRC_GPOLYH_GPOLYH (16U)         /*!< Bit field size in bits for CRC_GPOLYH_GPOLYH. */
 761
 762 /*! @brief Read current value of the CRC_GPOLYH_GPOLYH field. */
 763 #define BR_CRC_GPOLYH_GPOLYH(x) (HW_CRC_GPOLYH(x).U)
 764
 765 /*! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. */
 766 #define BF_CRC_GPOLYH_GPOLYH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYH_GPOLYH) & BM_CRC_GPOLYH_GPOLYH)
 767
 768 /*! @brief Set the GPOLYH field to a new value. */
 769 #define BW_CRC_GPOLYH_GPOLYH(x, v) (HW_CRC_GPOLYH_WR(x, v))
 770 /*@}*/
 771 /*******************************************************************************
 772  * HW_CRC_GPOLYLL - CRC_GPOLYLL register.
 773  ******************************************************************************/
 774
 775 /*!
 776  * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
 777  *
 778  * Reset value: 0xFFU
 779  */
 780 typedef union _hw_crc_gpolyll
 781 {
 782     uint8_t U;
 783     struct _hw_crc_gpolyll_bitfields
 784     {
 785         uint8_t GPOLYLL : 8;           /*!< [7:0] POLYLL stores the first 8 bits of the
 786                                         * 32 bit CRC */
 787     } B;
 788 } hw_crc_gpolyll_t;
 789
 790 /*!
 791  * @name Constants and macros for entire CRC_GPOLYLL register
 792  */
 793 /*@{*/
 794 #define HW_CRC_GPOLYLL_ADDR(x)   ((x) + 0x4U)
 795
 796 #define HW_CRC_GPOLYLL(x)        (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR(x))
 797 #define HW_CRC_GPOLYLL_RD(x)     (HW_CRC_GPOLYLL(x).U)
 798 #define HW_CRC_GPOLYLL_WR(x, v)  (HW_CRC_GPOLYLL(x).U = (v))
 799 #define HW_CRC_GPOLYLL_SET(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) |  (v)))
 800 #define HW_CRC_GPOLYLL_CLR(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) & ~(v)))
 801 #define HW_CRC_GPOLYLL_TOG(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) ^  (v)))
 802 /*@}*/
 803
 804 /*
 805  * Constants & macros for individual CRC_GPOLYLL bitfields
 806  */
 807
 808 /*!
 809  * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
 810  */
 811 /*@{*/
 812 #define BP_CRC_GPOLYLL_GPOLYLL (0U)        /*!< Bit position for CRC_GPOLYLL_GPOLYLL. */
 813 #define BM_CRC_GPOLYLL_GPOLYLL (0xFFU)     /*!< Bit mask for CRC_GPOLYLL_GPOLYLL. */
 814 #define BS_CRC_GPOLYLL_GPOLYLL (8U)        /*!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. */
 815
 816 /*! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. */
 817 #define BR_CRC_GPOLYLL_GPOLYLL(x) (HW_CRC_GPOLYLL(x).U)
 818
 819 /*! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. */
 820 #define BF_CRC_GPOLYLL_GPOLYLL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLL_GPOLYLL) & BM_CRC_GPOLYLL_GPOLYLL)
 821
 822 /*! @brief Set the GPOLYLL field to a new value. */
 823 #define BW_CRC_GPOLYLL_GPOLYLL(x, v) (HW_CRC_GPOLYLL_WR(x, v))
 824 /*@}*/
 825 /*******************************************************************************
 826  * HW_CRC_GPOLYLU - CRC_GPOLYLU register.
 827  ******************************************************************************/
 828
 829 /*!
 830  * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
 831  *
 832  * Reset value: 0xFFU
 833  */
 834 typedef union _hw_crc_gpolylu
 835 {
 836     uint8_t U;
 837     struct _hw_crc_gpolylu_bitfields
 838     {
 839         uint8_t GPOLYLU : 8;           /*!< [7:0] POLYLL stores the second 8 bits of
 840                                         * the 32 bit CRC */
 841     } B;
 842 } hw_crc_gpolylu_t;
 843
 844 /*!
 845  * @name Constants and macros for entire CRC_GPOLYLU register
 846  */
 847 /*@{*/
 848 #define HW_CRC_GPOLYLU_ADDR(x)   ((x) + 0x5U)
 849
 850 #define HW_CRC_GPOLYLU(x)        (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR(x))
 851 #define HW_CRC_GPOLYLU_RD(x)     (HW_CRC_GPOLYLU(x).U)
 852 #define HW_CRC_GPOLYLU_WR(x, v)  (HW_CRC_GPOLYLU(x).U = (v))
 853 #define HW_CRC_GPOLYLU_SET(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) |  (v)))
 854 #define HW_CRC_GPOLYLU_CLR(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) & ~(v)))
 855 #define HW_CRC_GPOLYLU_TOG(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) ^  (v)))
 856 /*@}*/
 857
 858 /*
 859  * Constants & macros for individual CRC_GPOLYLU bitfields
 860  */
 861
 862 /*!
 863  * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
 864  */
 865 /*@{*/
 866 #define BP_CRC_GPOLYLU_GPOLYLU (0U)        /*!< Bit position for CRC_GPOLYLU_GPOLYLU. */
 867 #define BM_CRC_GPOLYLU_GPOLYLU (0xFFU)     /*!< Bit mask for CRC_GPOLYLU_GPOLYLU. */
 868 #define BS_CRC_GPOLYLU_GPOLYLU (8U)        /*!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. */
 869
 870 /*! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. */
 871 #define BR_CRC_GPOLYLU_GPOLYLU(x) (HW_CRC_GPOLYLU(x).U)
 872
 873 /*! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. */
 874 #define BF_CRC_GPOLYLU_GPOLYLU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLU_GPOLYLU) & BM_CRC_GPOLYLU_GPOLYLU)
 875
 876 /*! @brief Set the GPOLYLU field to a new value. */
 877 #define BW_CRC_GPOLYLU_GPOLYLU(x, v) (HW_CRC_GPOLYLU_WR(x, v))
 878 /*@}*/
 879 /*******************************************************************************
 880  * HW_CRC_GPOLYHL - CRC_GPOLYHL register.
 881  ******************************************************************************/
 882
 883 /*!
 884  * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
 885  *
 886  * Reset value: 0xFFU
 887  */
 888 typedef union _hw_crc_gpolyhl
 889 {
 890     uint8_t U;
 891     struct _hw_crc_gpolyhl_bitfields
 892     {
 893         uint8_t GPOLYHL : 8;           /*!< [7:0] POLYHL stores the third 8 bits of the
 894                                         * 32 bit CRC */
 895     } B;
 896 } hw_crc_gpolyhl_t;
 897
 898 /*!
 899  * @name Constants and macros for entire CRC_GPOLYHL register
 900  */
 901 /*@{*/
 902 #define HW_CRC_GPOLYHL_ADDR(x)   ((x) + 0x6U)
 903
 904 #define HW_CRC_GPOLYHL(x)        (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR(x))
 905 #define HW_CRC_GPOLYHL_RD(x)     (HW_CRC_GPOLYHL(x).U)
 906 #define HW_CRC_GPOLYHL_WR(x, v)  (HW_CRC_GPOLYHL(x).U = (v))
 907 #define HW_CRC_GPOLYHL_SET(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) |  (v)))
 908 #define HW_CRC_GPOLYHL_CLR(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) & ~(v)))
 909 #define HW_CRC_GPOLYHL_TOG(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) ^  (v)))
 910 /*@}*/
 911
 912 /*
 913  * Constants & macros for individual CRC_GPOLYHL bitfields
 914  */
 915
 916 /*!
 917  * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
 918  */
 919 /*@{*/
 920 #define BP_CRC_GPOLYHL_GPOLYHL (0U)        /*!< Bit position for CRC_GPOLYHL_GPOLYHL. */
 921 #define BM_CRC_GPOLYHL_GPOLYHL (0xFFU)     /*!< Bit mask for CRC_GPOLYHL_GPOLYHL. */
 922 #define BS_CRC_GPOLYHL_GPOLYHL (8U)        /*!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. */
 923
 924 /*! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. */
 925 #define BR_CRC_GPOLYHL_GPOLYHL(x) (HW_CRC_GPOLYHL(x).U)
 926
 927 /*! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. */
 928 #define BF_CRC_GPOLYHL_GPOLYHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHL_GPOLYHL) & BM_CRC_GPOLYHL_GPOLYHL)
 929
 930 /*! @brief Set the GPOLYHL field to a new value. */
 931 #define BW_CRC_GPOLYHL_GPOLYHL(x, v) (HW_CRC_GPOLYHL_WR(x, v))
 932 /*@}*/
 933 /*******************************************************************************
 934  * HW_CRC_GPOLYHU - CRC_GPOLYHU register.
 935  ******************************************************************************/
 936
 937 /*!
 938  * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
 939  *
 940  * Reset value: 0xFFU
 941  */
 942 typedef union _hw_crc_gpolyhu
 943 {
 944     uint8_t U;
 945     struct _hw_crc_gpolyhu_bitfields
 946     {
 947         uint8_t GPOLYHU : 8;           /*!< [7:0] POLYHU stores the fourth 8 bits of
 948                                         * the 32 bit CRC */
 949     } B;
 950 } hw_crc_gpolyhu_t;
 951
 952 /*!
 953  * @name Constants and macros for entire CRC_GPOLYHU register
 954  */
 955 /*@{*/
 956 #define HW_CRC_GPOLYHU_ADDR(x)   ((x) + 0x7U)
 957
 958 #define HW_CRC_GPOLYHU(x)        (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR(x))
 959 #define HW_CRC_GPOLYHU_RD(x)     (HW_CRC_GPOLYHU(x).U)
 960 #define HW_CRC_GPOLYHU_WR(x, v)  (HW_CRC_GPOLYHU(x).U = (v))
 961 #define HW_CRC_GPOLYHU_SET(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) |  (v)))
 962 #define HW_CRC_GPOLYHU_CLR(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) & ~(v)))
 963 #define HW_CRC_GPOLYHU_TOG(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) ^  (v)))
 964 /*@}*/
 965
 966 /*
 967  * Constants & macros for individual CRC_GPOLYHU bitfields
 968  */
 969
 970 /*!
 971  * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
 972  */
 973 /*@{*/
 974 #define BP_CRC_GPOLYHU_GPOLYHU (0U)        /*!< Bit position for CRC_GPOLYHU_GPOLYHU. */
 975 #define BM_CRC_GPOLYHU_GPOLYHU (0xFFU)     /*!< Bit mask for CRC_GPOLYHU_GPOLYHU. */
 976 #define BS_CRC_GPOLYHU_GPOLYHU (8U)        /*!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. */
 977
 978 /*! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. */
 979 #define BR_CRC_GPOLYHU_GPOLYHU(x) (HW_CRC_GPOLYHU(x).U)
 980
 981 /*! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. */
 982 #define BF_CRC_GPOLYHU_GPOLYHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHU_GPOLYHU) & BM_CRC_GPOLYHU_GPOLYHU)
 983
 984 /*! @brief Set the GPOLYHU field to a new value. */
 985 #define BW_CRC_GPOLYHU_GPOLYHU(x, v) (HW_CRC_GPOLYHU_WR(x, v))
 986 /*@}*/
 987
 988 /*******************************************************************************
 989  * HW_CRC_CTRL - CRC Control register
 990  ******************************************************************************/
 991
 992 /*!
 993  * @brief HW_CRC_CTRL - CRC Control register (RW)
 994  *
 995  * Reset value: 0x00000000U
 996  *
 997  * This register controls the configuration and working of the CRC module.
 998  * Appropriate bits must be set before starting a new CRC calculation. A new CRC
 999  * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
1000  * the CRC data register.
1001  */
1002 typedef union _hw_crc_ctrl
1003 {
1004     uint32_t U;
1005     struct _hw_crc_ctrl_bitfields
1006     {
1007         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
1008         uint32_t TCRC : 1;             /*!< [24]  */
1009         uint32_t WAS : 1;              /*!< [25] Write CRC Data Register As Seed */
1010         uint32_t FXOR : 1;             /*!< [26] Complement Read Of CRC Data Register */
1011         uint32_t RESERVED1 : 1;        /*!< [27]  */
1012         uint32_t TOTR : 2;             /*!< [29:28] Type Of Transpose For Read */
1013         uint32_t TOT : 2;              /*!< [31:30] Type Of Transpose For Writes */
1014     } B;
1015 } hw_crc_ctrl_t;
1016
1017 /*!
1018  * @name Constants and macros for entire CRC_CTRL register
1019  */
1020 /*@{*/
1021 #define HW_CRC_CTRL_ADDR(x)      ((x) + 0x8U)
1022
1023 #define HW_CRC_CTRL(x)           (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR(x))
1024 #define HW_CRC_CTRL_RD(x)        (HW_CRC_CTRL(x).U)
1025 #define HW_CRC_CTRL_WR(x, v)     (HW_CRC_CTRL(x).U = (v))
1026 #define HW_CRC_CTRL_SET(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) |  (v)))
1027 #define HW_CRC_CTRL_CLR(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) & ~(v)))
1028 #define HW_CRC_CTRL_TOG(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) ^  (v)))
1029 /*@}*/
1030
1031 /*
1032  * Constants & macros for individual CRC_CTRL bitfields
1033  */
1034
1035 /*!
1036  * @name Register CRC_CTRL, field TCRC[24] (RW)
1037  *
1038  * Width of CRC protocol.
1039  *
1040  * Values:
1041  * - 0 - 16-bit CRC protocol.
1042  * - 1 - 32-bit CRC protocol.
1043  */
1044 /*@{*/
1045 #define BP_CRC_CTRL_TCRC     (24U)         /*!< Bit position for CRC_CTRL_TCRC. */
1046 #define BM_CRC_CTRL_TCRC     (0x01000000U) /*!< Bit mask for CRC_CTRL_TCRC. */
1047 #define BS_CRC_CTRL_TCRC     (1U)          /*!< Bit field size in bits for CRC_CTRL_TCRC. */
1048
1049 /*! @brief Read current value of the CRC_CTRL_TCRC field. */
1050 #define BR_CRC_CTRL_TCRC(x)  (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC))
1051
1052 /*! @brief Format value for bitfield CRC_CTRL_TCRC. */
1053 #define BF_CRC_CTRL_TCRC(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TCRC) & BM_CRC_CTRL_TCRC)
1054
1055 /*! @brief Set the TCRC field to a new value. */
1056 #define BW_CRC_CTRL_TCRC(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC) = (v))
1057 /*@}*/
1058
1059 /*!
1060  * @name Register CRC_CTRL, field WAS[25] (RW)
1061  *
1062  * When asserted, a value written to the CRC data register is considered a seed
1063  * value. When deasserted, a value written to the CRC data register is taken as
1064  * data for CRC computation.
1065  *
1066  * Values:
1067  * - 0 - Writes to the CRC data register are data values.
1068  * - 1 - Writes to the CRC data register are seed values.
1069  */
1070 /*@{*/
1071 #define BP_CRC_CTRL_WAS      (25U)         /*!< Bit position for CRC_CTRL_WAS. */
1072 #define BM_CRC_CTRL_WAS      (0x02000000U) /*!< Bit mask for CRC_CTRL_WAS. */
1073 #define BS_CRC_CTRL_WAS      (1U)          /*!< Bit field size in bits for CRC_CTRL_WAS. */
1074
1075 /*! @brief Read current value of the CRC_CTRL_WAS field. */
1076 #define BR_CRC_CTRL_WAS(x)   (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS))
1077
1078 /*! @brief Format value for bitfield CRC_CTRL_WAS. */
1079 #define BF_CRC_CTRL_WAS(v)   ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_WAS) & BM_CRC_CTRL_WAS)
1080
1081 /*! @brief Set the WAS field to a new value. */
1082 #define BW_CRC_CTRL_WAS(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS) = (v))
1083 /*@}*/
1084
1085 /*!
1086  * @name Register CRC_CTRL, field FXOR[26] (RW)
1087  *
1088  * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
1089  * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
1090  *
1091  * Values:
1092  * - 0 - No XOR on reading.
1093  * - 1 - Invert or complement the read value of the CRC Data register.
1094  */
1095 /*@{*/
1096 #define BP_CRC_CTRL_FXOR     (26U)         /*!< Bit position for CRC_CTRL_FXOR. */
1097 #define BM_CRC_CTRL_FXOR     (0x04000000U) /*!< Bit mask for CRC_CTRL_FXOR. */
1098 #define BS_CRC_CTRL_FXOR     (1U)          /*!< Bit field size in bits for CRC_CTRL_FXOR. */
1099
1100 /*! @brief Read current value of the CRC_CTRL_FXOR field. */
1101 #define BR_CRC_CTRL_FXOR(x)  (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR))
1102
1103 /*! @brief Format value for bitfield CRC_CTRL_FXOR. */
1104 #define BF_CRC_CTRL_FXOR(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_FXOR) & BM_CRC_CTRL_FXOR)
1105
1106 /*! @brief Set the FXOR field to a new value. */
1107 #define BW_CRC_CTRL_FXOR(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR) = (v))
1108 /*@}*/
1109
1110 /*!
1111  * @name Register CRC_CTRL, field TOTR[29:28] (RW)
1112  *
1113  * Identifies the transpose configuration of the value read from the CRC Data
1114  * register. See the description of the transpose feature for the available
1115  * transpose options.
1116  *
1117  * Values:
1118  * - 00 - No transposition.
1119  * - 01 - Bits in bytes are transposed; bytes are not transposed.
1120  * - 10 - Both bits in bytes and bytes are transposed.
1121  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1122  */
1123 /*@{*/
1124 #define BP_CRC_CTRL_TOTR     (28U)         /*!< Bit position for CRC_CTRL_TOTR. */
1125 #define BM_CRC_CTRL_TOTR     (0x30000000U) /*!< Bit mask for CRC_CTRL_TOTR. */
1126 #define BS_CRC_CTRL_TOTR     (2U)          /*!< Bit field size in bits for CRC_CTRL_TOTR. */
1127
1128 /*! @brief Read current value of the CRC_CTRL_TOTR field. */
1129 #define BR_CRC_CTRL_TOTR(x)  (HW_CRC_CTRL(x).B.TOTR)
1130
1131 /*! @brief Format value for bitfield CRC_CTRL_TOTR. */
1132 #define BF_CRC_CTRL_TOTR(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOTR) & BM_CRC_CTRL_TOTR)
1133
1134 /*! @brief Set the TOTR field to a new value. */
1135 #define BW_CRC_CTRL_TOTR(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v)))
1136 /*@}*/
1137
1138 /*!
1139  * @name Register CRC_CTRL, field TOT[31:30] (RW)
1140  *
1141  * Defines the transpose configuration of the data written to the CRC data
1142  * register. See the description of the transpose feature for the available transpose
1143  * options.
1144  *
1145  * Values:
1146  * - 00 - No transposition.
1147  * - 01 - Bits in bytes are transposed; bytes are not transposed.
1148  * - 10 - Both bits in bytes and bytes are transposed.
1149  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1150  */
1151 /*@{*/
1152 #define BP_CRC_CTRL_TOT      (30U)         /*!< Bit position for CRC_CTRL_TOT. */
1153 #define BM_CRC_CTRL_TOT      (0xC0000000U) /*!< Bit mask for CRC_CTRL_TOT. */
1154 #define BS_CRC_CTRL_TOT      (2U)          /*!< Bit field size in bits for CRC_CTRL_TOT. */
1155
1156 /*! @brief Read current value of the CRC_CTRL_TOT field. */
1157 #define BR_CRC_CTRL_TOT(x)   (HW_CRC_CTRL(x).B.TOT)
1158
1159 /*! @brief Format value for bitfield CRC_CTRL_TOT. */
1160 #define BF_CRC_CTRL_TOT(v)   ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOT) & BM_CRC_CTRL_TOT)
1161
1162 /*! @brief Set the TOT field to a new value. */
1163 #define BW_CRC_CTRL_TOT(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v)))
1164 /*@}*/
1165 /*******************************************************************************
1166  * HW_CRC_CTRLHU - CRC_CTRLHU register.
1167  ******************************************************************************/
1168
1169 /*!
1170  * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
1171  *
1172  * Reset value: 0x00U
1173  */
1174 typedef union _hw_crc_ctrlhu
1175 {
1176     uint8_t U;
1177     struct _hw_crc_ctrlhu_bitfields
1178     {
1179         uint8_t TCRC : 1;              /*!< [0]  */
1180         uint8_t WAS : 1;               /*!< [1]  */
1181         uint8_t FXOR : 1;              /*!< [2]  */
1182         uint8_t RESERVED0 : 1;         /*!< [3]  */
1183         uint8_t TOTR : 2;              /*!< [5:4]  */
1184         uint8_t TOT : 2;               /*!< [7:6]  */
1185     } B;
1186 } hw_crc_ctrlhu_t;
1187
1188 /*!
1189  * @name Constants and macros for entire CRC_CTRLHU register
1190  */
1191 /*@{*/
1192 #define HW_CRC_CTRLHU_ADDR(x)    ((x) + 0xBU)
1193
1194 #define HW_CRC_CTRLHU(x)         (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR(x))
1195 #define HW_CRC_CTRLHU_RD(x)      (HW_CRC_CTRLHU(x).U)
1196 #define HW_CRC_CTRLHU_WR(x, v)   (HW_CRC_CTRLHU(x).U = (v))
1197 #define HW_CRC_CTRLHU_SET(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) |  (v)))
1198 #define HW_CRC_CTRLHU_CLR(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) & ~(v)))
1199 #define HW_CRC_CTRLHU_TOG(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) ^  (v)))
1200 /*@}*/
1201
1202 /*
1203  * Constants & macros for individual CRC_CTRLHU bitfields
1204  */
1205
1206 /*!
1207  * @name Register CRC_CTRLHU, field TCRC[0] (RW)
1208  *
1209  * Values:
1210  * - 0 - 16-bit CRC protocol.
1211  * - 1 - 32-bit CRC protocol.
1212  */
1213 /*@{*/
1214 #define BP_CRC_CTRLHU_TCRC   (0U)          /*!< Bit position for CRC_CTRLHU_TCRC. */
1215 #define BM_CRC_CTRLHU_TCRC   (0x01U)       /*!< Bit mask for CRC_CTRLHU_TCRC. */
1216 #define BS_CRC_CTRLHU_TCRC   (1U)          /*!< Bit field size in bits for CRC_CTRLHU_TCRC. */
1217
1218 /*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
1219 #define BR_CRC_CTRLHU_TCRC(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC))
1220
1221 /*! @brief Format value for bitfield CRC_CTRLHU_TCRC. */
1222 #define BF_CRC_CTRLHU_TCRC(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TCRC) & BM_CRC_CTRLHU_TCRC)
1223
1224 /*! @brief Set the TCRC field to a new value. */
1225 #define BW_CRC_CTRLHU_TCRC(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC) = (v))
1226 /*@}*/
1227
1228 /*!
1229  * @name Register CRC_CTRLHU, field WAS[1] (RW)
1230  *
1231  * Values:
1232  * - 0 - Writes to CRC data register are data values.
1233  * - 1 - Writes to CRC data reguster are seed values.
1234  */
1235 /*@{*/
1236 #define BP_CRC_CTRLHU_WAS    (1U)          /*!< Bit position for CRC_CTRLHU_WAS. */
1237 #define BM_CRC_CTRLHU_WAS    (0x02U)       /*!< Bit mask for CRC_CTRLHU_WAS. */
1238 #define BS_CRC_CTRLHU_WAS    (1U)          /*!< Bit field size in bits for CRC_CTRLHU_WAS. */
1239
1240 /*! @brief Read current value of the CRC_CTRLHU_WAS field. */
1241 #define BR_CRC_CTRLHU_WAS(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS))
1242
1243 /*! @brief Format value for bitfield CRC_CTRLHU_WAS. */
1244 #define BF_CRC_CTRLHU_WAS(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_WAS) & BM_CRC_CTRLHU_WAS)
1245
1246 /*! @brief Set the WAS field to a new value. */
1247 #define BW_CRC_CTRLHU_WAS(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS) = (v))
1248 /*@}*/
1249
1250 /*!
1251  * @name Register CRC_CTRLHU, field FXOR[2] (RW)
1252  *
1253  * Values:
1254  * - 0 - No XOR on reading.
1255  * - 1 - Invert or complement the read value of CRC data register.
1256  */
1257 /*@{*/
1258 #define BP_CRC_CTRLHU_FXOR   (2U)          /*!< Bit position for CRC_CTRLHU_FXOR. */
1259 #define BM_CRC_CTRLHU_FXOR   (0x04U)       /*!< Bit mask for CRC_CTRLHU_FXOR. */
1260 #define BS_CRC_CTRLHU_FXOR   (1U)          /*!< Bit field size in bits for CRC_CTRLHU_FXOR. */
1261
1262 /*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
1263 #define BR_CRC_CTRLHU_FXOR(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR))
1264
1265 /*! @brief Format value for bitfield CRC_CTRLHU_FXOR. */
1266 #define BF_CRC_CTRLHU_FXOR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_FXOR) & BM_CRC_CTRLHU_FXOR)
1267
1268 /*! @brief Set the FXOR field to a new value. */
1269 #define BW_CRC_CTRLHU_FXOR(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR) = (v))
1270 /*@}*/
1271
1272 /*!
1273  * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
1274  *
1275  * Values:
1276  * - 00 - No Transposition.
1277  * - 01 - Bits in bytes are transposed, bytes are not transposed.
1278  * - 10 - Both bits in bytes and bytes are transposed.
1279  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1280  */
1281 /*@{*/
1282 #define BP_CRC_CTRLHU_TOTR   (4U)          /*!< Bit position for CRC_CTRLHU_TOTR. */
1283 #define BM_CRC_CTRLHU_TOTR   (0x30U)       /*!< Bit mask for CRC_CTRLHU_TOTR. */
1284 #define BS_CRC_CTRLHU_TOTR   (2U)          /*!< Bit field size in bits for CRC_CTRLHU_TOTR. */
1285
1286 /*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
1287 #define BR_CRC_CTRLHU_TOTR(x) (HW_CRC_CTRLHU(x).B.TOTR)
1288
1289 /*! @brief Format value for bitfield CRC_CTRLHU_TOTR. */
1290 #define BF_CRC_CTRLHU_TOTR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOTR) & BM_CRC_CTRLHU_TOTR)
1291
1292 /*! @brief Set the TOTR field to a new value. */
1293 #define BW_CRC_CTRLHU_TOTR(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v)))
1294 /*@}*/
1295
1296 /*!
1297  * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
1298  *
1299  * Values:
1300  * - 00 - No Transposition.
1301  * - 01 - Bits in bytes are transposed, bytes are not transposed.
1302  * - 10 - Both bits in bytes and bytes are transposed.
1303  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1304  */
1305 /*@{*/
1306 #define BP_CRC_CTRLHU_TOT    (6U)          /*!< Bit position for CRC_CTRLHU_TOT. */
1307 #define BM_CRC_CTRLHU_TOT    (0xC0U)       /*!< Bit mask for CRC_CTRLHU_TOT. */
1308 #define BS_CRC_CTRLHU_TOT    (2U)          /*!< Bit field size in bits for CRC_CTRLHU_TOT. */
1309
1310 /*! @brief Read current value of the CRC_CTRLHU_TOT field. */
1311 #define BR_CRC_CTRLHU_TOT(x) (HW_CRC_CTRLHU(x).B.TOT)
1312
1313 /*! @brief Format value for bitfield CRC_CTRLHU_TOT. */
1314 #define BF_CRC_CTRLHU_TOT(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOT) & BM_CRC_CTRLHU_TOT)
1315
1316 /*! @brief Set the TOT field to a new value. */
1317 #define BW_CRC_CTRLHU_TOT(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v)))
1318 /*@}*/
1319
1320 /*
1321 ** Start of section using anonymous unions
1322 */
1323
1324 #if defined(__ARMCC_VERSION)
1325   #pragma push
1326   #pragma anon_unions
1327 #elif defined(__CWCC__)
1328   #pragma push
1329   #pragma cpp_extensions on
1330 #elif defined(__GNUC__)
1331   /* anonymous unions are enabled by default */
1332 #elif defined(__IAR_SYSTEMS_ICC__)
1333   #pragma language=extended
1334 #else
1335   #error Not supported compiler type
1336 #endif
1337
1338 /*******************************************************************************
1339  * hw_crc_t - module struct
1340  ******************************************************************************/
1341 /*!
1342  * @brief All CRC module registers.
1343  */
1344 #pragma pack(1)
1345 typedef struct _hw_crc
1346 {
1347     union {
1348         struct {
1349             __IO hw_crc_datal_t DATAL;     /*!< [0x0] CRC_DATAL register. */
1350             __IO hw_crc_datah_t DATAH;     /*!< [0x2] CRC_DATAH register. */
1351         } ACCESS16BIT;
1352         struct {
1353             __IO hw_crc_datall_t DATALL;   /*!< [0x0] CRC_DATALL register. */
1354             __IO hw_crc_datalu_t DATALU;   /*!< [0x1] CRC_DATALU register. */
1355             __IO hw_crc_datahl_t DATAHL;   /*!< [0x2] CRC_DATAHL register. */
1356             __IO hw_crc_datahu_t DATAHU;   /*!< [0x3] CRC_DATAHU register. */
1357         } ACCESS8BIT;
1358         __IO hw_crc_data_t DATA;           /*!< [0x0] CRC Data register */
1359     };
1360     union {
1361         __IO hw_crc_gpoly_t GPOLY;         /*!< [0x4] CRC Polynomial register */
1362         struct {
1363             __IO hw_crc_gpolyl_t GPOLYL;   /*!< [0x4] CRC_GPOLYL register. */
1364             __IO hw_crc_gpolyh_t GPOLYH;   /*!< [0x6] CRC_GPOLYH register. */
1365         } GPOLY_ACCESS16BIT;
1366         struct {
1367             __IO hw_crc_gpolyll_t GPOLYLL; /*!< [0x4] CRC_GPOLYLL register. */
1368             __IO hw_crc_gpolylu_t GPOLYLU; /*!< [0x5] CRC_GPOLYLU register. */
1369             __IO hw_crc_gpolyhl_t GPOLYHL; /*!< [0x6] CRC_GPOLYHL register. */
1370             __IO hw_crc_gpolyhu_t GPOLYHU; /*!< [0x7] CRC_GPOLYHU register. */
1371         } GPOLY_ACCESS8BIT;
1372     };
1373     union {
1374         __IO hw_crc_ctrl_t CTRL;           /*!< [0x8] CRC Control register */
1375         struct {
1376             uint8_t _reserved0[3];
1377             __IO hw_crc_ctrlhu_t CTRLHU;   /*!< [0xB] CRC_CTRLHU register. */
1378         } CTRL_ACCESS8BIT;
1379     };
1380 } hw_crc_t;
1381 #pragma pack()
1382
1383 /*! @brief Macro to access all CRC registers. */
1384 /*! @param x CRC module instance base address. */
1385 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1386  *     use the '&' operator, like <code>&HW_CRC(CRC_BASE)</code>. */
1387 #define HW_CRC(x)      (*(hw_crc_t *)(x))
1388
1389 /*
1390 ** End of section using anonymous unions
1391 */
1392
1393 #if defined(__ARMCC_VERSION)
1394   #pragma pop
1395 #elif defined(__CWCC__)
1396   #pragma pop
1397 #elif defined(__GNUC__)
1398   /* leave anonymous unions enabled */
1399 #elif defined(__IAR_SYSTEMS_ICC__)
1400   #pragma language=default
1401 #else
1402   #error Not supported compiler type
1403 #endif
1404
1405 #endif /* __HW_CRC_REGISTERS_H__ */
1406 /* EOF */