tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_FB_REGISTERS_H__
  78 #define __HW_FB_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 FB
  85  *
  86  * FlexBus external bus interface
  87  *
  88  * Registers defined in this header file:
  89  * - HW_FB_CSARn - Chip Select Address Register
  90  * - HW_FB_CSMRn - Chip Select Mask Register
  91  * - HW_FB_CSCRn - Chip Select Control Register
  92  * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
  93  *
  94  * - hw_fb_t - Struct containing all module registers.
  95  */
  96
  97 #define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
  98
  99 /*******************************************************************************
 100  * HW_FB_CSARn - Chip Select Address Register
 101  ******************************************************************************/
 102
 103 /*!
 104  * @brief HW_FB_CSARn - Chip Select Address Register (RW)
 105  *
 106  * Reset value: 0x00000000U
 107  *
 108  * Specifies the associated chip-select's base address.
 109  */
 110 typedef union _hw_fb_csarn
 111 {
 112     uint32_t U;
 113     struct _hw_fb_csarn_bitfields
 114     {
 115         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
 116         uint32_t BA : 16;              /*!< [31:16] Base Address */
 117     } B;
 118 } hw_fb_csarn_t;
 119
 120 /*!
 121  * @name Constants and macros for entire FB_CSARn register
 122  */
 123 /*@{*/
 124 #define HW_FB_CSARn_COUNT (6U)
 125
 126 #define HW_FB_CSARn_ADDR(x, n)   ((x) + 0x0U + (0xCU * (n)))
 127
 128 #define HW_FB_CSARn(x, n)        (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n))
 129 #define HW_FB_CSARn_RD(x, n)     (HW_FB_CSARn(x, n).U)
 130 #define HW_FB_CSARn_WR(x, n, v)  (HW_FB_CSARn(x, n).U = (v))
 131 #define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) |  (v)))
 132 #define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v)))
 133 #define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^  (v)))
 134 /*@}*/
 135
 136 /*
 137  * Constants & macros for individual FB_CSARn bitfields
 138  */
 139
 140 /*!
 141  * @name Register FB_CSARn, field BA[31:16] (RW)
 142  *
 143  * Defines the base address for memory dedicated to the associated chip-select.
 144  * BA is compared to bits 31-16 on the internal address bus to determine if the
 145  * associated chip-select's memory is being accessed. Because the FlexBus module
 146  * is one of the slaves connected to the crossbar switch, it is only accessible
 147  * within a certain memory range. See the chip memory map for the applicable
 148  * FlexBus "expansion" address range for which the chip-selects can be active. Set the
 149  * CSARn and CSMRn registers appropriately before accessing this region.
 150  */
 151 /*@{*/
 152 #define BP_FB_CSARn_BA       (16U)         /*!< Bit position for FB_CSARn_BA. */
 153 #define BM_FB_CSARn_BA       (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */
 154 #define BS_FB_CSARn_BA       (16U)         /*!< Bit field size in bits for FB_CSARn_BA. */
 155
 156 /*! @brief Read current value of the FB_CSARn_BA field. */
 157 #define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA)
 158
 159 /*! @brief Format value for bitfield FB_CSARn_BA. */
 160 #define BF_FB_CSARn_BA(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA)
 161
 162 /*! @brief Set the BA field to a new value. */
 163 #define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
 164 /*@}*/
 165 /*******************************************************************************
 166  * HW_FB_CSMRn - Chip Select Mask Register
 167  ******************************************************************************/
 168
 169 /*!
 170  * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
 171  *
 172  * Reset value: 0x00000000U
 173  *
 174  * Specifies the address mask and allowable access types for the associated
 175  * chip-select.
 176  */
 177 typedef union _hw_fb_csmrn
 178 {
 179     uint32_t U;
 180     struct _hw_fb_csmrn_bitfields
 181     {
 182         uint32_t V : 1;                /*!< [0] Valid */
 183         uint32_t RESERVED0 : 7;        /*!< [7:1]  */
 184         uint32_t WP : 1;               /*!< [8] Write Protect */
 185         uint32_t RESERVED1 : 7;        /*!< [15:9]  */
 186         uint32_t BAM : 16;             /*!< [31:16] Base Address Mask */
 187     } B;
 188 } hw_fb_csmrn_t;
 189
 190 /*!
 191  * @name Constants and macros for entire FB_CSMRn register
 192  */
 193 /*@{*/
 194 #define HW_FB_CSMRn_COUNT (6U)
 195
 196 #define HW_FB_CSMRn_ADDR(x, n)   ((x) + 0x4U + (0xCU * (n)))
 197
 198 #define HW_FB_CSMRn(x, n)        (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n))
 199 #define HW_FB_CSMRn_RD(x, n)     (HW_FB_CSMRn(x, n).U)
 200 #define HW_FB_CSMRn_WR(x, n, v)  (HW_FB_CSMRn(x, n).U = (v))
 201 #define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) |  (v)))
 202 #define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v)))
 203 #define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^  (v)))
 204 /*@}*/
 205
 206 /*
 207  * Constants & macros for individual FB_CSMRn bitfields
 208  */
 209
 210 /*!
 211  * @name Register FB_CSMRn, field V[0] (RW)
 212  *
 213  * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
 214  * Programmed chip-selects do not assert until the V bit is 1b (except for
 215  * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
 216  * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
 217  * select initialization sequence to allow other chip selects to function as
 218  * programmed.
 219  *
 220  * Values:
 221  * - 0 - Chip-select is invalid.
 222  * - 1 - Chip-select is valid.
 223  */
 224 /*@{*/
 225 #define BP_FB_CSMRn_V        (0U)          /*!< Bit position for FB_CSMRn_V. */
 226 #define BM_FB_CSMRn_V        (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */
 227 #define BS_FB_CSMRn_V        (1U)          /*!< Bit field size in bits for FB_CSMRn_V. */
 228
 229 /*! @brief Read current value of the FB_CSMRn_V field. */
 230 #define BR_FB_CSMRn_V(x, n)  (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V))
 231
 232 /*! @brief Format value for bitfield FB_CSMRn_V. */
 233 #define BF_FB_CSMRn_V(v)     ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V)
 234
 235 /*! @brief Set the V field to a new value. */
 236 #define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v))
 237 /*@}*/
 238
 239 /*!
 240  * @name Register FB_CSMRn, field WP[8] (RW)
 241  *
 242  * Controls write accesses to the address range in the corresponding CSAR.
 243  *
 244  * Values:
 245  * - 0 - Write accesses are allowed.
 246  * - 1 - Write accesses are not allowed. Attempting to write to the range of
 247  *     addresses for which the WP bit is set results in a bus error termination of
 248  *     the internal cycle and no external cycle.
 249  */
 250 /*@{*/
 251 #define BP_FB_CSMRn_WP       (8U)          /*!< Bit position for FB_CSMRn_WP. */
 252 #define BM_FB_CSMRn_WP       (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */
 253 #define BS_FB_CSMRn_WP       (1U)          /*!< Bit field size in bits for FB_CSMRn_WP. */
 254
 255 /*! @brief Read current value of the FB_CSMRn_WP field. */
 256 #define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP))
 257
 258 /*! @brief Format value for bitfield FB_CSMRn_WP. */
 259 #define BF_FB_CSMRn_WP(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP)
 260
 261 /*! @brief Set the WP field to a new value. */
 262 #define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v))
 263 /*@}*/
 264
 265 /*!
 266  * @name Register FB_CSMRn, field BAM[31:16] (RW)
 267  *
 268  * Defines the associated chip-select's block size by masking address bits.
 269  *
 270  * Values:
 271  * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
 272  * - 1 - The corresponding address bit in CSAR is a don't care in the
 273  *     chip-select decode.
 274  */
 275 /*@{*/
 276 #define BP_FB_CSMRn_BAM      (16U)         /*!< Bit position for FB_CSMRn_BAM. */
 277 #define BM_FB_CSMRn_BAM      (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */
 278 #define BS_FB_CSMRn_BAM      (16U)         /*!< Bit field size in bits for FB_CSMRn_BAM. */
 279
 280 /*! @brief Read current value of the FB_CSMRn_BAM field. */
 281 #define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM)
 282
 283 /*! @brief Format value for bitfield FB_CSMRn_BAM. */
 284 #define BF_FB_CSMRn_BAM(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM)
 285
 286 /*! @brief Set the BAM field to a new value. */
 287 #define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
 288 /*@}*/
 289 /*******************************************************************************
 290  * HW_FB_CSCRn - Chip Select Control Register
 291  ******************************************************************************/
 292
 293 /*!
 294  * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
 295  *
 296  * Reset value: 0x003FFC00U
 297  *
 298  * Controls the auto-acknowledge, address setup and hold times, port size, burst
 299  * capability, and number of wait states for the associated chip select. To
 300  * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
 301  * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
 302  * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
 303  * particular chip for information on the exact CSCR0 reset value.
 304  */
 305 typedef union _hw_fb_cscrn
 306 {
 307     uint32_t U;
 308     struct _hw_fb_cscrn_bitfields
 309     {
 310         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
 311         uint32_t BSTW : 1;             /*!< [3] Burst-Write Enable */
 312         uint32_t BSTR : 1;             /*!< [4] Burst-Read Enable */
 313         uint32_t BEM : 1;              /*!< [5] Byte-Enable Mode */
 314         uint32_t PS : 2;               /*!< [7:6] Port Size */
 315         uint32_t AA : 1;               /*!< [8] Auto-Acknowledge Enable */
 316         uint32_t BLS : 1;              /*!< [9] Byte-Lane Shift */
 317         uint32_t WS : 6;               /*!< [15:10] Wait States */
 318         uint32_t WRAH : 2;             /*!< [17:16] Write Address Hold or Deselect */
 319         uint32_t RDAH : 2;             /*!< [19:18] Read Address Hold or Deselect */
 320         uint32_t ASET : 2;             /*!< [21:20] Address Setup */
 321         uint32_t EXTS : 1;             /*!< [22]  */
 322         uint32_t SWSEN : 1;            /*!< [23] Secondary Wait State Enable */
 323         uint32_t RESERVED1 : 2;        /*!< [25:24]  */
 324         uint32_t SWS : 6;              /*!< [31:26] Secondary Wait States */
 325     } B;
 326 } hw_fb_cscrn_t;
 327
 328 /*!
 329  * @name Constants and macros for entire FB_CSCRn register
 330  */
 331 /*@{*/
 332 #define HW_FB_CSCRn_COUNT (6U)
 333
 334 #define HW_FB_CSCRn_ADDR(x, n)   ((x) + 0x8U + (0xCU * (n)))
 335
 336 #define HW_FB_CSCRn(x, n)        (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n))
 337 #define HW_FB_CSCRn_RD(x, n)     (HW_FB_CSCRn(x, n).U)
 338 #define HW_FB_CSCRn_WR(x, n, v)  (HW_FB_CSCRn(x, n).U = (v))
 339 #define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) |  (v)))
 340 #define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v)))
 341 #define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^  (v)))
 342 /*@}*/
 343
 344 /*
 345  * Constants & macros for individual FB_CSCRn bitfields
 346  */
 347
 348 /*!
 349  * @name Register FB_CSCRn, field BSTW[3] (RW)
 350  *
 351  * Specifies whether burst writes are enabled for memory associated with each
 352  * chip select.
 353  *
 354  * Values:
 355  * - 0 - Disabled. Data exceeding the specified port size is broken into
 356  *     individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
 357  *     port takes four byte writes.
 358  * - 1 - Enabled. Enables burst write of data larger than the specified port
 359  *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
 360  *     ports, and line writes to 8-, 16-, and 32-bit ports.
 361  */
 362 /*@{*/
 363 #define BP_FB_CSCRn_BSTW     (3U)          /*!< Bit position for FB_CSCRn_BSTW. */
 364 #define BM_FB_CSCRn_BSTW     (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */
 365 #define BS_FB_CSCRn_BSTW     (1U)          /*!< Bit field size in bits for FB_CSCRn_BSTW. */
 366
 367 /*! @brief Read current value of the FB_CSCRn_BSTW field. */
 368 #define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW))
 369
 370 /*! @brief Format value for bitfield FB_CSCRn_BSTW. */
 371 #define BF_FB_CSCRn_BSTW(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW)
 372
 373 /*! @brief Set the BSTW field to a new value. */
 374 #define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v))
 375 /*@}*/
 376
 377 /*!
 378  * @name Register FB_CSCRn, field BSTR[4] (RW)
 379  *
 380  * Specifies whether burst reads are enabled for memory associated with each
 381  * chip select.
 382  *
 383  * Values:
 384  * - 0 - Disabled. Data exceeding the specified port size is broken into
 385  *     individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
 386  *     port is broken into four 8-bit reads.
 387  * - 1 - Enabled. Enables data burst reads larger than the specified port size,
 388  *     including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
 389  *     ports, and line reads from 8-, 16-, and 32-bit ports.
 390  */
 391 /*@{*/
 392 #define BP_FB_CSCRn_BSTR     (4U)          /*!< Bit position for FB_CSCRn_BSTR. */
 393 #define BM_FB_CSCRn_BSTR     (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */
 394 #define BS_FB_CSCRn_BSTR     (1U)          /*!< Bit field size in bits for FB_CSCRn_BSTR. */
 395
 396 /*! @brief Read current value of the FB_CSCRn_BSTR field. */
 397 #define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR))
 398
 399 /*! @brief Format value for bitfield FB_CSCRn_BSTR. */
 400 #define BF_FB_CSCRn_BSTR(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR)
 401
 402 /*! @brief Set the BSTR field to a new value. */
 403 #define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v))
 404 /*@}*/
 405
 406 /*!
 407  * @name Register FB_CSCRn, field BEM[5] (RW)
 408  *
 409  * Specifies whether the corresponding FB_BE is asserted for read accesses.
 410  * Certain memories have byte enables that must be asserted during reads and writes.
 411  * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
 412  * of byte enable support for these SRAMs.
 413  *
 414  * Values:
 415  * - 0 - FB_BE is asserted for data write only.
 416  * - 1 - FB_BE is asserted for data read and write accesses.
 417  */
 418 /*@{*/
 419 #define BP_FB_CSCRn_BEM      (5U)          /*!< Bit position for FB_CSCRn_BEM. */
 420 #define BM_FB_CSCRn_BEM      (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */
 421 #define BS_FB_CSCRn_BEM      (1U)          /*!< Bit field size in bits for FB_CSCRn_BEM. */
 422
 423 /*! @brief Read current value of the FB_CSCRn_BEM field. */
 424 #define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM))
 425
 426 /*! @brief Format value for bitfield FB_CSCRn_BEM. */
 427 #define BF_FB_CSCRn_BEM(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM)
 428
 429 /*! @brief Set the BEM field to a new value. */
 430 #define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v))
 431 /*@}*/
 432
 433 /*!
 434  * @name Register FB_CSCRn, field PS[7:6] (RW)
 435  *
 436  * Specifies the data port width of the associated chip-select, and determines
 437  * where data is driven during write cycles and where data is sampled during read
 438  * cycles.
 439  *
 440  * Values:
 441  * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
 442  * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
 443  *     BLS is 0b, or FB_D[7:0] when BLS is 1b.
 444  */
 445 /*@{*/
 446 #define BP_FB_CSCRn_PS       (6U)          /*!< Bit position for FB_CSCRn_PS. */
 447 #define BM_FB_CSCRn_PS       (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */
 448 #define BS_FB_CSCRn_PS       (2U)          /*!< Bit field size in bits for FB_CSCRn_PS. */
 449
 450 /*! @brief Read current value of the FB_CSCRn_PS field. */
 451 #define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS)
 452
 453 /*! @brief Format value for bitfield FB_CSCRn_PS. */
 454 #define BF_FB_CSCRn_PS(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS)
 455
 456 /*! @brief Set the PS field to a new value. */
 457 #define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
 458 /*@}*/
 459
 460 /*!
 461  * @name Register FB_CSCRn, field AA[8] (RW)
 462  *
 463  * Asserts the internal transfer acknowledge for accesses specified by the
 464  * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
 465  * asserts an external FB_TA before the wait-state countdown asserts the
 466  * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
 467  * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
 468  *
 469  * Values:
 470  * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
 471  *     terminated externally.
 472  * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
 473  */
 474 /*@{*/
 475 #define BP_FB_CSCRn_AA       (8U)          /*!< Bit position for FB_CSCRn_AA. */
 476 #define BM_FB_CSCRn_AA       (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */
 477 #define BS_FB_CSCRn_AA       (1U)          /*!< Bit field size in bits for FB_CSCRn_AA. */
 478
 479 /*! @brief Read current value of the FB_CSCRn_AA field. */
 480 #define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA))
 481
 482 /*! @brief Format value for bitfield FB_CSCRn_AA. */
 483 #define BF_FB_CSCRn_AA(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA)
 484
 485 /*! @brief Set the AA field to a new value. */
 486 #define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v))
 487 /*@}*/
 488
 489 /*!
 490  * @name Register FB_CSCRn, field BLS[9] (RW)
 491  *
 492  * Specifies if data on FB_AD appears left-aligned or right-aligned during the
 493  * data phase of a FlexBus access.
 494  *
 495  * Values:
 496  * - 0 - Not shifted. Data is left-aligned on FB_AD.
 497  * - 1 - Shifted. Data is right-aligned on FB_AD.
 498  */
 499 /*@{*/
 500 #define BP_FB_CSCRn_BLS      (9U)          /*!< Bit position for FB_CSCRn_BLS. */
 501 #define BM_FB_CSCRn_BLS      (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */
 502 #define BS_FB_CSCRn_BLS      (1U)          /*!< Bit field size in bits for FB_CSCRn_BLS. */
 503
 504 /*! @brief Read current value of the FB_CSCRn_BLS field. */
 505 #define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS))
 506
 507 /*! @brief Format value for bitfield FB_CSCRn_BLS. */
 508 #define BF_FB_CSCRn_BLS(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS)
 509
 510 /*! @brief Set the BLS field to a new value. */
 511 #define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v))
 512 /*@}*/
 513
 514 /*!
 515  * @name Register FB_CSCRn, field WS[15:10] (RW)
 516  *
 517  * Specifies the number of wait states inserted after FlexBus asserts the
 518  * associated chip-select and before an internal transfer acknowledge is generated (WS
 519  * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
 520  */
 521 /*@{*/
 522 #define BP_FB_CSCRn_WS       (10U)         /*!< Bit position for FB_CSCRn_WS. */
 523 #define BM_FB_CSCRn_WS       (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */
 524 #define BS_FB_CSCRn_WS       (6U)          /*!< Bit field size in bits for FB_CSCRn_WS. */
 525
 526 /*! @brief Read current value of the FB_CSCRn_WS field. */
 527 #define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS)
 528
 529 /*! @brief Format value for bitfield FB_CSCRn_WS. */
 530 #define BF_FB_CSCRn_WS(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS)
 531
 532 /*! @brief Set the WS field to a new value. */
 533 #define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
 534 /*@}*/
 535
 536 /*!
 537  * @name Register FB_CSCRn, field WRAH[17:16] (RW)
 538  *
 539  * Controls the address, data, and attribute hold time after the termination of
 540  * a write cycle that hits in the associated chip-select's address space. The
 541  * hold time applies only at the end of a transfer. Therefore, during a burst
 542  * transfer or a transfer to a port size smaller than the transfer size, the hold time
 543  * is only added after the last bus cycle.
 544  *
 545  * Values:
 546  * - 00 - 1 cycle (default for all but FB_CS0 )
 547  * - 01 - 2 cycles
 548  * - 10 - 3 cycles
 549  * - 11 - 4 cycles (default for FB_CS0 )
 550  */
 551 /*@{*/
 552 #define BP_FB_CSCRn_WRAH     (16U)         /*!< Bit position for FB_CSCRn_WRAH. */
 553 #define BM_FB_CSCRn_WRAH     (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */
 554 #define BS_FB_CSCRn_WRAH     (2U)          /*!< Bit field size in bits for FB_CSCRn_WRAH. */
 555
 556 /*! @brief Read current value of the FB_CSCRn_WRAH field. */
 557 #define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH)
 558
 559 /*! @brief Format value for bitfield FB_CSCRn_WRAH. */
 560 #define BF_FB_CSCRn_WRAH(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH)
 561
 562 /*! @brief Set the WRAH field to a new value. */
 563 #define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
 564 /*@}*/
 565
 566 /*!
 567  * @name Register FB_CSCRn, field RDAH[19:18] (RW)
 568  *
 569  * Controls the address and attribute hold time after the termination during a
 570  * read cycle that hits in the associated chip-select's address space. The hold
 571  * time applies only at the end of a transfer. Therefore, during a burst transfer
 572  * or a transfer to a port size smaller than the transfer size, the hold time is
 573  * only added after the last bus cycle. The number of cycles the address and
 574  * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
 575  *
 576  * Values:
 577  * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
 578  * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
 579  * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
 580  * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
 581  */
 582 /*@{*/
 583 #define BP_FB_CSCRn_RDAH     (18U)         /*!< Bit position for FB_CSCRn_RDAH. */
 584 #define BM_FB_CSCRn_RDAH     (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */
 585 #define BS_FB_CSCRn_RDAH     (2U)          /*!< Bit field size in bits for FB_CSCRn_RDAH. */
 586
 587 /*! @brief Read current value of the FB_CSCRn_RDAH field. */
 588 #define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH)
 589
 590 /*! @brief Format value for bitfield FB_CSCRn_RDAH. */
 591 #define BF_FB_CSCRn_RDAH(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH)
 592
 593 /*! @brief Set the RDAH field to a new value. */
 594 #define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
 595 /*@}*/
 596
 597 /*!
 598  * @name Register FB_CSCRn, field ASET[21:20] (RW)
 599  *
 600  * Controls when the chip-select is asserted with respect to assertion of a
 601  * valid address and attributes.
 602  *
 603  * Values:
 604  * - 00 - Assert FB_CSn on the first rising clock edge after the address is
 605  *     asserted (default for all but FB_CS0 ).
 606  * - 01 - Assert FB_CSn on the second rising clock edge after the address is
 607  *     asserted.
 608  * - 10 - Assert FB_CSn on the third rising clock edge after the address is
 609  *     asserted.
 610  * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
 611  *     asserted (default for FB_CS0 ).
 612  */
 613 /*@{*/
 614 #define BP_FB_CSCRn_ASET     (20U)         /*!< Bit position for FB_CSCRn_ASET. */
 615 #define BM_FB_CSCRn_ASET     (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */
 616 #define BS_FB_CSCRn_ASET     (2U)          /*!< Bit field size in bits for FB_CSCRn_ASET. */
 617
 618 /*! @brief Read current value of the FB_CSCRn_ASET field. */
 619 #define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET)
 620
 621 /*! @brief Format value for bitfield FB_CSCRn_ASET. */
 622 #define BF_FB_CSCRn_ASET(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET)
 623
 624 /*! @brief Set the ASET field to a new value. */
 625 #define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
 626 /*@}*/
 627
 628 /*!
 629  * @name Register FB_CSCRn, field EXTS[22] (RW)
 630  *
 631  * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
 632  * /FB_ALE is asserted.
 633  *
 634  * Values:
 635  * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
 636  * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
 637  *     edge after FB_CSn asserts.
 638  */
 639 /*@{*/
 640 #define BP_FB_CSCRn_EXTS     (22U)         /*!< Bit position for FB_CSCRn_EXTS. */
 641 #define BM_FB_CSCRn_EXTS     (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */
 642 #define BS_FB_CSCRn_EXTS     (1U)          /*!< Bit field size in bits for FB_CSCRn_EXTS. */
 643
 644 /*! @brief Read current value of the FB_CSCRn_EXTS field. */
 645 #define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS))
 646
 647 /*! @brief Format value for bitfield FB_CSCRn_EXTS. */
 648 #define BF_FB_CSCRn_EXTS(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS)
 649
 650 /*! @brief Set the EXTS field to a new value. */
 651 #define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v))
 652 /*@}*/
 653
 654 /*!
 655  * @name Register FB_CSCRn, field SWSEN[23] (RW)
 656  *
 657  * Values:
 658  * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
 659  *     an internal transfer acknowledge is generated for all transfers.
 660  * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
 661  *     an internal transfer acknowledge is generated for burst transfer
 662  *     secondary terminations.
 663  */
 664 /*@{*/
 665 #define BP_FB_CSCRn_SWSEN    (23U)         /*!< Bit position for FB_CSCRn_SWSEN. */
 666 #define BM_FB_CSCRn_SWSEN    (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */
 667 #define BS_FB_CSCRn_SWSEN    (1U)          /*!< Bit field size in bits for FB_CSCRn_SWSEN. */
 668
 669 /*! @brief Read current value of the FB_CSCRn_SWSEN field. */
 670 #define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN))
 671
 672 /*! @brief Format value for bitfield FB_CSCRn_SWSEN. */
 673 #define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN)
 674
 675 /*! @brief Set the SWSEN field to a new value. */
 676 #define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v))
 677 /*@}*/
 678
 679 /*!
 680  * @name Register FB_CSCRn, field SWS[31:26] (RW)
 681  *
 682  * Used only when the SWSEN bit is 1b. Specifies the number of wait states
 683  * inserted before an internal transfer acknowledge is generated for a burst transfer
 684  * (except for the first termination, which is controlled by WS).
 685  */
 686 /*@{*/
 687 #define BP_FB_CSCRn_SWS      (26U)         /*!< Bit position for FB_CSCRn_SWS. */
 688 #define BM_FB_CSCRn_SWS      (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */
 689 #define BS_FB_CSCRn_SWS      (6U)          /*!< Bit field size in bits for FB_CSCRn_SWS. */
 690
 691 /*! @brief Read current value of the FB_CSCRn_SWS field. */
 692 #define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS)
 693
 694 /*! @brief Format value for bitfield FB_CSCRn_SWS. */
 695 #define BF_FB_CSCRn_SWS(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS)
 696
 697 /*! @brief Set the SWS field to a new value. */
 698 #define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
 699 /*@}*/
 700
 701 /*******************************************************************************
 702  * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
 703  ******************************************************************************/
 704
 705 /*!
 706  * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
 707  *
 708  * Reset value: 0x00000000U
 709  *
 710  * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
 711  * do any of the following: Write to a reserved address Write to a reserved
 712  * field in this register, or Access this register using a size other than 32 bits.
 713  */
 714 typedef union _hw_fb_cspmcr
 715 {
 716     uint32_t U;
 717     struct _hw_fb_cspmcr_bitfields
 718     {
 719         uint32_t RESERVED0 : 12;       /*!< [11:0]  */
 720         uint32_t GROUP5 : 4;           /*!< [15:12] FlexBus Signal Group 5 Multiplex
 721                                         * control */
 722         uint32_t GROUP4 : 4;           /*!< [19:16] FlexBus Signal Group 4 Multiplex
 723                                         * control */
 724         uint32_t GROUP3 : 4;           /*!< [23:20] FlexBus Signal Group 3 Multiplex
 725                                         * control */
 726         uint32_t GROUP2 : 4;           /*!< [27:24] FlexBus Signal Group 2 Multiplex
 727                                         * control */
 728         uint32_t GROUP1 : 4;           /*!< [31:28] FlexBus Signal Group 1 Multiplex
 729                                         * control */
 730     } B;
 731 } hw_fb_cspmcr_t;
 732
 733 /*!
 734  * @name Constants and macros for entire FB_CSPMCR register
 735  */
 736 /*@{*/
 737 #define HW_FB_CSPMCR_ADDR(x)     ((x) + 0x60U)
 738
 739 #define HW_FB_CSPMCR(x)          (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x))
 740 #define HW_FB_CSPMCR_RD(x)       (HW_FB_CSPMCR(x).U)
 741 #define HW_FB_CSPMCR_WR(x, v)    (HW_FB_CSPMCR(x).U = (v))
 742 #define HW_FB_CSPMCR_SET(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) |  (v)))
 743 #define HW_FB_CSPMCR_CLR(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v)))
 744 #define HW_FB_CSPMCR_TOG(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^  (v)))
 745 /*@}*/
 746
 747 /*
 748  * Constants & macros for individual FB_CSPMCR bitfields
 749  */
 750
 751 /*!
 752  * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
 753  *
 754  * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
 755  * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
 756  * bus hangs during a transfer.
 757  *
 758  * Values:
 759  * - 0000 - FB_TA
 760  * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
 761  * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
 762  */
 763 /*@{*/
 764 #define BP_FB_CSPMCR_GROUP5  (12U)         /*!< Bit position for FB_CSPMCR_GROUP5. */
 765 #define BM_FB_CSPMCR_GROUP5  (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */
 766 #define BS_FB_CSPMCR_GROUP5  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */
 767
 768 /*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
 769 #define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5)
 770
 771 /*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */
 772 #define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5)
 773
 774 /*! @brief Set the GROUP5 field to a new value. */
 775 #define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
 776 /*@}*/
 777
 778 /*!
 779  * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
 780  *
 781  * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
 782  *
 783  * Values:
 784  * - 0000 - FB_TBST
 785  * - 0001 - FB_CS2
 786  * - 0010 - FB_BE_15_8
 787  */
 788 /*@{*/
 789 #define BP_FB_CSPMCR_GROUP4  (16U)         /*!< Bit position for FB_CSPMCR_GROUP4. */
 790 #define BM_FB_CSPMCR_GROUP4  (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */
 791 #define BS_FB_CSPMCR_GROUP4  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */
 792
 793 /*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
 794 #define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4)
 795
 796 /*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */
 797 #define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4)
 798
 799 /*! @brief Set the GROUP4 field to a new value. */
 800 #define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
 801 /*@}*/
 802
 803 /*!
 804  * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
 805  *
 806  * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
 807  *
 808  * Values:
 809  * - 0000 - FB_CS5
 810  * - 0001 - FB_TSIZ1
 811  * - 0010 - FB_BE_23_16
 812  */
 813 /*@{*/
 814 #define BP_FB_CSPMCR_GROUP3  (20U)         /*!< Bit position for FB_CSPMCR_GROUP3. */
 815 #define BM_FB_CSPMCR_GROUP3  (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */
 816 #define BS_FB_CSPMCR_GROUP3  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */
 817
 818 /*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
 819 #define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3)
 820
 821 /*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */
 822 #define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3)
 823
 824 /*! @brief Set the GROUP3 field to a new value. */
 825 #define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
 826 /*@}*/
 827
 828 /*!
 829  * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
 830  *
 831  * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
 832  *
 833  * Values:
 834  * - 0000 - FB_CS4
 835  * - 0001 - FB_TSIZ0
 836  * - 0010 - FB_BE_31_24
 837  */
 838 /*@{*/
 839 #define BP_FB_CSPMCR_GROUP2  (24U)         /*!< Bit position for FB_CSPMCR_GROUP2. */
 840 #define BM_FB_CSPMCR_GROUP2  (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */
 841 #define BS_FB_CSPMCR_GROUP2  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */
 842
 843 /*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
 844 #define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2)
 845
 846 /*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */
 847 #define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2)
 848
 849 /*! @brief Set the GROUP2 field to a new value. */
 850 #define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
 851 /*@}*/
 852
 853 /*!
 854  * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
 855  *
 856  * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
 857  *
 858  * Values:
 859  * - 0000 - FB_ALE
 860  * - 0001 - FB_CS1
 861  * - 0010 - FB_TS
 862  */
 863 /*@{*/
 864 #define BP_FB_CSPMCR_GROUP1  (28U)         /*!< Bit position for FB_CSPMCR_GROUP1. */
 865 #define BM_FB_CSPMCR_GROUP1  (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */
 866 #define BS_FB_CSPMCR_GROUP1  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */
 867
 868 /*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
 869 #define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1)
 870
 871 /*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */
 872 #define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1)
 873
 874 /*! @brief Set the GROUP1 field to a new value. */
 875 #define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
 876 /*@}*/
 877
 878 /*******************************************************************************
 879  * hw_fb_t - module struct
 880  ******************************************************************************/
 881 /*!
 882  * @brief All FB module registers.
 883  */
 884 #pragma pack(1)
 885 typedef struct _hw_fb
 886 {
 887     struct {
 888         __IO hw_fb_csarn_t CSARn;          /*!< [0x0] Chip Select Address Register */
 889         __IO hw_fb_csmrn_t CSMRn;          /*!< [0x4] Chip Select Mask Register */
 890         __IO hw_fb_cscrn_t CSCRn;          /*!< [0x8] Chip Select Control Register */
 891     } CS[6];
 892     uint8_t _reserved0[24];
 893     __IO hw_fb_cspmcr_t CSPMCR;            /*!< [0x60] Chip Select port Multiplexing Control Register */
 894 } hw_fb_t;
 895 #pragma pack()
 896
 897 /*! @brief Macro to access all FB registers. */
 898 /*! @param x FB module instance base address. */
 899 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 900  *     use the '&' operator, like <code>&HW_FB(FB_BASE)</code>. */
 901 #define HW_FB(x)       (*(hw_fb_t *)(x))
 902
 903 #endif /* __HW_FB_REGISTERS_H__ */
 904 /* EOF */