tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_PORT_REGISTERS_H__
  78 #define __HW_PORT_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 PORT
  85  *
  86  * Pin Control and Interrupts
  87  *
  88  * Registers defined in this header file:
  89  * - HW_PORT_PCRn - Pin Control Register n
  90  * - HW_PORT_GPCLR - Global Pin Control Low Register
  91  * - HW_PORT_GPCHR - Global Pin Control High Register
  92  * - HW_PORT_ISFR - Interrupt Status Flag Register
  93  * - HW_PORT_DFER - Digital Filter Enable Register
  94  * - HW_PORT_DFCR - Digital Filter Clock Register
  95  * - HW_PORT_DFWR - Digital Filter Width Register
  96  *
  97  * - hw_port_t - Struct containing all module registers.
  98  */
  99
 100 #define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
 101 #define HW_PORTA (0U) /*!< Instance number for PORTA. */
 102 #define HW_PORTB (1U) /*!< Instance number for PORTB. */
 103 #define HW_PORTC (2U) /*!< Instance number for PORTC. */
 104 #define HW_PORTD (3U) /*!< Instance number for PORTD. */
 105 #define HW_PORTE (4U) /*!< Instance number for PORTE. */
 106
 107 /*******************************************************************************
 108  * HW_PORT_PCRn - Pin Control Register n
 109  ******************************************************************************/
 110
 111 /*!
 112  * @brief HW_PORT_PCRn - Pin Control Register n (RW)
 113  *
 114  * Reset value: 0x00000700U
 115  *
 116  * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
 117  * this device. See the GPIO Configuration section for details on the available
 118  * functions for each pin. Do not modify pin configuration registers associated
 119  * with pins not available in your selected package. All unbonded pins not
 120  * available in your package will default to DISABLE state for lowest power consumption.
 121  */
 122 typedef union _hw_port_pcrn
 123 {
 124     uint32_t U;
 125     struct _hw_port_pcrn_bitfields
 126     {
 127         uint32_t PS : 1;               /*!< [0] Pull Select */
 128         uint32_t PE : 1;               /*!< [1] Pull Enable */
 129         uint32_t SRE : 1;              /*!< [2] Slew Rate Enable */
 130         uint32_t RESERVED0 : 1;        /*!< [3]  */
 131         uint32_t PFE : 1;              /*!< [4] Passive Filter Enable */
 132         uint32_t ODE : 1;              /*!< [5] Open Drain Enable */
 133         uint32_t DSE : 1;              /*!< [6] Drive Strength Enable */
 134         uint32_t RESERVED1 : 1;        /*!< [7]  */
 135         uint32_t MUX : 3;              /*!< [10:8] Pin Mux Control */
 136         uint32_t RESERVED2 : 4;        /*!< [14:11]  */
 137         uint32_t LK : 1;               /*!< [15] Lock Register */
 138         uint32_t IRQC : 4;             /*!< [19:16] Interrupt Configuration */
 139         uint32_t RESERVED3 : 4;        /*!< [23:20]  */
 140         uint32_t ISF : 1;              /*!< [24] Interrupt Status Flag */
 141         uint32_t RESERVED4 : 7;        /*!< [31:25]  */
 142     } B;
 143 } hw_port_pcrn_t;
 144
 145 /*!
 146  * @name Constants and macros for entire PORT_PCRn register
 147  */
 148 /*@{*/
 149 #define HW_PORT_PCRn_COUNT (32U)
 150
 151 #define HW_PORT_PCRn_ADDR(x, n)  ((x) + 0x0U + (0x4U * (n)))
 152
 153 #define HW_PORT_PCRn(x, n)       (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
 154 #define HW_PORT_PCRn_RD(x, n)    (HW_PORT_PCRn(x, n).U)
 155 #define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
 156 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) |  (v)))
 157 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
 158 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^  (v)))
 159 /*@}*/
 160
 161 /*
 162  * Constants & macros for individual PORT_PCRn bitfields
 163  */
 164
 165 /*!
 166  * @name Register PORT_PCRn, field PS[0] (RW)
 167  *
 168  * Pull configuration is valid in all digital pin muxing modes.
 169  *
 170  * Values:
 171  * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
 172  *     corresponding PE field is set.
 173  * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
 174  *     corresponding PE field is set.
 175  */
 176 /*@{*/
 177 #define BP_PORT_PCRn_PS      (0U)          /*!< Bit position for PORT_PCRn_PS. */
 178 #define BM_PORT_PCRn_PS      (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
 179 #define BS_PORT_PCRn_PS      (1U)          /*!< Bit field size in bits for PORT_PCRn_PS. */
 180
 181 /*! @brief Read current value of the PORT_PCRn_PS field. */
 182 #define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
 183
 184 /*! @brief Format value for bitfield PORT_PCRn_PS. */
 185 #define BF_PORT_PCRn_PS(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
 186
 187 /*! @brief Set the PS field to a new value. */
 188 #define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
 189 /*@}*/
 190
 191 /*!
 192  * @name Register PORT_PCRn, field PE[1] (RW)
 193  *
 194  * Pull configuration is valid in all digital pin muxing modes.
 195  *
 196  * Values:
 197  * - 0 - Internal pullup or pulldown resistor is not enabled on the
 198  *     corresponding pin.
 199  * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
 200  *     pin, if the pin is configured as a digital input.
 201  */
 202 /*@{*/
 203 #define BP_PORT_PCRn_PE      (1U)          /*!< Bit position for PORT_PCRn_PE. */
 204 #define BM_PORT_PCRn_PE      (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
 205 #define BS_PORT_PCRn_PE      (1U)          /*!< Bit field size in bits for PORT_PCRn_PE. */
 206
 207 /*! @brief Read current value of the PORT_PCRn_PE field. */
 208 #define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
 209
 210 /*! @brief Format value for bitfield PORT_PCRn_PE. */
 211 #define BF_PORT_PCRn_PE(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
 212
 213 /*! @brief Set the PE field to a new value. */
 214 #define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
 215 /*@}*/
 216
 217 /*!
 218  * @name Register PORT_PCRn, field SRE[2] (RW)
 219  *
 220  * Slew rate configuration is valid in all digital pin muxing modes.
 221  *
 222  * Values:
 223  * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
 224  *     configured as a digital output.
 225  * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
 226  *     configured as a digital output.
 227  */
 228 /*@{*/
 229 #define BP_PORT_PCRn_SRE     (2U)          /*!< Bit position for PORT_PCRn_SRE. */
 230 #define BM_PORT_PCRn_SRE     (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
 231 #define BS_PORT_PCRn_SRE     (1U)          /*!< Bit field size in bits for PORT_PCRn_SRE. */
 232
 233 /*! @brief Read current value of the PORT_PCRn_SRE field. */
 234 #define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
 235
 236 /*! @brief Format value for bitfield PORT_PCRn_SRE. */
 237 #define BF_PORT_PCRn_SRE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
 238
 239 /*! @brief Set the SRE field to a new value. */
 240 #define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
 241 /*@}*/
 242
 243 /*!
 244  * @name Register PORT_PCRn, field PFE[4] (RW)
 245  *
 246  * Passive filter configuration is valid in all digital pin muxing modes.
 247  *
 248  * Values:
 249  * - 0 - Passive input filter is disabled on the corresponding pin.
 250  * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
 251  *     configured as a digital input. Refer to the device data sheet for filter
 252  *     characteristics.
 253  */
 254 /*@{*/
 255 #define BP_PORT_PCRn_PFE     (4U)          /*!< Bit position for PORT_PCRn_PFE. */
 256 #define BM_PORT_PCRn_PFE     (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
 257 #define BS_PORT_PCRn_PFE     (1U)          /*!< Bit field size in bits for PORT_PCRn_PFE. */
 258
 259 /*! @brief Read current value of the PORT_PCRn_PFE field. */
 260 #define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
 261
 262 /*! @brief Format value for bitfield PORT_PCRn_PFE. */
 263 #define BF_PORT_PCRn_PFE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
 264
 265 /*! @brief Set the PFE field to a new value. */
 266 #define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
 267 /*@}*/
 268
 269 /*!
 270  * @name Register PORT_PCRn, field ODE[5] (RW)
 271  *
 272  * Open drain configuration is valid in all digital pin muxing modes.
 273  *
 274  * Values:
 275  * - 0 - Open drain output is disabled on the corresponding pin.
 276  * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
 277  *     configured as a digital output.
 278  */
 279 /*@{*/
 280 #define BP_PORT_PCRn_ODE     (5U)          /*!< Bit position for PORT_PCRn_ODE. */
 281 #define BM_PORT_PCRn_ODE     (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
 282 #define BS_PORT_PCRn_ODE     (1U)          /*!< Bit field size in bits for PORT_PCRn_ODE. */
 283
 284 /*! @brief Read current value of the PORT_PCRn_ODE field. */
 285 #define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
 286
 287 /*! @brief Format value for bitfield PORT_PCRn_ODE. */
 288 #define BF_PORT_PCRn_ODE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
 289
 290 /*! @brief Set the ODE field to a new value. */
 291 #define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
 292 /*@}*/
 293
 294 /*!
 295  * @name Register PORT_PCRn, field DSE[6] (RW)
 296  *
 297  * Drive strength configuration is valid in all digital pin muxing modes.
 298  *
 299  * Values:
 300  * - 0 - Low drive strength is configured on the corresponding pin, if pin is
 301  *     configured as a digital output.
 302  * - 1 - High drive strength is configured on the corresponding pin, if pin is
 303  *     configured as a digital output.
 304  */
 305 /*@{*/
 306 #define BP_PORT_PCRn_DSE     (6U)          /*!< Bit position for PORT_PCRn_DSE. */
 307 #define BM_PORT_PCRn_DSE     (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
 308 #define BS_PORT_PCRn_DSE     (1U)          /*!< Bit field size in bits for PORT_PCRn_DSE. */
 309
 310 /*! @brief Read current value of the PORT_PCRn_DSE field. */
 311 #define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
 312
 313 /*! @brief Format value for bitfield PORT_PCRn_DSE. */
 314 #define BF_PORT_PCRn_DSE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
 315
 316 /*! @brief Set the DSE field to a new value. */
 317 #define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
 318 /*@}*/
 319
 320 /*!
 321  * @name Register PORT_PCRn, field MUX[10:8] (RW)
 322  *
 323  * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
 324  * reserved and may result in configuring the pin for a different pin muxing
 325  * slot. The corresponding pin is configured in the following pin muxing slot as
 326  * follows:
 327  *
 328  * Values:
 329  * - 000 - Pin disabled (analog).
 330  * - 001 - Alternative 1 (GPIO).
 331  * - 010 - Alternative 2 (chip-specific).
 332  * - 011 - Alternative 3 (chip-specific).
 333  * - 100 - Alternative 4 (chip-specific).
 334  * - 101 - Alternative 5 (chip-specific).
 335  * - 110 - Alternative 6 (chip-specific).
 336  * - 111 - Alternative 7 (chip-specific).
 337  */
 338 /*@{*/
 339 #define BP_PORT_PCRn_MUX     (8U)          /*!< Bit position for PORT_PCRn_MUX. */
 340 #define BM_PORT_PCRn_MUX     (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
 341 #define BS_PORT_PCRn_MUX     (3U)          /*!< Bit field size in bits for PORT_PCRn_MUX. */
 342
 343 /*! @brief Read current value of the PORT_PCRn_MUX field. */
 344 #define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
 345
 346 /*! @brief Format value for bitfield PORT_PCRn_MUX. */
 347 #define BF_PORT_PCRn_MUX(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
 348
 349 /*! @brief Set the MUX field to a new value. */
 350 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
 351 /*@}*/
 352
 353 /*!
 354  * @name Register PORT_PCRn, field LK[15] (RW)
 355  *
 356  * Values:
 357  * - 0 - Pin Control Register fields [15:0] are not locked.
 358  * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
 359  *     until the next system reset.
 360  */
 361 /*@{*/
 362 #define BP_PORT_PCRn_LK      (15U)         /*!< Bit position for PORT_PCRn_LK. */
 363 #define BM_PORT_PCRn_LK      (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
 364 #define BS_PORT_PCRn_LK      (1U)          /*!< Bit field size in bits for PORT_PCRn_LK. */
 365
 366 /*! @brief Read current value of the PORT_PCRn_LK field. */
 367 #define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
 368
 369 /*! @brief Format value for bitfield PORT_PCRn_LK. */
 370 #define BF_PORT_PCRn_LK(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
 371
 372 /*! @brief Set the LK field to a new value. */
 373 #define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
 374 /*@}*/
 375
 376 /*!
 377  * @name Register PORT_PCRn, field IRQC[19:16] (RW)
 378  *
 379  * The pin interrupt configuration is valid in all digital pin muxing modes. The
 380  * corresponding pin is configured to generate interrupt/DMA request as follows:
 381  *
 382  * Values:
 383  * - 0000 - Interrupt/DMA request disabled.
 384  * - 0001 - DMA request on rising edge.
 385  * - 0010 - DMA request on falling edge.
 386  * - 0011 - DMA request on either edge.
 387  * - 1000 - Interrupt when logic 0.
 388  * - 1001 - Interrupt on rising-edge.
 389  * - 1010 - Interrupt on falling-edge.
 390  * - 1011 - Interrupt on either edge.
 391  * - 1100 - Interrupt when logic 1.
 392  */
 393 /*@{*/
 394 #define BP_PORT_PCRn_IRQC    (16U)         /*!< Bit position for PORT_PCRn_IRQC. */
 395 #define BM_PORT_PCRn_IRQC    (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
 396 #define BS_PORT_PCRn_IRQC    (4U)          /*!< Bit field size in bits for PORT_PCRn_IRQC. */
 397
 398 /*! @brief Read current value of the PORT_PCRn_IRQC field. */
 399 #define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
 400
 401 /*! @brief Format value for bitfield PORT_PCRn_IRQC. */
 402 #define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
 403
 404 /*! @brief Set the IRQC field to a new value. */
 405 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
 406 /*@}*/
 407
 408 /*!
 409  * @name Register PORT_PCRn, field ISF[24] (W1C)
 410  *
 411  * The pin interrupt configuration is valid in all digital pin muxing modes.
 412  *
 413  * Values:
 414  * - 0 - Configured interrupt is not detected.
 415  * - 1 - Configured interrupt is detected. If the pin is configured to generate
 416  *     a DMA request, then the corresponding flag will be cleared automatically
 417  *     at the completion of the requested DMA transfer. Otherwise, the flag
 418  *     remains set until a logic 1 is written to the flag. If the pin is configured for
 419  *     a level sensitive interrupt and the pin remains asserted, then the flag
 420  *     is set again immediately after it is cleared.
 421  */
 422 /*@{*/
 423 #define BP_PORT_PCRn_ISF     (24U)         /*!< Bit position for PORT_PCRn_ISF. */
 424 #define BM_PORT_PCRn_ISF     (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
 425 #define BS_PORT_PCRn_ISF     (1U)          /*!< Bit field size in bits for PORT_PCRn_ISF. */
 426
 427 /*! @brief Read current value of the PORT_PCRn_ISF field. */
 428 #define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
 429
 430 /*! @brief Format value for bitfield PORT_PCRn_ISF. */
 431 #define BF_PORT_PCRn_ISF(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
 432
 433 /*! @brief Set the ISF field to a new value. */
 434 #define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
 435 /*@}*/
 436
 437 /*******************************************************************************
 438  * HW_PORT_GPCLR - Global Pin Control Low Register
 439  ******************************************************************************/
 440
 441 /*!
 442  * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
 443  *
 444  * Reset value: 0x00000000U
 445  *
 446  * Only 32-bit writes are supported to this register.
 447  */
 448 typedef union _hw_port_gpclr
 449 {
 450     uint32_t U;
 451     struct _hw_port_gpclr_bitfields
 452     {
 453         uint32_t GPWD : 16;            /*!< [15:0] Global Pin Write Data */
 454         uint32_t GPWE : 16;            /*!< [31:16] Global Pin Write Enable */
 455     } B;
 456 } hw_port_gpclr_t;
 457
 458 /*!
 459  * @name Constants and macros for entire PORT_GPCLR register
 460  */
 461 /*@{*/
 462 #define HW_PORT_GPCLR_ADDR(x)    ((x) + 0x80U)
 463
 464 #define HW_PORT_GPCLR(x)         (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
 465 #define HW_PORT_GPCLR_RD(x)      (HW_PORT_GPCLR(x).U)
 466 #define HW_PORT_GPCLR_WR(x, v)   (HW_PORT_GPCLR(x).U = (v))
 467 /*@}*/
 468
 469 /*
 470  * Constants & macros for individual PORT_GPCLR bitfields
 471  */
 472
 473 /*!
 474  * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
 475  *
 476  * Write value that is written to all Pin Control Registers bits [15:0] that are
 477  * selected by GPWE.
 478  */
 479 /*@{*/
 480 #define BP_PORT_GPCLR_GPWD   (0U)          /*!< Bit position for PORT_GPCLR_GPWD. */
 481 #define BM_PORT_GPCLR_GPWD   (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
 482 #define BS_PORT_GPCLR_GPWD   (16U)         /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
 483
 484 /*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
 485 #define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
 486
 487 /*! @brief Set the GPWD field to a new value. */
 488 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
 489 /*@}*/
 490
 491 /*!
 492  * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
 493  *
 494  * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
 495  * the value in GPWD. If a selected Pin Control Register is locked then the write
 496  * to that register is ignored.
 497  *
 498  * Values:
 499  * - 0 - Corresponding Pin Control Register is not updated with the value in
 500  *     GPWD.
 501  * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
 502  */
 503 /*@{*/
 504 #define BP_PORT_GPCLR_GPWE   (16U)         /*!< Bit position for PORT_GPCLR_GPWE. */
 505 #define BM_PORT_GPCLR_GPWE   (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
 506 #define BS_PORT_GPCLR_GPWE   (16U)         /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
 507
 508 /*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
 509 #define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
 510
 511 /*! @brief Set the GPWE field to a new value. */
 512 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
 513 /*@}*/
 514
 515 /*******************************************************************************
 516  * HW_PORT_GPCHR - Global Pin Control High Register
 517  ******************************************************************************/
 518
 519 /*!
 520  * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
 521  *
 522  * Reset value: 0x00000000U
 523  *
 524  * Only 32-bit writes are supported to this register.
 525  */
 526 typedef union _hw_port_gpchr
 527 {
 528     uint32_t U;
 529     struct _hw_port_gpchr_bitfields
 530     {
 531         uint32_t GPWD : 16;            /*!< [15:0] Global Pin Write Data */
 532         uint32_t GPWE : 16;            /*!< [31:16] Global Pin Write Enable */
 533     } B;
 534 } hw_port_gpchr_t;
 535
 536 /*!
 537  * @name Constants and macros for entire PORT_GPCHR register
 538  */
 539 /*@{*/
 540 #define HW_PORT_GPCHR_ADDR(x)    ((x) + 0x84U)
 541
 542 #define HW_PORT_GPCHR(x)         (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
 543 #define HW_PORT_GPCHR_RD(x)      (HW_PORT_GPCHR(x).U)
 544 #define HW_PORT_GPCHR_WR(x, v)   (HW_PORT_GPCHR(x).U = (v))
 545 /*@}*/
 546
 547 /*
 548  * Constants & macros for individual PORT_GPCHR bitfields
 549  */
 550
 551 /*!
 552  * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
 553  *
 554  * Write value that is written to all Pin Control Registers bits [15:0] that are
 555  * selected by GPWE.
 556  */
 557 /*@{*/
 558 #define BP_PORT_GPCHR_GPWD   (0U)          /*!< Bit position for PORT_GPCHR_GPWD. */
 559 #define BM_PORT_GPCHR_GPWD   (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
 560 #define BS_PORT_GPCHR_GPWD   (16U)         /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
 561
 562 /*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
 563 #define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
 564
 565 /*! @brief Set the GPWD field to a new value. */
 566 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
 567 /*@}*/
 568
 569 /*!
 570  * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
 571  *
 572  * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
 573  * the value in GPWD. If a selected Pin Control Register is locked then the write
 574  * to that register is ignored.
 575  *
 576  * Values:
 577  * - 0 - Corresponding Pin Control Register is not updated with the value in
 578  *     GPWD.
 579  * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
 580  */
 581 /*@{*/
 582 #define BP_PORT_GPCHR_GPWE   (16U)         /*!< Bit position for PORT_GPCHR_GPWE. */
 583 #define BM_PORT_GPCHR_GPWE   (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
 584 #define BS_PORT_GPCHR_GPWE   (16U)         /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
 585
 586 /*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
 587 #define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
 588
 589 /*! @brief Set the GPWE field to a new value. */
 590 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
 591 /*@}*/
 592
 593 /*******************************************************************************
 594  * HW_PORT_ISFR - Interrupt Status Flag Register
 595  ******************************************************************************/
 596
 597 /*!
 598  * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
 599  *
 600  * Reset value: 0x00000000U
 601  *
 602  * The pin interrupt configuration is valid in all digital pin muxing modes. The
 603  * Interrupt Status Flag for each pin is also visible in the corresponding Pin
 604  * Control Register, and each flag can be cleared in either location.
 605  */
 606 typedef union _hw_port_isfr
 607 {
 608     uint32_t U;
 609     struct _hw_port_isfr_bitfields
 610     {
 611         uint32_t ISF : 32;             /*!< [31:0] Interrupt Status Flag */
 612     } B;
 613 } hw_port_isfr_t;
 614
 615 /*!
 616  * @name Constants and macros for entire PORT_ISFR register
 617  */
 618 /*@{*/
 619 #define HW_PORT_ISFR_ADDR(x)     ((x) + 0xA0U)
 620
 621 #define HW_PORT_ISFR(x)          (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
 622 #define HW_PORT_ISFR_RD(x)       (HW_PORT_ISFR(x).U)
 623 #define HW_PORT_ISFR_WR(x, v)    (HW_PORT_ISFR(x).U = (v))
 624 #define HW_PORT_ISFR_SET(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) |  (v)))
 625 #define HW_PORT_ISFR_CLR(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
 626 #define HW_PORT_ISFR_TOG(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^  (v)))
 627 /*@}*/
 628
 629 /*
 630  * Constants & macros for individual PORT_ISFR bitfields
 631  */
 632
 633 /*!
 634  * @name Register PORT_ISFR, field ISF[31:0] (W1C)
 635  *
 636  * Each bit in the field indicates the detection of the configured interrupt of
 637  * the same number as the field.
 638  *
 639  * Values:
 640  * - 0 - Configured interrupt is not detected.
 641  * - 1 - Configured interrupt is detected. If the pin is configured to generate
 642  *     a DMA request, then the corresponding flag will be cleared automatically
 643  *     at the completion of the requested DMA transfer. Otherwise, the flag
 644  *     remains set until a logic 1 is written to the flag. If the pin is configured for
 645  *     a level sensitive interrupt and the pin remains asserted, then the flag
 646  *     is set again immediately after it is cleared.
 647  */
 648 /*@{*/
 649 #define BP_PORT_ISFR_ISF     (0U)          /*!< Bit position for PORT_ISFR_ISF. */
 650 #define BM_PORT_ISFR_ISF     (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
 651 #define BS_PORT_ISFR_ISF     (32U)         /*!< Bit field size in bits for PORT_ISFR_ISF. */
 652
 653 /*! @brief Read current value of the PORT_ISFR_ISF field. */
 654 #define BR_PORT_ISFR_ISF(x)  (HW_PORT_ISFR(x).U)
 655
 656 /*! @brief Format value for bitfield PORT_ISFR_ISF. */
 657 #define BF_PORT_ISFR_ISF(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
 658
 659 /*! @brief Set the ISF field to a new value. */
 660 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
 661 /*@}*/
 662
 663 /*******************************************************************************
 664  * HW_PORT_DFER - Digital Filter Enable Register
 665  ******************************************************************************/
 666
 667 /*!
 668  * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
 669  *
 670  * Reset value: 0x00000000U
 671  *
 672  * The corresponding bit is read only for pins that do not support a digital
 673  * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
 674  * the pins that support digital filter. The digital filter configuration is valid
 675  * in all digital pin muxing modes.
 676  */
 677 typedef union _hw_port_dfer
 678 {
 679     uint32_t U;
 680     struct _hw_port_dfer_bitfields
 681     {
 682         uint32_t DFE : 32;             /*!< [31:0] Digital Filter Enable */
 683     } B;
 684 } hw_port_dfer_t;
 685
 686 /*!
 687  * @name Constants and macros for entire PORT_DFER register
 688  */
 689 /*@{*/
 690 #define HW_PORT_DFER_ADDR(x)     ((x) + 0xC0U)
 691
 692 #define HW_PORT_DFER(x)          (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
 693 #define HW_PORT_DFER_RD(x)       (HW_PORT_DFER(x).U)
 694 #define HW_PORT_DFER_WR(x, v)    (HW_PORT_DFER(x).U = (v))
 695 #define HW_PORT_DFER_SET(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) |  (v)))
 696 #define HW_PORT_DFER_CLR(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
 697 #define HW_PORT_DFER_TOG(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^  (v)))
 698 /*@}*/
 699
 700 /*
 701  * Constants & macros for individual PORT_DFER bitfields
 702  */
 703
 704 /*!
 705  * @name Register PORT_DFER, field DFE[31:0] (RW)
 706  *
 707  * The digital filter configuration is valid in all digital pin muxing modes.
 708  * The output of each digital filter is reset to zero at system reset and whenever
 709  * the digital filter is disabled. Each bit in the field enables the digital
 710  * filter of the same number as the field.
 711  *
 712  * Values:
 713  * - 0 - Digital filter is disabled on the corresponding pin and output of the
 714  *     digital filter is reset to zero.
 715  * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
 716  *     configured as a digital input.
 717  */
 718 /*@{*/
 719 #define BP_PORT_DFER_DFE     (0U)          /*!< Bit position for PORT_DFER_DFE. */
 720 #define BM_PORT_DFER_DFE     (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
 721 #define BS_PORT_DFER_DFE     (32U)         /*!< Bit field size in bits for PORT_DFER_DFE. */
 722
 723 /*! @brief Read current value of the PORT_DFER_DFE field. */
 724 #define BR_PORT_DFER_DFE(x)  (HW_PORT_DFER(x).U)
 725
 726 /*! @brief Format value for bitfield PORT_DFER_DFE. */
 727 #define BF_PORT_DFER_DFE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
 728
 729 /*! @brief Set the DFE field to a new value. */
 730 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
 731 /*@}*/
 732
 733 /*******************************************************************************
 734  * HW_PORT_DFCR - Digital Filter Clock Register
 735  ******************************************************************************/
 736
 737 /*!
 738  * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
 739  *
 740  * Reset value: 0x00000000U
 741  *
 742  * This register is read only for ports that do not support a digital filter.
 743  * The digital filter configuration is valid in all digital pin muxing modes.
 744  */
 745 typedef union _hw_port_dfcr
 746 {
 747     uint32_t U;
 748     struct _hw_port_dfcr_bitfields
 749     {
 750         uint32_t CS : 1;               /*!< [0] Clock Source */
 751         uint32_t RESERVED0 : 31;       /*!< [31:1]  */
 752     } B;
 753 } hw_port_dfcr_t;
 754
 755 /*!
 756  * @name Constants and macros for entire PORT_DFCR register
 757  */
 758 /*@{*/
 759 #define HW_PORT_DFCR_ADDR(x)     ((x) + 0xC4U)
 760
 761 #define HW_PORT_DFCR(x)          (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
 762 #define HW_PORT_DFCR_RD(x)       (HW_PORT_DFCR(x).U)
 763 #define HW_PORT_DFCR_WR(x, v)    (HW_PORT_DFCR(x).U = (v))
 764 #define HW_PORT_DFCR_SET(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) |  (v)))
 765 #define HW_PORT_DFCR_CLR(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
 766 #define HW_PORT_DFCR_TOG(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^  (v)))
 767 /*@}*/
 768
 769 /*
 770  * Constants & macros for individual PORT_DFCR bitfields
 771  */
 772
 773 /*!
 774  * @name Register PORT_DFCR, field CS[0] (RW)
 775  *
 776  * The digital filter configuration is valid in all digital pin muxing modes.
 777  * Configures the clock source for the digital input filters. Changing the filter
 778  * clock source must be done only when all digital filters are disabled.
 779  *
 780  * Values:
 781  * - 0 - Digital filters are clocked by the bus clock.
 782  * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
 783  */
 784 /*@{*/
 785 #define BP_PORT_DFCR_CS      (0U)          /*!< Bit position for PORT_DFCR_CS. */
 786 #define BM_PORT_DFCR_CS      (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
 787 #define BS_PORT_DFCR_CS      (1U)          /*!< Bit field size in bits for PORT_DFCR_CS. */
 788
 789 /*! @brief Read current value of the PORT_DFCR_CS field. */
 790 #define BR_PORT_DFCR_CS(x)   (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
 791
 792 /*! @brief Format value for bitfield PORT_DFCR_CS. */
 793 #define BF_PORT_DFCR_CS(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
 794
 795 /*! @brief Set the CS field to a new value. */
 796 #define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
 797 /*@}*/
 798
 799 /*******************************************************************************
 800  * HW_PORT_DFWR - Digital Filter Width Register
 801  ******************************************************************************/
 802
 803 /*!
 804  * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
 805  *
 806  * Reset value: 0x00000000U
 807  *
 808  * This register is read only for ports that do not support a digital filter.
 809  * The digital filter configuration is valid in all digital pin muxing modes.
 810  */
 811 typedef union _hw_port_dfwr
 812 {
 813     uint32_t U;
 814     struct _hw_port_dfwr_bitfields
 815     {
 816         uint32_t FILT : 5;             /*!< [4:0] Filter Length */
 817         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
 818     } B;
 819 } hw_port_dfwr_t;
 820
 821 /*!
 822  * @name Constants and macros for entire PORT_DFWR register
 823  */
 824 /*@{*/
 825 #define HW_PORT_DFWR_ADDR(x)     ((x) + 0xC8U)
 826
 827 #define HW_PORT_DFWR(x)          (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
 828 #define HW_PORT_DFWR_RD(x)       (HW_PORT_DFWR(x).U)
 829 #define HW_PORT_DFWR_WR(x, v)    (HW_PORT_DFWR(x).U = (v))
 830 #define HW_PORT_DFWR_SET(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) |  (v)))
 831 #define HW_PORT_DFWR_CLR(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
 832 #define HW_PORT_DFWR_TOG(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^  (v)))
 833 /*@}*/
 834
 835 /*
 836  * Constants & macros for individual PORT_DFWR bitfields
 837  */
 838
 839 /*!
 840  * @name Register PORT_DFWR, field FILT[4:0] (RW)
 841  *
 842  * The digital filter configuration is valid in all digital pin muxing modes.
 843  * Configures the maximum size of the glitches, in clock cycles, that the digital
 844  * filter absorbs for the enabled digital filters. Glitches that are longer than
 845  * this register setting will pass through the digital filter, and glitches that
 846  * are equal to or less than this register setting are filtered. Changing the
 847  * filter length must be done only after all filters are disabled.
 848  */
 849 /*@{*/
 850 #define BP_PORT_DFWR_FILT    (0U)          /*!< Bit position for PORT_DFWR_FILT. */
 851 #define BM_PORT_DFWR_FILT    (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
 852 #define BS_PORT_DFWR_FILT    (5U)          /*!< Bit field size in bits for PORT_DFWR_FILT. */
 853
 854 /*! @brief Read current value of the PORT_DFWR_FILT field. */
 855 #define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
 856
 857 /*! @brief Format value for bitfield PORT_DFWR_FILT. */
 858 #define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
 859
 860 /*! @brief Set the FILT field to a new value. */
 861 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
 862 /*@}*/
 863
 864 /*******************************************************************************
 865  * hw_port_t - module struct
 866  ******************************************************************************/
 867 /*!
 868  * @brief All PORT module registers.
 869  */
 870 #pragma pack(1)
 871 typedef struct _hw_port
 872 {
 873     __IO hw_port_pcrn_t PCRn[32];          /*!< [0x0] Pin Control Register n */
 874     __O hw_port_gpclr_t GPCLR;             /*!< [0x80] Global Pin Control Low Register */
 875     __O hw_port_gpchr_t GPCHR;             /*!< [0x84] Global Pin Control High Register */
 876     uint8_t _reserved0[24];
 877     __IO hw_port_isfr_t ISFR;              /*!< [0xA0] Interrupt Status Flag Register */
 878     uint8_t _reserved1[28];
 879     __IO hw_port_dfer_t DFER;              /*!< [0xC0] Digital Filter Enable Register */
 880     __IO hw_port_dfcr_t DFCR;              /*!< [0xC4] Digital Filter Clock Register */
 881     __IO hw_port_dfwr_t DFWR;              /*!< [0xC8] Digital Filter Width Register */
 882 } hw_port_t;
 883 #pragma pack()
 884
 885 /*! @brief Macro to access all PORT registers. */
 886 /*! @param x PORT module instance base address. */
 887 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 888  *     use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
 889 #define HW_PORT(x)     (*(hw_port_t *)(x))
 890
 891 #endif /* __HW_PORT_REGISTERS_H__ */
 892 /* EOF */