tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBRegs_STM32.h

   1 /**
   2   ******************************************************************************
   3   * @file    usb_regs.h
   4   * @author  MCD Application Team
   5   * @version V2.1.0
   6   * @date    19-March-2012
   7   * @brief   hardware registers
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  12   *
  13   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  14   * You may not use this file except in compliance with the License.
  15   * You may obtain a copy of the License at:
  16   *
  17   *        http://www.st.com/software_license_agreement_liberty_v2
  18   *
  19   * Unless required by applicable law or agreed to in writing, software
  20   * distributed under the License is distributed on an "AS IS" BASIS,
  21   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  22   * See the License for the specific language governing permissions and
  23   * limitations under the License.
  24   *
  25   ******************************************************************************
  26   */
  27
  28 #ifndef __USB_OTG_REGS_H__
  29 #define __USB_OTG_REGS_H__
  30
  31 typedef struct //000h
  32 {
  33   __IO uint32_t GOTGCTL;      /* USB_OTG Control and Status Register    000h*/
  34   __IO uint32_t GOTGINT;      /* USB_OTG Interrupt Register             004h*/
  35   __IO uint32_t GAHBCFG;      /* Core AHB Configuration Register    008h*/
  36   __IO uint32_t GUSBCFG;      /* Core USB Configuration Register    00Ch*/
  37   __IO uint32_t GRSTCTL;      /* Core Reset Register                010h*/
  38   __IO uint32_t GINTSTS;      /* Core Interrupt Register            014h*/
  39   __IO uint32_t GINTMSK;      /* Core Interrupt Mask Register       018h*/
  40   __IO uint32_t GRXSTSR;      /* Receive Sts Q Read Register        01Ch*/
  41   __IO uint32_t GRXSTSP;      /* Receive Sts Q Read & POP Register  020h*/
  42   __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register         024h*/
  43   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
  44   __IO uint32_t HNPTXSTS;     /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
  45   uint32_t Reserved30[2];     /* Reserved                           030h*/
  46   __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
  47   __IO uint32_t CID;          /* User ID Register                   03Ch*/
  48   uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
  49   __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
  50   __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
  51 }
  52 USB_OTG_GREGS;
  53
  54 typedef struct // 800h
  55 {
  56   __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
  57   __IO uint32_t DCTL;         /* dev Control Register         804h*/
  58   __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
  59   uint32_t Reserved0C;           /* Reserved                     80Ch*/
  60   __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
  61   __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
  62   __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
  63   __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
  64   uint32_t  Reserved20;          /* Reserved                     820h*/
  65   uint32_t Reserved9;       /* Reserved                     824h*/
  66   __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
  67   __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
  68   __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
  69   __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
  70 }
  71 USB_OTG_DREGS;
  72
  73 typedef struct
  74 {
  75   __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
  76   uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
  77   __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
  78   uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
  79   __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
  80   uint32_t Reserved14;
  81   __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
  82   uint32_t Reserved1C;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
  83 }
  84 USB_OTG_INEPREGS;
  85
  86 typedef struct
  87 {
  88   __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
  89   uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
  90   __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
  91   uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
  92   __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
  93   uint32_t Reserved14[3];
  94 }
  95 USB_OTG_OUTEPREGS;
  96
  97 typedef struct
  98 {
  99   __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
 100   __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
 101   __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
 102   uint32_t Reserved40C;                   /* Reserved                       40Ch*/
 103   __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
 104   __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
 105   __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
 106 }
 107 USB_OTG_HREGS;
 108
 109 typedef struct
 110 {
 111   __IO uint32_t HCCHAR;
 112   __IO uint32_t HCSPLT;
 113   __IO uint32_t HCINT;
 114   __IO uint32_t HCINTMSK;
 115   __IO uint32_t HCTSIZ;
 116   uint32_t Reserved[3];
 117 }
 118 USB_OTG_HC_REGS;
 119
 120 typedef struct
 121 {
 122     USB_OTG_GREGS         GREGS;
 123     uint32_t RESERVED0[188];
 124     USB_OTG_HREGS         HREGS;
 125     uint32_t RESERVED1[9];
 126     __IO uint32_t         HPRT;
 127     uint32_t RESERVED2[47];
 128     USB_OTG_HC_REGS       HC_REGS[8];
 129     uint32_t RESERVED3[128];
 130     USB_OTG_DREGS         DREGS;
 131     uint32_t RESERVED4[50];
 132     USB_OTG_INEPREGS      INEP_REGS[4];
 133     uint32_t RESERVED5[96];
 134     USB_OTG_OUTEPREGS     OUTEP_REGS[4];
 135     uint32_t RESERVED6[160];
 136     __IO uint32_t         PCGCCTL;
 137     uint32_t RESERVED7[127];
 138     __IO uint32_t         FIFO[4][1024];
 139 }
 140 USB_OTG_CORE_REGS;
 141
 142
 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
 145
 146 #endif //__USB_OTG_REGS_H__
 147
 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 149