tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q7.c

   1 /* ----------------------------------------------------------------------
   2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
   3 *
   4 * $Date:        17. January 2013
   5 * $Revision:    V1.4.1
   6 *
   7 * Project:          CMSIS DSP Library
   8 * Title:                arm_power_q7.c
   9 *
  10 * Description:  Sum of the squares of the elements of a Q7 vector.
  11 *
  12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
  13 *
  14 * Redistribution and use in source and binary forms, with or without
  15 * modification, are permitted provided that the following conditions
  16 * are met:
  17 *   - Redistributions of source code must retain the above copyright
  18 *     notice, this list of conditions and the following disclaimer.
  19 *   - Redistributions in binary form must reproduce the above copyright
  20 *     notice, this list of conditions and the following disclaimer in
  21 *     the documentation and/or other materials provided with the
  22 *     distribution.
  23 *   - Neither the name of ARM LIMITED nor the names of its contributors
  24 *     may be used to endorse or promote products derived from this
  25 *     software without specific prior written permission.
  26 *
  27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38 * POSSIBILITY OF SUCH DAMAGE.
  39 * -------------------------------------------------------------------- */
  40
  41 #include "arm_math.h"
  42
  43 /**
  44  * @ingroup groupStats
  45  */
  46
  47 /**
  48  * @addtogroup power
  49  * @{
  50  */
  51
  52 /**
  53  * @brief Sum of the squares of the elements of a Q7 vector.
  54  * @param[in]       *pSrc points to the input vector
  55  * @param[in]       blockSize length of the input vector
  56  * @param[out]      *pResult sum of the squares value returned here
  57  * @return none.
  58  *
  59  * @details
  60  * <b>Scaling and Overflow Behavior:</b>
  61  *
  62  * \par
  63  * The function is implemented using a 32-bit internal accumulator.
  64  * The input is represented in 1.7 format.
  65  * Intermediate multiplication yields a 2.14 format, and this
  66  * result is added without saturation to an accumulator in 18.14 format.
  67  * With 17 guard bits in the accumulator, there is no risk of overflow, and the
  68  * full precision of the intermediate multiplication is preserved.
  69  * Finally, the return result is in 18.14 format.
  70  *
  71  */
  72
  73 void arm_power_q7(
  74   q7_t * pSrc,
  75   uint32_t blockSize,
  76   q31_t * pResult)
  77 {
  78   q31_t sum = 0;                                 /* Temporary result storage */
  79   q7_t in;                                       /* Temporary variable to store input */
  80   uint32_t blkCnt;                               /* loop counter */
  81
  82 #ifndef ARM_MATH_CM0_FAMILY
  83
  84   /* Run the below code for Cortex-M4 and Cortex-M3 */
  85
  86   q31_t input1;                                  /* Temporary variable to store packed input */
  87   q31_t in1, in2;                                /* Temporary variables to store input */
  88
  89   /*loop Unrolling */
  90   blkCnt = blockSize >> 2u;
  91
  92   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
  93    ** a second loop below computes the remaining 1 to 3 samples. */
  94   while(blkCnt > 0u)
  95   {
  96     /* Reading two inputs of pSrc vector and packing */
  97     input1 = *__SIMD32(pSrc)++;
  98
  99     in1 = __SXTB16(__ROR(input1, 8));
 100     in2 = __SXTB16(input1);
 101
 102     /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
 103     /* calculate power and accumulate to accumulator */
 104     sum = __SMLAD(in1, in1, sum);
 105     sum = __SMLAD(in2, in2, sum);
 106
 107     /* Decrement the loop counter */
 108     blkCnt--;
 109   }
 110
 111   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
 112    ** No loop unrolling is used. */
 113   blkCnt = blockSize % 0x4u;
 114
 115 #else
 116
 117   /* Run the below code for Cortex-M0 */
 118
 119   /* Loop over blockSize number of values */
 120   blkCnt = blockSize;
 121
 122 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
 123
 124   while(blkCnt > 0u)
 125   {
 126     /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
 127     /* Compute Power and then store the result in a temporary variable, sum. */
 128     in = *pSrc++;
 129     sum += ((q15_t) in * in);
 130
 131     /* Decrement the loop counter */
 132     blkCnt--;
 133   }
 134
 135   /* Store the result in 18.14 format  */
 136   *pResult = sum;
 137 }
 138
 139 /**
 140  * @} end of power group
 141  */