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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_Freescale / TARGET_K20XX / TARGET_K20D50M / MK20D5.h
1 /*
2 ** ###################################################################
3 ** Compilers: ARM Compiler
4 ** Freescale C/C++ for Embedded ARM
5 ** GNU C Compiler
6 ** IAR ANSI C/C++ Compiler for ARM
7 **
8 ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
9 ** K20P32M50SF0RM Rev. 1, Oct 2011
10 ** K20P48M50SF0RM Rev. 1, Oct 2011
11 **
12 ** Version: rev. 2.0, 2012-03-19
13 **
14 ** Abstract:
15 ** CMSIS Peripheral Access Layer for MK20D5
16 **
17 ** Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
18 **
19 ** http: www.freescale.com
20 ** mail: support@freescale.com
21 **
22 ** Revisions:
23 ** - rev. 1.0 (2011-12-15)
24 ** Initial version
25 ** - rev. 2.0 (2012-03-19)
26 ** PDB Peripheral register structure updated.
27 ** DMA Registers and bits for unsupported DMA channels removed.
28 **
29 ** ###################################################################
30 */
31
32 /**
33 * @file MK20D5.h
34 * @version 2.0
35 * @date 2012-03-19
36 * @brief CMSIS Peripheral Access Layer for MK20D5
37 *
38 * CMSIS Peripheral Access Layer for MK20D5
39 */
40
41 #if !defined(MK20D5_H_)
42 #define MK20D5_H_ /**< Symbol preventing repeated inclusion */
43
44 /** Memory map major version (memory maps with equal major version number are
45 * compatible) */
46 #define MCU_MEM_MAP_VERSION 0x0200u
47 /** Memory map minor version */
48 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
49
50 /**
51 * @brief Macro to access a single bit of a peripheral register (bit band region
52 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
53 * @param Reg Register to access.
54 * @param Bit Bit number to access.
55 * @return Value of the targeted bit in the bit band region.
56 */
57 #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
58
59 /* ----------------------------------------------------------------------------
60 -- Interrupt vector numbers
61 ---------------------------------------------------------------------------- */
62
63 /**
64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
65 * @{
66 */
67
68 /** Interrupt Number Definitions */
69 typedef enum IRQn {
70 /* Core interrupts */
71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
72 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
73 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
74 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
75 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
76 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
77 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
78 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
79
80 /* Device specific interrupts */
81 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
82 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
83 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
84 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
85 DMA_Error_IRQn = 4, /**< DMA error interrupt */
86 Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
87 FTFL_IRQn = 6, /**< FTFL interrupt */
88 Read_Collision_IRQn = 7, /**< Read collision interrupt */
89 LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */
90 LLW_IRQn = 9, /**< Low Leakage Wakeup */
91 Watchdog_IRQn = 10, /**< WDOG interrupt */
92 I2C0_IRQn = 11, /**< I2C0 interrupt */
93 SPI0_IRQn = 12, /**< SPI0 interrupt */
94 I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */
95 I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */
96 UART0_LON_IRQn = 15, /**< UART0 LON interrupt */
97 UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */
98 UART0_ERR_IRQn = 17, /**< UART0 error interrupt */
99 UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */
100 UART1_ERR_IRQn = 19, /**< UART1 error interrupt */
101 UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */
102 UART2_ERR_IRQn = 21, /**< UART2 error interrupt */
103 ADC0_IRQn = 22, /**< ADC0 interrupt */
104 CMP0_IRQn = 23, /**< CMP0 interrupt */
105 CMP1_IRQn = 24, /**< CMP1 interrupt */
106 FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */
107 FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */
108 CMT_IRQn = 27, /**< CMT interrupt */
109 RTC_IRQn = 28, /**< RTC interrupt */
110 RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */
111 PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */
112 PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */
113 PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */
114 PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */
115 PDB0_IRQn = 34, /**< PDB0 interrupt */
116 USB0_IRQn = 35, /**< USB0 interrupt */
117 USBDCD_IRQn = 36, /**< USBDCD interrupt */
118 TSI0_IRQn = 37, /**< TSI0 interrupt */
119 MCG_IRQn = 38, /**< MCG interrupt */
120 LPTimer_IRQn = 39, /**< LPTimer interrupt */
121 PORTA_IRQn = 40, /**< Port A interrupt */
122 PORTB_IRQn = 41, /**< Port B interrupt */
123 PORTC_IRQn = 42, /**< Port C interrupt */
124 PORTD_IRQn = 43, /**< Port D interrupt */
125 PORTE_IRQn = 44, /**< Port E interrupt */
126 SWI_IRQn = 45 /**< Software interrupt */
127 } IRQn_Type;
128
129 /**
130 * @}
131 */ /* end of group Interrupt_vector_numbers */
132
133
134 /* ----------------------------------------------------------------------------
135 -- Cortex M4 Core Configuration
136 ---------------------------------------------------------------------------- */
137
138 /**
139 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
140 * @{
141 */
142
143 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
144 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
145 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
146
147 #include "core_cm4.h" /* Core Peripheral Access Layer */
148 #include "system_MK20D5.h" /* Device specific configuration file */
149
150 /**
151 * @}
152 */ /* end of group Cortex_Core_Configuration */
153
154
155 /* ----------------------------------------------------------------------------
156 -- Device Peripheral Access Layer
157 ---------------------------------------------------------------------------- */
158
159 /**
160 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
161 * @{
162 */
163
164
165 /*
166 ** Start of section using anonymous unions
167 */
168
169 #if defined(__ARMCC_VERSION)
170 #pragma push
171 #pragma anon_unions
172 #elif defined(__CWCC__)
173 #pragma push
174 #pragma cpp_extensions on
175 #elif defined(__GNUC__)
176 /* anonymous unions are enabled by default */
177 #elif defined(__IAR_SYSTEMS_ICC__)
178 #pragma language=extended
179 #else
180 #error Not supported compiler type
181 #endif
182
183 /* ----------------------------------------------------------------------------
184 -- ADC Peripheral Access Layer
185 ---------------------------------------------------------------------------- */
186
187 /**
188 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
189 * @{
190 */
191
192 /** ADC - Register Layout Typedef */
193 typedef struct {
194 __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
195 __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
196 __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
197 __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
198 __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
199 __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
200 __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
201 __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
202 __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
203 __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
204 __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
205 __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
206 __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
207 __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
208 __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
209 __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
210 __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
211 __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
212 uint8_t RESERVED_0[4];
213 __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
214 __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
215 __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
216 __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
217 __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
218 __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
219 __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
220 } ADC_Type;
221
222 /* ----------------------------------------------------------------------------
223 -- ADC Register Masks
224 ---------------------------------------------------------------------------- */
225
226 /**
227 * @addtogroup ADC_Register_Masks ADC Register Masks
228 * @{
229 */
230
231 /* SC1 Bit Fields */
232 #define ADC_SC1_ADCH_MASK 0x1Fu
233 #define ADC_SC1_ADCH_SHIFT 0
234 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
235 #define ADC_SC1_DIFF_MASK 0x20u
236 #define ADC_SC1_DIFF_SHIFT 5
237 #define ADC_SC1_AIEN_MASK 0x40u
238 #define ADC_SC1_AIEN_SHIFT 6
239 #define ADC_SC1_COCO_MASK 0x80u
240 #define ADC_SC1_COCO_SHIFT 7
241 /* CFG1 Bit Fields */
242 #define ADC_CFG1_ADICLK_MASK 0x3u
243 #define ADC_CFG1_ADICLK_SHIFT 0
244 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
245 #define ADC_CFG1_MODE_MASK 0xCu
246 #define ADC_CFG1_MODE_SHIFT 2
247 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
248 #define ADC_CFG1_ADLSMP_MASK 0x10u
249 #define ADC_CFG1_ADLSMP_SHIFT 4
250 #define ADC_CFG1_ADIV_MASK 0x60u
251 #define ADC_CFG1_ADIV_SHIFT 5
252 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
253 #define ADC_CFG1_ADLPC_MASK 0x80u
254 #define ADC_CFG1_ADLPC_SHIFT 7
255 /* CFG2 Bit Fields */
256 #define ADC_CFG2_ADLSTS_MASK 0x3u
257 #define ADC_CFG2_ADLSTS_SHIFT 0
258 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
259 #define ADC_CFG2_ADHSC_MASK 0x4u
260 #define ADC_CFG2_ADHSC_SHIFT 2
261 #define ADC_CFG2_ADACKEN_MASK 0x8u
262 #define ADC_CFG2_ADACKEN_SHIFT 3
263 #define ADC_CFG2_MUXSEL_MASK 0x10u
264 #define ADC_CFG2_MUXSEL_SHIFT 4
265 /* R Bit Fields */
266 #define ADC_R_D_MASK 0xFFFFu
267 #define ADC_R_D_SHIFT 0
268 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
269 /* CV1 Bit Fields */
270 #define ADC_CV1_CV_MASK 0xFFFFu
271 #define ADC_CV1_CV_SHIFT 0
272 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
273 /* CV2 Bit Fields */
274 #define ADC_CV2_CV_MASK 0xFFFFu
275 #define ADC_CV2_CV_SHIFT 0
276 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
277 /* SC2 Bit Fields */
278 #define ADC_SC2_REFSEL_MASK 0x3u
279 #define ADC_SC2_REFSEL_SHIFT 0
280 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
281 #define ADC_SC2_DMAEN_MASK 0x4u
282 #define ADC_SC2_DMAEN_SHIFT 2
283 #define ADC_SC2_ACREN_MASK 0x8u
284 #define ADC_SC2_ACREN_SHIFT 3
285 #define ADC_SC2_ACFGT_MASK 0x10u
286 #define ADC_SC2_ACFGT_SHIFT 4
287 #define ADC_SC2_ACFE_MASK 0x20u
288 #define ADC_SC2_ACFE_SHIFT 5
289 #define ADC_SC2_ADTRG_MASK 0x40u
290 #define ADC_SC2_ADTRG_SHIFT 6
291 #define ADC_SC2_ADACT_MASK 0x80u
292 #define ADC_SC2_ADACT_SHIFT 7
293 /* SC3 Bit Fields */
294 #define ADC_SC3_AVGS_MASK 0x3u
295 #define ADC_SC3_AVGS_SHIFT 0
296 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
297 #define ADC_SC3_AVGE_MASK 0x4u
298 #define ADC_SC3_AVGE_SHIFT 2
299 #define ADC_SC3_ADCO_MASK 0x8u
300 #define ADC_SC3_ADCO_SHIFT 3
301 #define ADC_SC3_CALF_MASK 0x40u
302 #define ADC_SC3_CALF_SHIFT 6
303 #define ADC_SC3_CAL_MASK 0x80u
304 #define ADC_SC3_CAL_SHIFT 7
305 /* OFS Bit Fields */
306 #define ADC_OFS_OFS_MASK 0xFFFFu
307 #define ADC_OFS_OFS_SHIFT 0
308 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
309 /* PG Bit Fields */
310 #define ADC_PG_PG_MASK 0xFFFFu
311 #define ADC_PG_PG_SHIFT 0
312 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
313 /* MG Bit Fields */
314 #define ADC_MG_MG_MASK 0xFFFFu
315 #define ADC_MG_MG_SHIFT 0
316 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
317 /* CLPD Bit Fields */
318 #define ADC_CLPD_CLPD_MASK 0x3Fu
319 #define ADC_CLPD_CLPD_SHIFT 0
320 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
321 /* CLPS Bit Fields */
322 #define ADC_CLPS_CLPS_MASK 0x3Fu
323 #define ADC_CLPS_CLPS_SHIFT 0
324 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
325 /* CLP4 Bit Fields */
326 #define ADC_CLP4_CLP4_MASK 0x3FFu
327 #define ADC_CLP4_CLP4_SHIFT 0
328 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
329 /* CLP3 Bit Fields */
330 #define ADC_CLP3_CLP3_MASK 0x1FFu
331 #define ADC_CLP3_CLP3_SHIFT 0
332 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
333 /* CLP2 Bit Fields */
334 #define ADC_CLP2_CLP2_MASK 0xFFu
335 #define ADC_CLP2_CLP2_SHIFT 0
336 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
337 /* CLP1 Bit Fields */
338 #define ADC_CLP1_CLP1_MASK 0x7Fu
339 #define ADC_CLP1_CLP1_SHIFT 0
340 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
341 /* CLP0 Bit Fields */
342 #define ADC_CLP0_CLP0_MASK 0x3Fu
343 #define ADC_CLP0_CLP0_SHIFT 0
344 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
345 /* CLMD Bit Fields */
346 #define ADC_CLMD_CLMD_MASK 0x3Fu
347 #define ADC_CLMD_CLMD_SHIFT 0
348 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
349 /* CLMS Bit Fields */
350 #define ADC_CLMS_CLMS_MASK 0x3Fu
351 #define ADC_CLMS_CLMS_SHIFT 0
352 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
353 /* CLM4 Bit Fields */
354 #define ADC_CLM4_CLM4_MASK 0x3FFu
355 #define ADC_CLM4_CLM4_SHIFT 0
356 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
357 /* CLM3 Bit Fields */
358 #define ADC_CLM3_CLM3_MASK 0x1FFu
359 #define ADC_CLM3_CLM3_SHIFT 0
360 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
361 /* CLM2 Bit Fields */
362 #define ADC_CLM2_CLM2_MASK 0xFFu
363 #define ADC_CLM2_CLM2_SHIFT 0
364 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
365 /* CLM1 Bit Fields */
366 #define ADC_CLM1_CLM1_MASK 0x7Fu
367 #define ADC_CLM1_CLM1_SHIFT 0
368 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
369 /* CLM0 Bit Fields */
370 #define ADC_CLM0_CLM0_MASK 0x3Fu
371 #define ADC_CLM0_CLM0_SHIFT 0
372 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
373
374 /**
375 * @}
376 */ /* end of group ADC_Register_Masks */
377
378
379 /* ADC - Peripheral instance base addresses */
380 /** Peripheral ADC0 base address */
381 #define ADC0_BASE (0x4003B000u)
382 /** Peripheral ADC0 base pointer */
383 #define ADC0 ((ADC_Type *)ADC0_BASE)
384
385 /**
386 * @}
387 */ /* end of group ADC_Peripheral_Access_Layer */
388
389
390 /* ----------------------------------------------------------------------------
391 -- CMP Peripheral Access Layer
392 ---------------------------------------------------------------------------- */
393
394 /**
395 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
396 * @{
397 */
398
399 /** CMP - Register Layout Typedef */
400 typedef struct {
401 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
402 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
403 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
404 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
405 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
406 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
407 } CMP_Type;
408
409 /* ----------------------------------------------------------------------------
410 -- CMP Register Masks
411 ---------------------------------------------------------------------------- */
412
413 /**
414 * @addtogroup CMP_Register_Masks CMP Register Masks
415 * @{
416 */
417
418 /* CR0 Bit Fields */
419 #define CMP_CR0_HYSTCTR_MASK 0x3u
420 #define CMP_CR0_HYSTCTR_SHIFT 0
421 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
422 #define CMP_CR0_FILTER_CNT_MASK 0x70u
423 #define CMP_CR0_FILTER_CNT_SHIFT 4
424 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
425 /* CR1 Bit Fields */
426 #define CMP_CR1_EN_MASK 0x1u
427 #define CMP_CR1_EN_SHIFT 0
428 #define CMP_CR1_OPE_MASK 0x2u
429 #define CMP_CR1_OPE_SHIFT 1
430 #define CMP_CR1_COS_MASK 0x4u
431 #define CMP_CR1_COS_SHIFT 2
432 #define CMP_CR1_INV_MASK 0x8u
433 #define CMP_CR1_INV_SHIFT 3
434 #define CMP_CR1_PMODE_MASK 0x10u
435 #define CMP_CR1_PMODE_SHIFT 4
436 #define CMP_CR1_WE_MASK 0x40u
437 #define CMP_CR1_WE_SHIFT 6
438 #define CMP_CR1_SE_MASK 0x80u
439 #define CMP_CR1_SE_SHIFT 7
440 /* FPR Bit Fields */
441 #define CMP_FPR_FILT_PER_MASK 0xFFu
442 #define CMP_FPR_FILT_PER_SHIFT 0
443 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
444 /* SCR Bit Fields */
445 #define CMP_SCR_COUT_MASK 0x1u
446 #define CMP_SCR_COUT_SHIFT 0
447 #define CMP_SCR_CFF_MASK 0x2u
448 #define CMP_SCR_CFF_SHIFT 1
449 #define CMP_SCR_CFR_MASK 0x4u
450 #define CMP_SCR_CFR_SHIFT 2
451 #define CMP_SCR_IEF_MASK 0x8u
452 #define CMP_SCR_IEF_SHIFT 3
453 #define CMP_SCR_IER_MASK 0x10u
454 #define CMP_SCR_IER_SHIFT 4
455 #define CMP_SCR_DMAEN_MASK 0x40u
456 #define CMP_SCR_DMAEN_SHIFT 6
457 /* DACCR Bit Fields */
458 #define CMP_DACCR_VOSEL_MASK 0x3Fu
459 #define CMP_DACCR_VOSEL_SHIFT 0
460 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
461 #define CMP_DACCR_VRSEL_MASK 0x40u
462 #define CMP_DACCR_VRSEL_SHIFT 6
463 #define CMP_DACCR_DACEN_MASK 0x80u
464 #define CMP_DACCR_DACEN_SHIFT 7
465 /* MUXCR Bit Fields */
466 #define CMP_MUXCR_MSEL_MASK 0x7u
467 #define CMP_MUXCR_MSEL_SHIFT 0
468 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
469 #define CMP_MUXCR_PSEL_MASK 0x38u
470 #define CMP_MUXCR_PSEL_SHIFT 3
471 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
472
473 /**
474 * @}
475 */ /* end of group CMP_Register_Masks */
476
477
478 /* CMP - Peripheral instance base addresses */
479 /** Peripheral CMP0 base address */
480 #define CMP0_BASE (0x40073000u)
481 /** Peripheral CMP0 base pointer */
482 #define CMP0 ((CMP_Type *)CMP0_BASE)
483 /** Peripheral CMP1 base address */
484 #define CMP1_BASE (0x40073008u)
485 /** Peripheral CMP1 base pointer */
486 #define CMP1 ((CMP_Type *)CMP1_BASE)
487
488 /**
489 * @}
490 */ /* end of group CMP_Peripheral_Access_Layer */
491
492
493 /* ----------------------------------------------------------------------------
494 -- CMT Peripheral Access Layer
495 ---------------------------------------------------------------------------- */
496
497 /**
498 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
499 * @{
500 */
501
502 /** CMT - Register Layout Typedef */
503 typedef struct {
504 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
505 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
506 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
507 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
508 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
509 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
510 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
511 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
512 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
513 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
514 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
515 __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
516 } CMT_Type;
517
518 /* ----------------------------------------------------------------------------
519 -- CMT Register Masks
520 ---------------------------------------------------------------------------- */
521
522 /**
523 * @addtogroup CMT_Register_Masks CMT Register Masks
524 * @{
525 */
526
527 /* CGH1 Bit Fields */
528 #define CMT_CGH1_PH_MASK 0xFFu
529 #define CMT_CGH1_PH_SHIFT 0
530 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
531 /* CGL1 Bit Fields */
532 #define CMT_CGL1_PL_MASK 0xFFu
533 #define CMT_CGL1_PL_SHIFT 0
534 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
535 /* CGH2 Bit Fields */
536 #define CMT_CGH2_SH_MASK 0xFFu
537 #define CMT_CGH2_SH_SHIFT 0
538 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
539 /* CGL2 Bit Fields */
540 #define CMT_CGL2_SL_MASK 0xFFu
541 #define CMT_CGL2_SL_SHIFT 0
542 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
543 /* OC Bit Fields */
544 #define CMT_OC_IROPEN_MASK 0x20u
545 #define CMT_OC_IROPEN_SHIFT 5
546 #define CMT_OC_CMTPOL_MASK 0x40u
547 #define CMT_OC_CMTPOL_SHIFT 6
548 #define CMT_OC_IROL_MASK 0x80u
549 #define CMT_OC_IROL_SHIFT 7
550 /* MSC Bit Fields */
551 #define CMT_MSC_MCGEN_MASK 0x1u
552 #define CMT_MSC_MCGEN_SHIFT 0
553 #define CMT_MSC_EOCIE_MASK 0x2u
554 #define CMT_MSC_EOCIE_SHIFT 1
555 #define CMT_MSC_FSK_MASK 0x4u
556 #define CMT_MSC_FSK_SHIFT 2
557 #define CMT_MSC_BASE_MASK 0x8u
558 #define CMT_MSC_BASE_SHIFT 3
559 #define CMT_MSC_EXSPC_MASK 0x10u
560 #define CMT_MSC_EXSPC_SHIFT 4
561 #define CMT_MSC_CMTDIV_MASK 0x60u
562 #define CMT_MSC_CMTDIV_SHIFT 5
563 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
564 #define CMT_MSC_EOCF_MASK 0x80u
565 #define CMT_MSC_EOCF_SHIFT 7
566 /* CMD1 Bit Fields */
567 #define CMT_CMD1_MB_MASK 0xFFu
568 #define CMT_CMD1_MB_SHIFT 0
569 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
570 /* CMD2 Bit Fields */
571 #define CMT_CMD2_MB_MASK 0xFFu
572 #define CMT_CMD2_MB_SHIFT 0
573 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
574 /* CMD3 Bit Fields */
575 #define CMT_CMD3_SB_MASK 0xFFu
576 #define CMT_CMD3_SB_SHIFT 0
577 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
578 /* CMD4 Bit Fields */
579 #define CMT_CMD4_SB_MASK 0xFFu
580 #define CMT_CMD4_SB_SHIFT 0
581 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
582 /* PPS Bit Fields */
583 #define CMT_PPS_PPSDIV_MASK 0xFu
584 #define CMT_PPS_PPSDIV_SHIFT 0
585 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
586 /* DMA Bit Fields */
587 #define CMT_DMA_DMA_MASK 0x1u
588 #define CMT_DMA_DMA_SHIFT 0
589
590 /**
591 * @}
592 */ /* end of group CMT_Register_Masks */
593
594
595 /* CMT - Peripheral instance base addresses */
596 /** Peripheral CMT base address */
597 #define CMT_BASE (0x40062000u)
598 /** Peripheral CMT base pointer */
599 #define CMT ((CMT_Type *)CMT_BASE)
600
601 /**
602 * @}
603 */ /* end of group CMT_Peripheral_Access_Layer */
604
605
606 /* ----------------------------------------------------------------------------
607 -- CRC Peripheral Access Layer
608 ---------------------------------------------------------------------------- */
609
610 /**
611 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
612 * @{
613 */
614
615 /** CRC - Register Layout Typedef */
616 typedef struct {
617 union { /* offset: 0x0 */
618 struct { /* offset: 0x0 */
619 __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
620 __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
621 } ACCESS16BIT;
622 __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
623 struct { /* offset: 0x0 */
624 __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
625 __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
626 __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
627 __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
628 } ACCESS8BIT;
629 };
630 union { /* offset: 0x4 */
631 struct { /* offset: 0x4 */
632 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
633 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
634 } GPOLY_ACCESS16BIT;
635 __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
636 struct { /* offset: 0x4 */
637 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
638 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
639 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
640 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
641 } GPOLY_ACCESS8BIT;
642 };
643 union { /* offset: 0x8 */
644 __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
645 struct { /* offset: 0x8 */
646 uint8_t RESERVED_0[3];
647 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
648 } CTRL_ACCESS8BIT;
649 };
650 } CRC_Type;
651
652 /* ----------------------------------------------------------------------------
653 -- CRC Register Masks
654 ---------------------------------------------------------------------------- */
655
656 /**
657 * @addtogroup CRC_Register_Masks CRC Register Masks
658 * @{
659 */
660
661 /* CRCL Bit Fields */
662 #define CRC_CRCL_CRCL_MASK 0xFFFFu
663 #define CRC_CRCL_CRCL_SHIFT 0
664 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
665 /* CRCH Bit Fields */
666 #define CRC_CRCH_CRCH_MASK 0xFFFFu
667 #define CRC_CRCH_CRCH_SHIFT 0
668 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
669 /* CRC Bit Fields */
670 #define CRC_CRC_LL_MASK 0xFFu
671 #define CRC_CRC_LL_SHIFT 0
672 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
673 #define CRC_CRC_LU_MASK 0xFF00u
674 #define CRC_CRC_LU_SHIFT 8
675 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
676 #define CRC_CRC_HL_MASK 0xFF0000u
677 #define CRC_CRC_HL_SHIFT 16
678 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
679 #define CRC_CRC_HU_MASK 0xFF000000u
680 #define CRC_CRC_HU_SHIFT 24
681 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
682 /* CRCLL Bit Fields */
683 #define CRC_CRCLL_CRCLL_MASK 0xFFu
684 #define CRC_CRCLL_CRCLL_SHIFT 0
685 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
686 /* CRCLU Bit Fields */
687 #define CRC_CRCLU_CRCLU_MASK 0xFFu
688 #define CRC_CRCLU_CRCLU_SHIFT 0
689 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
690 /* CRCHL Bit Fields */
691 #define CRC_CRCHL_CRCHL_MASK 0xFFu
692 #define CRC_CRCHL_CRCHL_SHIFT 0
693 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
694 /* CRCHU Bit Fields */
695 #define CRC_CRCHU_CRCHU_MASK 0xFFu
696 #define CRC_CRCHU_CRCHU_SHIFT 0
697 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
698 /* GPOLYL Bit Fields */
699 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
700 #define CRC_GPOLYL_GPOLYL_SHIFT 0
701 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
702 /* GPOLYH Bit Fields */
703 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
704 #define CRC_GPOLYH_GPOLYH_SHIFT 0
705 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
706 /* GPOLY Bit Fields */
707 #define CRC_GPOLY_LOW_MASK 0xFFFFu
708 #define CRC_GPOLY_LOW_SHIFT 0
709 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
710 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
711 #define CRC_GPOLY_HIGH_SHIFT 16
712 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
713 /* GPOLYLL Bit Fields */
714 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
715 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
716 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
717 /* GPOLYLU Bit Fields */
718 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
719 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
720 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
721 /* GPOLYHL Bit Fields */
722 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
723 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
724 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
725 /* GPOLYHU Bit Fields */
726 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
727 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
728 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
729 /* CTRL Bit Fields */
730 #define CRC_CTRL_TCRC_MASK 0x1000000u
731 #define CRC_CTRL_TCRC_SHIFT 24
732 #define CRC_CTRL_WAS_MASK 0x2000000u
733 #define CRC_CTRL_WAS_SHIFT 25
734 #define CRC_CTRL_FXOR_MASK 0x4000000u
735 #define CRC_CTRL_FXOR_SHIFT 26
736 #define CRC_CTRL_TOTR_MASK 0x30000000u
737 #define CRC_CTRL_TOTR_SHIFT 28
738 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
739 #define CRC_CTRL_TOT_MASK 0xC0000000u
740 #define CRC_CTRL_TOT_SHIFT 30
741 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
742 /* CTRLHU Bit Fields */
743 #define CRC_CTRLHU_TCRC_MASK 0x1u
744 #define CRC_CTRLHU_TCRC_SHIFT 0
745 #define CRC_CTRLHU_WAS_MASK 0x2u
746 #define CRC_CTRLHU_WAS_SHIFT 1
747 #define CRC_CTRLHU_FXOR_MASK 0x4u
748 #define CRC_CTRLHU_FXOR_SHIFT 2
749 #define CRC_CTRLHU_TOTR_MASK 0x30u
750 #define CRC_CTRLHU_TOTR_SHIFT 4
751 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
752 #define CRC_CTRLHU_TOT_MASK 0xC0u
753 #define CRC_CTRLHU_TOT_SHIFT 6
754 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
755
756 /**
757 * @}
758 */ /* end of group CRC_Register_Masks */
759
760
761 /* CRC - Peripheral instance base addresses */
762 /** Peripheral CRC base address */
763 #define CRC_BASE (0x40032000u)
764 /** Peripheral CRC base pointer */
765 #define CRC0 ((CRC_Type *)CRC_BASE)
766
767 /**
768 * @}
769 */ /* end of group CRC_Peripheral_Access_Layer */
770
771
772 /* ----------------------------------------------------------------------------
773 -- DMA Peripheral Access Layer
774 ---------------------------------------------------------------------------- */
775
776 /**
777 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
778 * @{
779 */
780
781 /** DMA - Register Layout Typedef */
782 typedef struct {
783 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
784 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
785 uint8_t RESERVED_0[4];
786 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
787 uint8_t RESERVED_1[4];
788 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
789 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
790 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
791 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
792 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
793 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
794 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
795 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
796 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
797 uint8_t RESERVED_2[4];
798 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
799 uint8_t RESERVED_3[4];
800 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
801 uint8_t RESERVED_4[4];
802 __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
803 uint8_t RESERVED_5[200];
804 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
805 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
806 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
807 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
808 uint8_t RESERVED_6[3836];
809 struct { /* offset: 0x1000, array step: 0x20 */
810 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
811 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
812 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
813 union { /* offset: 0x1008, array step: 0x20 */
814 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
815 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
816 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
817 };
818 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
819 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
820 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
821 union { /* offset: 0x1016, array step: 0x20 */
822 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
823 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
824 };
825 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
826 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
827 union { /* offset: 0x101E, array step: 0x20 */
828 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
829 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
830 };
831 } TCD[4];
832 } DMA_Type;
833
834 /* ----------------------------------------------------------------------------
835 -- DMA Register Masks
836 ---------------------------------------------------------------------------- */
837
838 /**
839 * @addtogroup DMA_Register_Masks DMA Register Masks
840 * @{
841 */
842
843 /* CR Bit Fields */
844 #define DMA_CR_EDBG_MASK 0x2u
845 #define DMA_CR_EDBG_SHIFT 1
846 #define DMA_CR_ERCA_MASK 0x4u
847 #define DMA_CR_ERCA_SHIFT 2
848 #define DMA_CR_HOE_MASK 0x10u
849 #define DMA_CR_HOE_SHIFT 4
850 #define DMA_CR_HALT_MASK 0x20u
851 #define DMA_CR_HALT_SHIFT 5
852 #define DMA_CR_CLM_MASK 0x40u
853 #define DMA_CR_CLM_SHIFT 6
854 #define DMA_CR_EMLM_MASK 0x80u
855 #define DMA_CR_EMLM_SHIFT 7
856 #define DMA_CR_ECX_MASK 0x10000u
857 #define DMA_CR_ECX_SHIFT 16
858 #define DMA_CR_CX_MASK 0x20000u
859 #define DMA_CR_CX_SHIFT 17
860 /* ES Bit Fields */
861 #define DMA_ES_DBE_MASK 0x1u
862 #define DMA_ES_DBE_SHIFT 0
863 #define DMA_ES_SBE_MASK 0x2u
864 #define DMA_ES_SBE_SHIFT 1
865 #define DMA_ES_SGE_MASK 0x4u
866 #define DMA_ES_SGE_SHIFT 2
867 #define DMA_ES_NCE_MASK 0x8u
868 #define DMA_ES_NCE_SHIFT 3
869 #define DMA_ES_DOE_MASK 0x10u
870 #define DMA_ES_DOE_SHIFT 4
871 #define DMA_ES_DAE_MASK 0x20u
872 #define DMA_ES_DAE_SHIFT 5
873 #define DMA_ES_SOE_MASK 0x40u
874 #define DMA_ES_SOE_SHIFT 6
875 #define DMA_ES_SAE_MASK 0x80u
876 #define DMA_ES_SAE_SHIFT 7
877 #define DMA_ES_ERRCHN_MASK 0xF00u
878 #define DMA_ES_ERRCHN_SHIFT 8
879 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
880 #define DMA_ES_CPE_MASK 0x4000u
881 #define DMA_ES_CPE_SHIFT 14
882 #define DMA_ES_ECX_MASK 0x10000u
883 #define DMA_ES_ECX_SHIFT 16
884 #define DMA_ES_VLD_MASK 0x80000000u
885 #define DMA_ES_VLD_SHIFT 31
886 /* ERQ Bit Fields */
887 #define DMA_ERQ_ERQ0_MASK 0x1u
888 #define DMA_ERQ_ERQ0_SHIFT 0
889 #define DMA_ERQ_ERQ1_MASK 0x2u
890 #define DMA_ERQ_ERQ1_SHIFT 1
891 #define DMA_ERQ_ERQ2_MASK 0x4u
892 #define DMA_ERQ_ERQ2_SHIFT 2
893 #define DMA_ERQ_ERQ3_MASK 0x8u
894 #define DMA_ERQ_ERQ3_SHIFT 3
895 /* EEI Bit Fields */
896 #define DMA_EEI_EEI0_MASK 0x1u
897 #define DMA_EEI_EEI0_SHIFT 0
898 #define DMA_EEI_EEI1_MASK 0x2u
899 #define DMA_EEI_EEI1_SHIFT 1
900 #define DMA_EEI_EEI2_MASK 0x4u
901 #define DMA_EEI_EEI2_SHIFT 2
902 #define DMA_EEI_EEI3_MASK 0x8u
903 #define DMA_EEI_EEI3_SHIFT 3
904 /* CEEI Bit Fields */
905 #define DMA_CEEI_CEEI_MASK 0xFu
906 #define DMA_CEEI_CEEI_SHIFT 0
907 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
908 #define DMA_CEEI_CAEE_MASK 0x40u
909 #define DMA_CEEI_CAEE_SHIFT 6
910 #define DMA_CEEI_NOP_MASK 0x80u
911 #define DMA_CEEI_NOP_SHIFT 7
912 /* SEEI Bit Fields */
913 #define DMA_SEEI_SEEI_MASK 0xFu
914 #define DMA_SEEI_SEEI_SHIFT 0
915 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
916 #define DMA_SEEI_SAEE_MASK 0x40u
917 #define DMA_SEEI_SAEE_SHIFT 6
918 #define DMA_SEEI_NOP_MASK 0x80u
919 #define DMA_SEEI_NOP_SHIFT 7
920 /* CERQ Bit Fields */
921 #define DMA_CERQ_CERQ_MASK 0xFu
922 #define DMA_CERQ_CERQ_SHIFT 0
923 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
924 #define DMA_CERQ_CAER_MASK 0x40u
925 #define DMA_CERQ_CAER_SHIFT 6
926 #define DMA_CERQ_NOP_MASK 0x80u
927 #define DMA_CERQ_NOP_SHIFT 7
928 /* SERQ Bit Fields */
929 #define DMA_SERQ_SERQ_MASK 0xFu
930 #define DMA_SERQ_SERQ_SHIFT 0
931 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
932 #define DMA_SERQ_SAER_MASK 0x40u
933 #define DMA_SERQ_SAER_SHIFT 6
934 #define DMA_SERQ_NOP_MASK 0x80u
935 #define DMA_SERQ_NOP_SHIFT 7
936 /* CDNE Bit Fields */
937 #define DMA_CDNE_CDNE_MASK 0xFu
938 #define DMA_CDNE_CDNE_SHIFT 0
939 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
940 #define DMA_CDNE_CADN_MASK 0x40u
941 #define DMA_CDNE_CADN_SHIFT 6
942 #define DMA_CDNE_NOP_MASK 0x80u
943 #define DMA_CDNE_NOP_SHIFT 7
944 /* SSRT Bit Fields */
945 #define DMA_SSRT_SSRT_MASK 0xFu
946 #define DMA_SSRT_SSRT_SHIFT 0
947 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
948 #define DMA_SSRT_SAST_MASK 0x40u
949 #define DMA_SSRT_SAST_SHIFT 6
950 #define DMA_SSRT_NOP_MASK 0x80u
951 #define DMA_SSRT_NOP_SHIFT 7
952 /* CERR Bit Fields */
953 #define DMA_CERR_CERR_MASK 0xFu
954 #define DMA_CERR_CERR_SHIFT 0
955 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
956 #define DMA_CERR_CAEI_MASK 0x40u
957 #define DMA_CERR_CAEI_SHIFT 6
958 #define DMA_CERR_NOP_MASK 0x80u
959 #define DMA_CERR_NOP_SHIFT 7
960 /* CINT Bit Fields */
961 #define DMA_CINT_CINT_MASK 0xFu
962 #define DMA_CINT_CINT_SHIFT 0
963 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
964 #define DMA_CINT_CAIR_MASK 0x40u
965 #define DMA_CINT_CAIR_SHIFT 6
966 #define DMA_CINT_NOP_MASK 0x80u
967 #define DMA_CINT_NOP_SHIFT 7
968 /* INT Bit Fields */
969 #define DMA_INT_INT0_MASK 0x1u
970 #define DMA_INT_INT0_SHIFT 0
971 #define DMA_INT_INT1_MASK 0x2u
972 #define DMA_INT_INT1_SHIFT 1
973 #define DMA_INT_INT2_MASK 0x4u
974 #define DMA_INT_INT2_SHIFT 2
975 #define DMA_INT_INT3_MASK 0x8u
976 #define DMA_INT_INT3_SHIFT 3
977 /* ERR Bit Fields */
978 #define DMA_ERR_ERR0_MASK 0x1u
979 #define DMA_ERR_ERR0_SHIFT 0
980 #define DMA_ERR_ERR1_MASK 0x2u
981 #define DMA_ERR_ERR1_SHIFT 1
982 #define DMA_ERR_ERR2_MASK 0x4u
983 #define DMA_ERR_ERR2_SHIFT 2
984 #define DMA_ERR_ERR3_MASK 0x8u
985 #define DMA_ERR_ERR3_SHIFT 3
986 /* HRS Bit Fields */
987 #define DMA_HRS_HRS0_MASK 0x1u
988 #define DMA_HRS_HRS0_SHIFT 0
989 #define DMA_HRS_HRS1_MASK 0x2u
990 #define DMA_HRS_HRS1_SHIFT 1
991 #define DMA_HRS_HRS2_MASK 0x4u
992 #define DMA_HRS_HRS2_SHIFT 2
993 #define DMA_HRS_HRS3_MASK 0x8u
994 #define DMA_HRS_HRS3_SHIFT 3
995 /* DCHPRI3 Bit Fields */
996 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
997 #define DMA_DCHPRI3_CHPRI_SHIFT 0
998 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
999 #define DMA_DCHPRI3_DPA_MASK 0x40u
1000 #define DMA_DCHPRI3_DPA_SHIFT 6
1001 #define DMA_DCHPRI3_ECP_MASK 0x80u
1002 #define DMA_DCHPRI3_ECP_SHIFT 7
1003 /* DCHPRI2 Bit Fields */
1004 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
1005 #define DMA_DCHPRI2_CHPRI_SHIFT 0
1006 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
1007 #define DMA_DCHPRI2_DPA_MASK 0x40u
1008 #define DMA_DCHPRI2_DPA_SHIFT 6
1009 #define DMA_DCHPRI2_ECP_MASK 0x80u
1010 #define DMA_DCHPRI2_ECP_SHIFT 7
1011 /* DCHPRI1 Bit Fields */
1012 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
1013 #define DMA_DCHPRI1_CHPRI_SHIFT 0
1014 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
1015 #define DMA_DCHPRI1_DPA_MASK 0x40u
1016 #define DMA_DCHPRI1_DPA_SHIFT 6
1017 #define DMA_DCHPRI1_ECP_MASK 0x80u
1018 #define DMA_DCHPRI1_ECP_SHIFT 7
1019 /* DCHPRI0 Bit Fields */
1020 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
1021 #define DMA_DCHPRI0_CHPRI_SHIFT 0
1022 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
1023 #define DMA_DCHPRI0_DPA_MASK 0x40u
1024 #define DMA_DCHPRI0_DPA_SHIFT 6
1025 #define DMA_DCHPRI0_ECP_MASK 0x80u
1026 #define DMA_DCHPRI0_ECP_SHIFT 7
1027 /* SADDR Bit Fields */
1028 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
1029 #define DMA_SADDR_SADDR_SHIFT 0
1030 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
1031 /* SOFF Bit Fields */
1032 #define DMA_SOFF_SOFF_MASK 0xFFFFu
1033 #define DMA_SOFF_SOFF_SHIFT 0
1034 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
1035 /* ATTR Bit Fields */
1036 #define DMA_ATTR_DSIZE_MASK 0x7u
1037 #define DMA_ATTR_DSIZE_SHIFT 0
1038 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
1039 #define DMA_ATTR_DMOD_MASK 0xF8u
1040 #define DMA_ATTR_DMOD_SHIFT 3
1041 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
1042 #define DMA_ATTR_SSIZE_MASK 0x700u
1043 #define DMA_ATTR_SSIZE_SHIFT 8
1044 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
1045 #define DMA_ATTR_SMOD_MASK 0xF800u
1046 #define DMA_ATTR_SMOD_SHIFT 11
1047 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
1048 /* NBYTES_MLNO Bit Fields */
1049 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
1050 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
1051 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
1052 /* NBYTES_MLOFFNO Bit Fields */
1053 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
1054 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
1055 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
1056 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
1057 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
1058 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
1059 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
1060 /* NBYTES_MLOFFYES Bit Fields */
1061 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
1062 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
1063 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
1064 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
1065 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
1066 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
1067 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
1068 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
1069 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
1070 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
1071 /* SLAST Bit Fields */
1072 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
1073 #define DMA_SLAST_SLAST_SHIFT 0
1074 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
1075 /* DADDR Bit Fields */
1076 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
1077 #define DMA_DADDR_DADDR_SHIFT 0
1078 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
1079 /* DOFF Bit Fields */
1080 #define DMA_DOFF_DOFF_MASK 0xFFFFu
1081 #define DMA_DOFF_DOFF_SHIFT 0
1082 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
1083 /* CITER_ELINKNO Bit Fields */
1084 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
1085 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
1086 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
1087 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
1088 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
1089 /* CITER_ELINKYES Bit Fields */
1090 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
1091 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
1092 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
1093 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
1094 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
1095 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
1096 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
1097 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
1098 /* DLAST_SGA Bit Fields */
1099 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
1100 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
1101 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
1102 /* CSR Bit Fields */
1103 #define DMA_CSR_START_MASK 0x1u
1104 #define DMA_CSR_START_SHIFT 0
1105 #define DMA_CSR_INTMAJOR_MASK 0x2u
1106 #define DMA_CSR_INTMAJOR_SHIFT 1
1107 #define DMA_CSR_INTHALF_MASK 0x4u
1108 #define DMA_CSR_INTHALF_SHIFT 2
1109 #define DMA_CSR_DREQ_MASK 0x8u
1110 #define DMA_CSR_DREQ_SHIFT 3
1111 #define DMA_CSR_ESG_MASK 0x10u
1112 #define DMA_CSR_ESG_SHIFT 4
1113 #define DMA_CSR_MAJORELINK_MASK 0x20u
1114 #define DMA_CSR_MAJORELINK_SHIFT 5
1115 #define DMA_CSR_ACTIVE_MASK 0x40u
1116 #define DMA_CSR_ACTIVE_SHIFT 6
1117 #define DMA_CSR_DONE_MASK 0x80u
1118 #define DMA_CSR_DONE_SHIFT 7
1119 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
1120 #define DMA_CSR_MAJORLINKCH_SHIFT 8
1121 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
1122 #define DMA_CSR_BWC_MASK 0xC000u
1123 #define DMA_CSR_BWC_SHIFT 14
1124 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
1125 /* BITER_ELINKNO Bit Fields */
1126 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
1127 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
1128 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
1129 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
1130 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
1131 /* BITER_ELINKYES Bit Fields */
1132 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
1133 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
1134 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
1135 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
1136 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
1137 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
1138 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
1139 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
1140
1141 /**
1142 * @}
1143 */ /* end of group DMA_Register_Masks */
1144
1145
1146 /* DMA - Peripheral instance base addresses */
1147 /** Peripheral DMA base address */
1148 #define DMA_BASE (0x40008000u)
1149 /** Peripheral DMA base pointer */
1150 #define DMA0 ((DMA_Type *)DMA_BASE)
1151
1152 /**
1153 * @}
1154 */ /* end of group DMA_Peripheral_Access_Layer */
1155
1156
1157 /* ----------------------------------------------------------------------------
1158 -- DMAMUX Peripheral Access Layer
1159 ---------------------------------------------------------------------------- */
1160
1161 /**
1162 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
1163 * @{
1164 */
1165
1166 /** DMAMUX - Register Layout Typedef */
1167 typedef struct {
1168 __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
1169 } DMAMUX_Type;
1170
1171 /* ----------------------------------------------------------------------------
1172 -- DMAMUX Register Masks
1173 ---------------------------------------------------------------------------- */
1174
1175 /**
1176 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
1177 * @{
1178 */
1179
1180 /* CHCFG Bit Fields */
1181 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
1182 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
1183 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
1184 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
1185 #define DMAMUX_CHCFG_TRIG_SHIFT 6
1186 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
1187 #define DMAMUX_CHCFG_ENBL_SHIFT 7
1188
1189 /**
1190 * @}
1191 */ /* end of group DMAMUX_Register_Masks */
1192
1193
1194 /* DMAMUX - Peripheral instance base addresses */
1195 /** Peripheral DMAMUX base address */
1196 #define DMAMUX_BASE (0x40021000u)
1197 /** Peripheral DMAMUX base pointer */
1198 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
1199
1200 /**
1201 * @}
1202 */ /* end of group DMAMUX_Peripheral_Access_Layer */
1203
1204
1205 /* ----------------------------------------------------------------------------
1206 -- EWM Peripheral Access Layer
1207 ---------------------------------------------------------------------------- */
1208
1209 /**
1210 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
1211 * @{
1212 */
1213
1214 /** EWM - Register Layout Typedef */
1215 typedef struct {
1216 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
1217 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
1218 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
1219 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
1220 } EWM_Type;
1221
1222 /* ----------------------------------------------------------------------------
1223 -- EWM Register Masks
1224 ---------------------------------------------------------------------------- */
1225
1226 /**
1227 * @addtogroup EWM_Register_Masks EWM Register Masks
1228 * @{
1229 */
1230
1231 /* CTRL Bit Fields */
1232 #define EWM_CTRL_EWMEN_MASK 0x1u
1233 #define EWM_CTRL_EWMEN_SHIFT 0
1234 #define EWM_CTRL_ASSIN_MASK 0x2u
1235 #define EWM_CTRL_ASSIN_SHIFT 1
1236 #define EWM_CTRL_INEN_MASK 0x4u
1237 #define EWM_CTRL_INEN_SHIFT 2
1238 #define EWM_CTRL_INTEN_MASK 0x8u
1239 #define EWM_CTRL_INTEN_SHIFT 3
1240 /* SERV Bit Fields */
1241 #define EWM_SERV_SERVICE_MASK 0xFFu
1242 #define EWM_SERV_SERVICE_SHIFT 0
1243 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
1244 /* CMPL Bit Fields */
1245 #define EWM_CMPL_COMPAREL_MASK 0xFFu
1246 #define EWM_CMPL_COMPAREL_SHIFT 0
1247 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
1248 /* CMPH Bit Fields */
1249 #define EWM_CMPH_COMPAREH_MASK 0xFFu
1250 #define EWM_CMPH_COMPAREH_SHIFT 0
1251 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
1252
1253 /**
1254 * @}
1255 */ /* end of group EWM_Register_Masks */
1256
1257
1258 /* EWM - Peripheral instance base addresses */
1259 /** Peripheral EWM base address */
1260 #define EWM_BASE (0x40061000u)
1261 /** Peripheral EWM base pointer */
1262 #define EWM ((EWM_Type *)EWM_BASE)
1263
1264 /**
1265 * @}
1266 */ /* end of group EWM_Peripheral_Access_Layer */
1267
1268
1269 /* ----------------------------------------------------------------------------
1270 -- FMC Peripheral Access Layer
1271 ---------------------------------------------------------------------------- */
1272
1273 /**
1274 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
1275 * @{
1276 */
1277
1278 /** FMC - Register Layout Typedef */
1279 typedef struct {
1280 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
1281 __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
1282 uint8_t RESERVED_0[248];
1283 struct { /* offset: 0x100, array step: 0x20 */
1284 __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
1285 uint8_t RESERVED_0[24];
1286 } TAG_WAY[4];
1287 uint8_t RESERVED_1[132];
1288 struct { /* offset: 0x204, array step: 0x8 */
1289 __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
1290 uint8_t RESERVED_0[4];
1291 } DATAW0S[2];
1292 uint8_t RESERVED_2[48];
1293 struct { /* offset: 0x244, array step: 0x8 */
1294 __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
1295 uint8_t RESERVED_0[4];
1296 } DATAW1S[2];
1297 uint8_t RESERVED_3[48];
1298 struct { /* offset: 0x284, array step: 0x8 */
1299 __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
1300 uint8_t RESERVED_0[4];
1301 } DATAW2S[2];
1302 uint8_t RESERVED_4[48];
1303 struct { /* offset: 0x2C4, array step: 0x8 */
1304 __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
1305 uint8_t RESERVED_0[4];
1306 } DATAW3S[2];
1307 } FMC_Type;
1308
1309 /* ----------------------------------------------------------------------------
1310 -- FMC Register Masks
1311 ---------------------------------------------------------------------------- */
1312
1313 /**
1314 * @addtogroup FMC_Register_Masks FMC Register Masks
1315 * @{
1316 */
1317
1318 /* PFAPR Bit Fields */
1319 #define FMC_PFAPR_M0AP_MASK 0x3u
1320 #define FMC_PFAPR_M0AP_SHIFT 0
1321 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
1322 #define FMC_PFAPR_M1AP_MASK 0xCu
1323 #define FMC_PFAPR_M1AP_SHIFT 2
1324 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
1325 #define FMC_PFAPR_M2AP_MASK 0x30u
1326 #define FMC_PFAPR_M2AP_SHIFT 4
1327 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
1328 #define FMC_PFAPR_M3AP_MASK 0xC0u
1329 #define FMC_PFAPR_M3AP_SHIFT 6
1330 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
1331 #define FMC_PFAPR_M0PFD_MASK 0x10000u
1332 #define FMC_PFAPR_M0PFD_SHIFT 16
1333 #define FMC_PFAPR_M1PFD_MASK 0x20000u
1334 #define FMC_PFAPR_M1PFD_SHIFT 17
1335 #define FMC_PFAPR_M2PFD_MASK 0x40000u
1336 #define FMC_PFAPR_M2PFD_SHIFT 18
1337 #define FMC_PFAPR_M3PFD_MASK 0x80000u
1338 #define FMC_PFAPR_M3PFD_SHIFT 19
1339 /* PFB0CR Bit Fields */
1340 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
1341 #define FMC_PFB0CR_B0SEBE_SHIFT 0
1342 #define FMC_PFB0CR_B0IPE_MASK 0x2u
1343 #define FMC_PFB0CR_B0IPE_SHIFT 1
1344 #define FMC_PFB0CR_B0DPE_MASK 0x4u
1345 #define FMC_PFB0CR_B0DPE_SHIFT 2
1346 #define FMC_PFB0CR_B0ICE_MASK 0x8u
1347 #define FMC_PFB0CR_B0ICE_SHIFT 3
1348 #define FMC_PFB0CR_B0DCE_MASK 0x10u
1349 #define FMC_PFB0CR_B0DCE_SHIFT 4
1350 #define FMC_PFB0CR_CRC_MASK 0xE0u
1351 #define FMC_PFB0CR_CRC_SHIFT 5
1352 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
1353 #define FMC_PFB0CR_B0MW_MASK 0x60000u
1354 #define FMC_PFB0CR_B0MW_SHIFT 17
1355 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
1356 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
1357 #define FMC_PFB0CR_S_B_INV_SHIFT 19
1358 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
1359 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
1360 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
1361 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
1362 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
1363 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
1364 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
1365 #define FMC_PFB0CR_B0RWSC_SHIFT 28
1366 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
1367 /* TAGVD Bit Fields */
1368 #define FMC_TAGVD_valid_MASK 0x1u
1369 #define FMC_TAGVD_valid_SHIFT 0
1370 #define FMC_TAGVD_tag_MASK 0x7FFC0u
1371 #define FMC_TAGVD_tag_SHIFT 6
1372 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
1373 /* DATAW0S Bit Fields */
1374 #define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
1375 #define FMC_DATAW0S_data_SHIFT 0
1376 #define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
1377 /* DATAW1S Bit Fields */
1378 #define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
1379 #define FMC_DATAW1S_data_SHIFT 0
1380 #define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
1381 /* DATAW2S Bit Fields */
1382 #define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
1383 #define FMC_DATAW2S_data_SHIFT 0
1384 #define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
1385 /* DATAW3S Bit Fields */
1386 #define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
1387 #define FMC_DATAW3S_data_SHIFT 0
1388 #define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
1389
1390 /**
1391 * @}
1392 */ /* end of group FMC_Register_Masks */
1393
1394
1395 /* FMC - Peripheral instance base addresses */
1396 /** Peripheral FMC base address */
1397 #define FMC_BASE (0x4001F000u)
1398 /** Peripheral FMC base pointer */
1399 #define FMC ((FMC_Type *)FMC_BASE)
1400
1401 /**
1402 * @}
1403 */ /* end of group FMC_Peripheral_Access_Layer */
1404
1405
1406 /* ----------------------------------------------------------------------------
1407 -- FTFL Peripheral Access Layer
1408 ---------------------------------------------------------------------------- */
1409
1410 /**
1411 * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
1412 * @{
1413 */
1414
1415 /** FTFL - Register Layout Typedef */
1416 typedef struct {
1417 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
1418 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
1419 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
1420 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
1421 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
1422 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
1423 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
1424 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
1425 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
1426 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
1427 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
1428 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
1429 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
1430 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
1431 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
1432 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
1433 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
1434 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
1435 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
1436 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
1437 uint8_t RESERVED_0[2];
1438 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
1439 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
1440 } FTFL_Type;
1441
1442 /* ----------------------------------------------------------------------------
1443 -- FTFL Register Masks
1444 ---------------------------------------------------------------------------- */
1445
1446 /**
1447 * @addtogroup FTFL_Register_Masks FTFL Register Masks
1448 * @{
1449 */
1450
1451 /* FSTAT Bit Fields */
1452 #define FTFL_FSTAT_MGSTAT0_MASK 0x1u
1453 #define FTFL_FSTAT_MGSTAT0_SHIFT 0
1454 #define FTFL_FSTAT_FPVIOL_MASK 0x10u
1455 #define FTFL_FSTAT_FPVIOL_SHIFT 4
1456 #define FTFL_FSTAT_ACCERR_MASK 0x20u
1457 #define FTFL_FSTAT_ACCERR_SHIFT 5
1458 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u
1459 #define FTFL_FSTAT_RDCOLERR_SHIFT 6
1460 #define FTFL_FSTAT_CCIF_MASK 0x80u
1461 #define FTFL_FSTAT_CCIF_SHIFT 7
1462 /* FCNFG Bit Fields */
1463 #define FTFL_FCNFG_EEERDY_MASK 0x1u
1464 #define FTFL_FCNFG_EEERDY_SHIFT 0
1465 #define FTFL_FCNFG_RAMRDY_MASK 0x2u
1466 #define FTFL_FCNFG_RAMRDY_SHIFT 1
1467 #define FTFL_FCNFG_PFLSH_MASK 0x4u
1468 #define FTFL_FCNFG_PFLSH_SHIFT 2
1469 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u
1470 #define FTFL_FCNFG_ERSSUSP_SHIFT 4
1471 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u
1472 #define FTFL_FCNFG_ERSAREQ_SHIFT 5
1473 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
1474 #define FTFL_FCNFG_RDCOLLIE_SHIFT 6
1475 #define FTFL_FCNFG_CCIE_MASK 0x80u
1476 #define FTFL_FCNFG_CCIE_SHIFT 7
1477 /* FSEC Bit Fields */
1478 #define FTFL_FSEC_SEC_MASK 0x3u
1479 #define FTFL_FSEC_SEC_SHIFT 0
1480 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
1481 #define FTFL_FSEC_FSLACC_MASK 0xCu
1482 #define FTFL_FSEC_FSLACC_SHIFT 2
1483 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
1484 #define FTFL_FSEC_MEEN_MASK 0x30u
1485 #define FTFL_FSEC_MEEN_SHIFT 4
1486 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
1487 #define FTFL_FSEC_KEYEN_MASK 0xC0u
1488 #define FTFL_FSEC_KEYEN_SHIFT 6
1489 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
1490 /* FOPT Bit Fields */
1491 #define FTFL_FOPT_OPT_MASK 0xFFu
1492 #define FTFL_FOPT_OPT_SHIFT 0
1493 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
1494 /* FCCOB3 Bit Fields */
1495 #define FTFL_FCCOB3_CCOBn_MASK 0xFFu
1496 #define FTFL_FCCOB3_CCOBn_SHIFT 0
1497 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
1498 /* FCCOB2 Bit Fields */
1499 #define FTFL_FCCOB2_CCOBn_MASK 0xFFu
1500 #define FTFL_FCCOB2_CCOBn_SHIFT 0
1501 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
1502 /* FCCOB1 Bit Fields */
1503 #define FTFL_FCCOB1_CCOBn_MASK 0xFFu
1504 #define FTFL_FCCOB1_CCOBn_SHIFT 0
1505 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
1506 /* FCCOB0 Bit Fields */
1507 #define FTFL_FCCOB0_CCOBn_MASK 0xFFu
1508 #define FTFL_FCCOB0_CCOBn_SHIFT 0
1509 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
1510 /* FCCOB7 Bit Fields */
1511 #define FTFL_FCCOB7_CCOBn_MASK 0xFFu
1512 #define FTFL_FCCOB7_CCOBn_SHIFT 0
1513 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
1514 /* FCCOB6 Bit Fields */
1515 #define FTFL_FCCOB6_CCOBn_MASK 0xFFu
1516 #define FTFL_FCCOB6_CCOBn_SHIFT 0
1517 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
1518 /* FCCOB5 Bit Fields */
1519 #define FTFL_FCCOB5_CCOBn_MASK 0xFFu
1520 #define FTFL_FCCOB5_CCOBn_SHIFT 0
1521 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
1522 /* FCCOB4 Bit Fields */
1523 #define FTFL_FCCOB4_CCOBn_MASK 0xFFu
1524 #define FTFL_FCCOB4_CCOBn_SHIFT 0
1525 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
1526 /* FCCOBB Bit Fields */
1527 #define FTFL_FCCOBB_CCOBn_MASK 0xFFu
1528 #define FTFL_FCCOBB_CCOBn_SHIFT 0
1529 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
1530 /* FCCOBA Bit Fields */
1531 #define FTFL_FCCOBA_CCOBn_MASK 0xFFu
1532 #define FTFL_FCCOBA_CCOBn_SHIFT 0
1533 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
1534 /* FCCOB9 Bit Fields */
1535 #define FTFL_FCCOB9_CCOBn_MASK 0xFFu
1536 #define FTFL_FCCOB9_CCOBn_SHIFT 0
1537 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
1538 /* FCCOB8 Bit Fields */
1539 #define FTFL_FCCOB8_CCOBn_MASK 0xFFu
1540 #define FTFL_FCCOB8_CCOBn_SHIFT 0
1541 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
1542 /* FPROT3 Bit Fields */
1543 #define FTFL_FPROT3_PROT_MASK 0xFFu
1544 #define FTFL_FPROT3_PROT_SHIFT 0
1545 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
1546 /* FPROT2 Bit Fields */
1547 #define FTFL_FPROT2_PROT_MASK 0xFFu
1548 #define FTFL_FPROT2_PROT_SHIFT 0
1549 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
1550 /* FPROT1 Bit Fields */
1551 #define FTFL_FPROT1_PROT_MASK 0xFFu
1552 #define FTFL_FPROT1_PROT_SHIFT 0
1553 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
1554 /* FPROT0 Bit Fields */
1555 #define FTFL_FPROT0_PROT_MASK 0xFFu
1556 #define FTFL_FPROT0_PROT_SHIFT 0
1557 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
1558 /* FEPROT Bit Fields */
1559 #define FTFL_FEPROT_EPROT_MASK 0xFFu
1560 #define FTFL_FEPROT_EPROT_SHIFT 0
1561 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
1562 /* FDPROT Bit Fields */
1563 #define FTFL_FDPROT_DPROT_MASK 0xFFu
1564 #define FTFL_FDPROT_DPROT_SHIFT 0
1565 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
1566
1567 /**
1568 * @}
1569 */ /* end of group FTFL_Register_Masks */
1570
1571
1572 /* FTFL - Peripheral instance base addresses */
1573 /** Peripheral FTFL base address */
1574 #define FTFL_BASE (0x40020000u)
1575 /** Peripheral FTFL base pointer */
1576 #define FTFL ((FTFL_Type *)FTFL_BASE)
1577
1578 /**
1579 * @}
1580 */ /* end of group FTFL_Peripheral_Access_Layer */
1581
1582
1583 /* ----------------------------------------------------------------------------
1584 -- FTM Peripheral Access Layer
1585 ---------------------------------------------------------------------------- */
1586
1587 /**
1588 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
1589 * @{
1590 */
1591
1592 /** FTM - Register Layout Typedef */
1593 typedef struct {
1594 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
1595 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
1596 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
1597 struct { /* offset: 0xC, array step: 0x8 */
1598 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
1599 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
1600 } CONTROLS[8];
1601 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
1602 __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
1603 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
1604 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
1605 __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
1606 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
1607 __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
1608 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
1609 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
1610 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
1611 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
1612 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
1613 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
1614 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
1615 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
1616 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
1617 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
1618 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
1619 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
1620 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
1621 } FTM_Type;
1622
1623 /* ----------------------------------------------------------------------------
1624 -- FTM Register Masks
1625 ---------------------------------------------------------------------------- */
1626
1627 /**
1628 * @addtogroup FTM_Register_Masks FTM Register Masks
1629 * @{
1630 */
1631
1632 /* SC Bit Fields */
1633 #define FTM_SC_PS_MASK 0x7u
1634 #define FTM_SC_PS_SHIFT 0
1635 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
1636 #define FTM_SC_CLKS_MASK 0x18u
1637 #define FTM_SC_CLKS_SHIFT 3
1638 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
1639 #define FTM_SC_CPWMS_MASK 0x20u
1640 #define FTM_SC_CPWMS_SHIFT 5
1641 #define FTM_SC_TOIE_MASK 0x40u
1642 #define FTM_SC_TOIE_SHIFT 6
1643 #define FTM_SC_TOF_MASK 0x80u
1644 #define FTM_SC_TOF_SHIFT 7
1645 /* CNT Bit Fields */
1646 #define FTM_CNT_COUNT_MASK 0xFFFFu
1647 #define FTM_CNT_COUNT_SHIFT 0
1648 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
1649 /* MOD Bit Fields */
1650 #define FTM_MOD_MOD_MASK 0xFFFFu
1651 #define FTM_MOD_MOD_SHIFT 0
1652 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
1653 /* CnSC Bit Fields */
1654 #define FTM_CnSC_DMA_MASK 0x1u
1655 #define FTM_CnSC_DMA_SHIFT 0
1656 #define FTM_CnSC_ELSA_MASK 0x4u
1657 #define FTM_CnSC_ELSA_SHIFT 2
1658 #define FTM_CnSC_ELSB_MASK 0x8u
1659 #define FTM_CnSC_ELSB_SHIFT 3
1660 #define FTM_CnSC_MSA_MASK 0x10u
1661 #define FTM_CnSC_MSA_SHIFT 4
1662 #define FTM_CnSC_MSB_MASK 0x20u
1663 #define FTM_CnSC_MSB_SHIFT 5
1664 #define FTM_CnSC_CHIE_MASK 0x40u
1665 #define FTM_CnSC_CHIE_SHIFT 6
1666 #define FTM_CnSC_CHF_MASK 0x80u
1667 #define FTM_CnSC_CHF_SHIFT 7
1668 /* CnV Bit Fields */
1669 #define FTM_CnV_VAL_MASK 0xFFFFu
1670 #define FTM_CnV_VAL_SHIFT 0
1671 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
1672 /* CNTIN Bit Fields */
1673 #define FTM_CNTIN_INIT_MASK 0xFFFFu
1674 #define FTM_CNTIN_INIT_SHIFT 0
1675 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
1676 /* STATUS Bit Fields */
1677 #define FTM_STATUS_CH0F_MASK 0x1u
1678 #define FTM_STATUS_CH0F_SHIFT 0
1679 #define FTM_STATUS_CH1F_MASK 0x2u
1680 #define FTM_STATUS_CH1F_SHIFT 1
1681 #define FTM_STATUS_CH2F_MASK 0x4u
1682 #define FTM_STATUS_CH2F_SHIFT 2
1683 #define FTM_STATUS_CH3F_MASK 0x8u
1684 #define FTM_STATUS_CH3F_SHIFT 3
1685 #define FTM_STATUS_CH4F_MASK 0x10u
1686 #define FTM_STATUS_CH4F_SHIFT 4
1687 #define FTM_STATUS_CH5F_MASK 0x20u
1688 #define FTM_STATUS_CH5F_SHIFT 5
1689 #define FTM_STATUS_CH6F_MASK 0x40u
1690 #define FTM_STATUS_CH6F_SHIFT 6
1691 #define FTM_STATUS_CH7F_MASK 0x80u
1692 #define FTM_STATUS_CH7F_SHIFT 7
1693 /* MODE Bit Fields */
1694 #define FTM_MODE_FTMEN_MASK 0x1u
1695 #define FTM_MODE_FTMEN_SHIFT 0
1696 #define FTM_MODE_INIT_MASK 0x2u
1697 #define FTM_MODE_INIT_SHIFT 1
1698 #define FTM_MODE_WPDIS_MASK 0x4u
1699 #define FTM_MODE_WPDIS_SHIFT 2
1700 #define FTM_MODE_PWMSYNC_MASK 0x8u
1701 #define FTM_MODE_PWMSYNC_SHIFT 3
1702 #define FTM_MODE_CAPTEST_MASK 0x10u
1703 #define FTM_MODE_CAPTEST_SHIFT 4
1704 #define FTM_MODE_FAULTM_MASK 0x60u
1705 #define FTM_MODE_FAULTM_SHIFT 5
1706 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
1707 #define FTM_MODE_FAULTIE_MASK 0x80u
1708 #define FTM_MODE_FAULTIE_SHIFT 7
1709 /* SYNC Bit Fields */
1710 #define FTM_SYNC_CNTMIN_MASK 0x1u
1711 #define FTM_SYNC_CNTMIN_SHIFT 0
1712 #define FTM_SYNC_CNTMAX_MASK 0x2u
1713 #define FTM_SYNC_CNTMAX_SHIFT 1
1714 #define FTM_SYNC_REINIT_MASK 0x4u
1715 #define FTM_SYNC_REINIT_SHIFT 2
1716 #define FTM_SYNC_SYNCHOM_MASK 0x8u
1717 #define FTM_SYNC_SYNCHOM_SHIFT 3
1718 #define FTM_SYNC_TRIG0_MASK 0x10u
1719 #define FTM_SYNC_TRIG0_SHIFT 4
1720 #define FTM_SYNC_TRIG1_MASK 0x20u
1721 #define FTM_SYNC_TRIG1_SHIFT 5
1722 #define FTM_SYNC_TRIG2_MASK 0x40u
1723 #define FTM_SYNC_TRIG2_SHIFT 6
1724 #define FTM_SYNC_SWSYNC_MASK 0x80u
1725 #define FTM_SYNC_SWSYNC_SHIFT 7
1726 /* OUTINIT Bit Fields */
1727 #define FTM_OUTINIT_CH0OI_MASK 0x1u
1728 #define FTM_OUTINIT_CH0OI_SHIFT 0
1729 #define FTM_OUTINIT_CH1OI_MASK 0x2u
1730 #define FTM_OUTINIT_CH1OI_SHIFT 1
1731 #define FTM_OUTINIT_CH2OI_MASK 0x4u
1732 #define FTM_OUTINIT_CH2OI_SHIFT 2
1733 #define FTM_OUTINIT_CH3OI_MASK 0x8u
1734 #define FTM_OUTINIT_CH3OI_SHIFT 3
1735 #define FTM_OUTINIT_CH4OI_MASK 0x10u
1736 #define FTM_OUTINIT_CH4OI_SHIFT 4
1737 #define FTM_OUTINIT_CH5OI_MASK 0x20u
1738 #define FTM_OUTINIT_CH5OI_SHIFT 5
1739 #define FTM_OUTINIT_CH6OI_MASK 0x40u
1740 #define FTM_OUTINIT_CH6OI_SHIFT 6
1741 #define FTM_OUTINIT_CH7OI_MASK 0x80u
1742 #define FTM_OUTINIT_CH7OI_SHIFT 7
1743 /* OUTMASK Bit Fields */
1744 #define FTM_OUTMASK_CH0OM_MASK 0x1u
1745 #define FTM_OUTMASK_CH0OM_SHIFT 0
1746 #define FTM_OUTMASK_CH1OM_MASK 0x2u
1747 #define FTM_OUTMASK_CH1OM_SHIFT 1
1748 #define FTM_OUTMASK_CH2OM_MASK 0x4u
1749 #define FTM_OUTMASK_CH2OM_SHIFT 2
1750 #define FTM_OUTMASK_CH3OM_MASK 0x8u
1751 #define FTM_OUTMASK_CH3OM_SHIFT 3
1752 #define FTM_OUTMASK_CH4OM_MASK 0x10u
1753 #define FTM_OUTMASK_CH4OM_SHIFT 4
1754 #define FTM_OUTMASK_CH5OM_MASK 0x20u
1755 #define FTM_OUTMASK_CH5OM_SHIFT 5
1756 #define FTM_OUTMASK_CH6OM_MASK 0x40u
1757 #define FTM_OUTMASK_CH6OM_SHIFT 6
1758 #define FTM_OUTMASK_CH7OM_MASK 0x80u
1759 #define FTM_OUTMASK_CH7OM_SHIFT 7
1760 /* COMBINE Bit Fields */
1761 #define FTM_COMBINE_COMBINE0_MASK 0x1u
1762 #define FTM_COMBINE_COMBINE0_SHIFT 0
1763 #define FTM_COMBINE_COMP0_MASK 0x2u
1764 #define FTM_COMBINE_COMP0_SHIFT 1
1765 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
1766 #define FTM_COMBINE_DECAPEN0_SHIFT 2
1767 #define FTM_COMBINE_DECAP0_MASK 0x8u
1768 #define FTM_COMBINE_DECAP0_SHIFT 3
1769 #define FTM_COMBINE_DTEN0_MASK 0x10u
1770 #define FTM_COMBINE_DTEN0_SHIFT 4
1771 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
1772 #define FTM_COMBINE_SYNCEN0_SHIFT 5
1773 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
1774 #define FTM_COMBINE_FAULTEN0_SHIFT 6
1775 #define FTM_COMBINE_COMBINE1_MASK 0x100u
1776 #define FTM_COMBINE_COMBINE1_SHIFT 8
1777 #define FTM_COMBINE_COMP1_MASK 0x200u
1778 #define FTM_COMBINE_COMP1_SHIFT 9
1779 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
1780 #define FTM_COMBINE_DECAPEN1_SHIFT 10
1781 #define FTM_COMBINE_DECAP1_MASK 0x800u
1782 #define FTM_COMBINE_DECAP1_SHIFT 11
1783 #define FTM_COMBINE_DTEN1_MASK 0x1000u
1784 #define FTM_COMBINE_DTEN1_SHIFT 12
1785 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
1786 #define FTM_COMBINE_SYNCEN1_SHIFT 13
1787 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
1788 #define FTM_COMBINE_FAULTEN1_SHIFT 14
1789 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
1790 #define FTM_COMBINE_COMBINE2_SHIFT 16
1791 #define FTM_COMBINE_COMP2_MASK 0x20000u
1792 #define FTM_COMBINE_COMP2_SHIFT 17
1793 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
1794 #define FTM_COMBINE_DECAPEN2_SHIFT 18
1795 #define FTM_COMBINE_DECAP2_MASK 0x80000u
1796 #define FTM_COMBINE_DECAP2_SHIFT 19
1797 #define FTM_COMBINE_DTEN2_MASK 0x100000u
1798 #define FTM_COMBINE_DTEN2_SHIFT 20
1799 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
1800 #define FTM_COMBINE_SYNCEN2_SHIFT 21
1801 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
1802 #define FTM_COMBINE_FAULTEN2_SHIFT 22
1803 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
1804 #define FTM_COMBINE_COMBINE3_SHIFT 24
1805 #define FTM_COMBINE_COMP3_MASK 0x2000000u
1806 #define FTM_COMBINE_COMP3_SHIFT 25
1807 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
1808 #define FTM_COMBINE_DECAPEN3_SHIFT 26
1809 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
1810 #define FTM_COMBINE_DECAP3_SHIFT 27
1811 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
1812 #define FTM_COMBINE_DTEN3_SHIFT 28
1813 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
1814 #define FTM_COMBINE_SYNCEN3_SHIFT 29
1815 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
1816 #define FTM_COMBINE_FAULTEN3_SHIFT 30
1817 /* DEADTIME Bit Fields */
1818 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
1819 #define FTM_DEADTIME_DTVAL_SHIFT 0
1820 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
1821 #define FTM_DEADTIME_DTPS_MASK 0xC0u
1822 #define FTM_DEADTIME_DTPS_SHIFT 6
1823 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
1824 /* EXTTRIG Bit Fields */
1825 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
1826 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
1827 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
1828 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
1829 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
1830 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
1831 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
1832 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
1833 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
1834 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
1835 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
1836 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
1837 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
1838 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
1839 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
1840 #define FTM_EXTTRIG_TRIGF_SHIFT 7
1841 /* POL Bit Fields */
1842 #define FTM_POL_POL0_MASK 0x1u
1843 #define FTM_POL_POL0_SHIFT 0
1844 #define FTM_POL_POL1_MASK 0x2u
1845 #define FTM_POL_POL1_SHIFT 1
1846 #define FTM_POL_POL2_MASK 0x4u
1847 #define FTM_POL_POL2_SHIFT 2
1848 #define FTM_POL_POL3_MASK 0x8u
1849 #define FTM_POL_POL3_SHIFT 3
1850 #define FTM_POL_POL4_MASK 0x10u
1851 #define FTM_POL_POL4_SHIFT 4
1852 #define FTM_POL_POL5_MASK 0x20u
1853 #define FTM_POL_POL5_SHIFT 5
1854 #define FTM_POL_POL6_MASK 0x40u
1855 #define FTM_POL_POL6_SHIFT 6
1856 #define FTM_POL_POL7_MASK 0x80u
1857 #define FTM_POL_POL7_SHIFT 7
1858 /* FMS Bit Fields */
1859 #define FTM_FMS_FAULTF0_MASK 0x1u
1860 #define FTM_FMS_FAULTF0_SHIFT 0
1861 #define FTM_FMS_FAULTF1_MASK 0x2u
1862 #define FTM_FMS_FAULTF1_SHIFT 1
1863 #define FTM_FMS_FAULTF2_MASK 0x4u
1864 #define FTM_FMS_FAULTF2_SHIFT 2
1865 #define FTM_FMS_FAULTF3_MASK 0x8u
1866 #define FTM_FMS_FAULTF3_SHIFT 3
1867 #define FTM_FMS_FAULTIN_MASK 0x20u
1868 #define FTM_FMS_FAULTIN_SHIFT 5
1869 #define FTM_FMS_WPEN_MASK 0x40u
1870 #define FTM_FMS_WPEN_SHIFT 6
1871 #define FTM_FMS_FAULTF_MASK 0x80u
1872 #define FTM_FMS_FAULTF_SHIFT 7
1873 /* FILTER Bit Fields */
1874 #define FTM_FILTER_CH0FVAL_MASK 0xFu
1875 #define FTM_FILTER_CH0FVAL_SHIFT 0
1876 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
1877 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
1878 #define FTM_FILTER_CH1FVAL_SHIFT 4
1879 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
1880 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
1881 #define FTM_FILTER_CH2FVAL_SHIFT 8
1882 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
1883 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
1884 #define FTM_FILTER_CH3FVAL_SHIFT 12
1885 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
1886 /* FLTCTRL Bit Fields */
1887 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
1888 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
1889 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
1890 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
1891 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
1892 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
1893 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
1894 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
1895 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
1896 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
1897 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
1898 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
1899 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
1900 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
1901 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
1902 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
1903 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
1904 #define FTM_FLTCTRL_FFVAL_SHIFT 8
1905 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
1906 /* QDCTRL Bit Fields */
1907 #define FTM_QDCTRL_QUADEN_MASK 0x1u
1908 #define FTM_QDCTRL_QUADEN_SHIFT 0
1909 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
1910 #define FTM_QDCTRL_TOFDIR_SHIFT 1
1911 #define FTM_QDCTRL_QUADIR_MASK 0x4u
1912 #define FTM_QDCTRL_QUADIR_SHIFT 2
1913 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
1914 #define FTM_QDCTRL_QUADMODE_SHIFT 3
1915 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
1916 #define FTM_QDCTRL_PHBPOL_SHIFT 4
1917 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
1918 #define FTM_QDCTRL_PHAPOL_SHIFT 5
1919 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
1920 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
1921 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
1922 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
1923 /* CONF Bit Fields */
1924 #define FTM_CONF_NUMTOF_MASK 0x1Fu
1925 #define FTM_CONF_NUMTOF_SHIFT 0
1926 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
1927 #define FTM_CONF_BDMMODE_MASK 0xC0u
1928 #define FTM_CONF_BDMMODE_SHIFT 6
1929 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
1930 #define FTM_CONF_GTBEEN_MASK 0x200u
1931 #define FTM_CONF_GTBEEN_SHIFT 9
1932 #define FTM_CONF_GTBEOUT_MASK 0x400u
1933 #define FTM_CONF_GTBEOUT_SHIFT 10
1934 /* FLTPOL Bit Fields */
1935 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
1936 #define FTM_FLTPOL_FLT0POL_SHIFT 0
1937 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
1938 #define FTM_FLTPOL_FLT1POL_SHIFT 1
1939 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
1940 #define FTM_FLTPOL_FLT2POL_SHIFT 2
1941 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
1942 #define FTM_FLTPOL_FLT3POL_SHIFT 3
1943 /* SYNCONF Bit Fields */
1944 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
1945 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
1946 #define FTM_SYNCONF_CNTINC_MASK 0x4u
1947 #define FTM_SYNCONF_CNTINC_SHIFT 2
1948 #define FTM_SYNCONF_INVC_MASK 0x10u
1949 #define FTM_SYNCONF_INVC_SHIFT 4
1950 #define FTM_SYNCONF_SWOC_MASK 0x20u
1951 #define FTM_SYNCONF_SWOC_SHIFT 5
1952 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
1953 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
1954 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
1955 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
1956 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
1957 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
1958 #define FTM_SYNCONF_SWOM_MASK 0x400u
1959 #define FTM_SYNCONF_SWOM_SHIFT 10
1960 #define FTM_SYNCONF_SWINVC_MASK 0x800u
1961 #define FTM_SYNCONF_SWINVC_SHIFT 11
1962 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
1963 #define FTM_SYNCONF_SWSOC_SHIFT 12
1964 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
1965 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
1966 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
1967 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
1968 #define FTM_SYNCONF_HWOM_MASK 0x40000u
1969 #define FTM_SYNCONF_HWOM_SHIFT 18
1970 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
1971 #define FTM_SYNCONF_HWINVC_SHIFT 19
1972 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
1973 #define FTM_SYNCONF_HWSOC_SHIFT 20
1974 /* INVCTRL Bit Fields */
1975 #define FTM_INVCTRL_INV0EN_MASK 0x1u
1976 #define FTM_INVCTRL_INV0EN_SHIFT 0
1977 #define FTM_INVCTRL_INV1EN_MASK 0x2u
1978 #define FTM_INVCTRL_INV1EN_SHIFT 1
1979 #define FTM_INVCTRL_INV2EN_MASK 0x4u
1980 #define FTM_INVCTRL_INV2EN_SHIFT 2
1981 #define FTM_INVCTRL_INV3EN_MASK 0x8u
1982 #define FTM_INVCTRL_INV3EN_SHIFT 3
1983 /* SWOCTRL Bit Fields */
1984 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
1985 #define FTM_SWOCTRL_CH0OC_SHIFT 0
1986 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
1987 #define FTM_SWOCTRL_CH1OC_SHIFT 1
1988 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
1989 #define FTM_SWOCTRL_CH2OC_SHIFT 2
1990 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
1991 #define FTM_SWOCTRL_CH3OC_SHIFT 3
1992 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
1993 #define FTM_SWOCTRL_CH4OC_SHIFT 4
1994 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
1995 #define FTM_SWOCTRL_CH5OC_SHIFT 5
1996 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
1997 #define FTM_SWOCTRL_CH6OC_SHIFT 6
1998 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
1999 #define FTM_SWOCTRL_CH7OC_SHIFT 7
2000 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
2001 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
2002 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
2003 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
2004 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
2005 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
2006 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
2007 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
2008 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
2009 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
2010 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
2011 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
2012 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
2013 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
2014 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
2015 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
2016 /* PWMLOAD Bit Fields */
2017 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
2018 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
2019 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
2020 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
2021 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
2022 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
2023 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
2024 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
2025 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
2026 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
2027 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
2028 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
2029 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
2030 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
2031 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
2032 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
2033 #define FTM_PWMLOAD_LDOK_MASK 0x200u
2034 #define FTM_PWMLOAD_LDOK_SHIFT 9
2035
2036 /**
2037 * @}
2038 */ /* end of group FTM_Register_Masks */
2039
2040
2041 /* FTM - Peripheral instance base addresses */
2042 /** Peripheral FTM0 base address */
2043 #define FTM0_BASE (0x40038000u)
2044 /** Peripheral FTM0 base pointer */
2045 #define FTM0 ((FTM_Type *)FTM0_BASE)
2046 /** Peripheral FTM1 base address */
2047 #define FTM1_BASE (0x40039000u)
2048 /** Peripheral FTM1 base pointer */
2049 #define FTM1 ((FTM_Type *)FTM1_BASE)
2050
2051 /**
2052 * @}
2053 */ /* end of group FTM_Peripheral_Access_Layer */
2054
2055
2056 /* ----------------------------------------------------------------------------
2057 -- GPIO Peripheral Access Layer
2058 ---------------------------------------------------------------------------- */
2059
2060 /**
2061 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
2062 * @{
2063 */
2064
2065 /** GPIO - Register Layout Typedef */
2066 typedef struct {
2067 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
2068 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
2069 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
2070 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
2071 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
2072 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
2073 } GPIO_Type;
2074
2075 /* ----------------------------------------------------------------------------
2076 -- GPIO Register Masks
2077 ---------------------------------------------------------------------------- */
2078
2079 /**
2080 * @addtogroup GPIO_Register_Masks GPIO Register Masks
2081 * @{
2082 */
2083
2084 /* PDOR Bit Fields */
2085 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
2086 #define GPIO_PDOR_PDO_SHIFT 0
2087 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
2088 /* PSOR Bit Fields */
2089 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
2090 #define GPIO_PSOR_PTSO_SHIFT 0
2091 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
2092 /* PCOR Bit Fields */
2093 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
2094 #define GPIO_PCOR_PTCO_SHIFT 0
2095 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
2096 /* PTOR Bit Fields */
2097 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
2098 #define GPIO_PTOR_PTTO_SHIFT 0
2099 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
2100 /* PDIR Bit Fields */
2101 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
2102 #define GPIO_PDIR_PDI_SHIFT 0
2103 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
2104 /* PDDR Bit Fields */
2105 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
2106 #define GPIO_PDDR_PDD_SHIFT 0
2107 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
2108
2109 /**
2110 * @}
2111 */ /* end of group GPIO_Register_Masks */
2112
2113
2114 /* GPIO - Peripheral instance base addresses */
2115 /** Peripheral PTA base address */
2116 #define PTA_BASE (0x400FF000u)
2117 /** Peripheral PTA base pointer */
2118 #define PTA ((GPIO_Type *)PTA_BASE)
2119 /** Peripheral PTB base address */
2120 #define PTB_BASE (0x400FF040u)
2121 /** Peripheral PTB base pointer */
2122 #define PTB ((GPIO_Type *)PTB_BASE)
2123 /** Peripheral PTC base address */
2124 #define PTC_BASE (0x400FF080u)
2125 /** Peripheral PTC base pointer */
2126 #define PTC ((GPIO_Type *)PTC_BASE)
2127 /** Peripheral PTD base address */
2128 #define PTD_BASE (0x400FF0C0u)
2129 /** Peripheral PTD base pointer */
2130 #define PTD ((GPIO_Type *)PTD_BASE)
2131 /** Peripheral PTE base address */
2132 #define PTE_BASE (0x400FF100u)
2133 /** Peripheral PTE base pointer */
2134 #define PTE ((GPIO_Type *)PTE_BASE)
2135
2136 /**
2137 * @}
2138 */ /* end of group GPIO_Peripheral_Access_Layer */
2139
2140
2141 /* ----------------------------------------------------------------------------
2142 -- I2C Peripheral Access Layer
2143 ---------------------------------------------------------------------------- */
2144
2145 /**
2146 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
2147 * @{
2148 */
2149
2150 /** I2C - Register Layout Typedef */
2151 typedef struct {
2152 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
2153 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
2154 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
2155 __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
2156 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
2157 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
2158 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
2159 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
2160 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
2161 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
2162 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
2163 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
2164 } I2C_Type;
2165
2166 /* ----------------------------------------------------------------------------
2167 -- I2C Register Masks
2168 ---------------------------------------------------------------------------- */
2169
2170 /**
2171 * @addtogroup I2C_Register_Masks I2C Register Masks
2172 * @{
2173 */
2174
2175 /* A1 Bit Fields */
2176 #define I2C_A1_AD_MASK 0xFEu
2177 #define I2C_A1_AD_SHIFT 1
2178 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
2179 /* F Bit Fields */
2180 #define I2C_F_ICR_MASK 0x3Fu
2181 #define I2C_F_ICR_SHIFT 0
2182 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
2183 #define I2C_F_MULT_MASK 0xC0u
2184 #define I2C_F_MULT_SHIFT 6
2185 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
2186 /* C1 Bit Fields */
2187 #define I2C_C1_DMAEN_MASK 0x1u
2188 #define I2C_C1_DMAEN_SHIFT 0
2189 #define I2C_C1_WUEN_MASK 0x2u
2190 #define I2C_C1_WUEN_SHIFT 1
2191 #define I2C_C1_RSTA_MASK 0x4u
2192 #define I2C_C1_RSTA_SHIFT 2
2193 #define I2C_C1_TXAK_MASK 0x8u
2194 #define I2C_C1_TXAK_SHIFT 3
2195 #define I2C_C1_TX_MASK 0x10u
2196 #define I2C_C1_TX_SHIFT 4
2197 #define I2C_C1_MST_MASK 0x20u
2198 #define I2C_C1_MST_SHIFT 5
2199 #define I2C_C1_IICIE_MASK 0x40u
2200 #define I2C_C1_IICIE_SHIFT 6
2201 #define I2C_C1_IICEN_MASK 0x80u
2202 #define I2C_C1_IICEN_SHIFT 7
2203 /* S Bit Fields */
2204 #define I2C_S_RXAK_MASK 0x1u
2205 #define I2C_S_RXAK_SHIFT 0
2206 #define I2C_S_IICIF_MASK 0x2u
2207 #define I2C_S_IICIF_SHIFT 1
2208 #define I2C_S_SRW_MASK 0x4u
2209 #define I2C_S_SRW_SHIFT 2
2210 #define I2C_S_RAM_MASK 0x8u
2211 #define I2C_S_RAM_SHIFT 3
2212 #define I2C_S_ARBL_MASK 0x10u
2213 #define I2C_S_ARBL_SHIFT 4
2214 #define I2C_S_BUSY_MASK 0x20u
2215 #define I2C_S_BUSY_SHIFT 5
2216 #define I2C_S_IAAS_MASK 0x40u
2217 #define I2C_S_IAAS_SHIFT 6
2218 #define I2C_S_TCF_MASK 0x80u
2219 #define I2C_S_TCF_SHIFT 7
2220 /* D Bit Fields */
2221 #define I2C_D_DATA_MASK 0xFFu
2222 #define I2C_D_DATA_SHIFT 0
2223 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
2224 /* C2 Bit Fields */
2225 #define I2C_C2_AD_MASK 0x7u
2226 #define I2C_C2_AD_SHIFT 0
2227 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
2228 #define I2C_C2_RMEN_MASK 0x8u
2229 #define I2C_C2_RMEN_SHIFT 3
2230 #define I2C_C2_SBRC_MASK 0x10u
2231 #define I2C_C2_SBRC_SHIFT 4
2232 #define I2C_C2_HDRS_MASK 0x20u
2233 #define I2C_C2_HDRS_SHIFT 5
2234 #define I2C_C2_ADEXT_MASK 0x40u
2235 #define I2C_C2_ADEXT_SHIFT 6
2236 #define I2C_C2_GCAEN_MASK 0x80u
2237 #define I2C_C2_GCAEN_SHIFT 7
2238 /* FLT Bit Fields */
2239 #define I2C_FLT_FLT_MASK 0x1Fu
2240 #define I2C_FLT_FLT_SHIFT 0
2241 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
2242 /* RA Bit Fields */
2243 #define I2C_RA_RAD_MASK 0xFEu
2244 #define I2C_RA_RAD_SHIFT 1
2245 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
2246 /* SMB Bit Fields */
2247 #define I2C_SMB_SHTF2IE_MASK 0x1u
2248 #define I2C_SMB_SHTF2IE_SHIFT 0
2249 #define I2C_SMB_SHTF2_MASK 0x2u
2250 #define I2C_SMB_SHTF2_SHIFT 1
2251 #define I2C_SMB_SHTF1_MASK 0x4u
2252 #define I2C_SMB_SHTF1_SHIFT 2
2253 #define I2C_SMB_SLTF_MASK 0x8u
2254 #define I2C_SMB_SLTF_SHIFT 3
2255 #define I2C_SMB_TCKSEL_MASK 0x10u
2256 #define I2C_SMB_TCKSEL_SHIFT 4
2257 #define I2C_SMB_SIICAEN_MASK 0x20u
2258 #define I2C_SMB_SIICAEN_SHIFT 5
2259 #define I2C_SMB_ALERTEN_MASK 0x40u
2260 #define I2C_SMB_ALERTEN_SHIFT 6
2261 #define I2C_SMB_FACK_MASK 0x80u
2262 #define I2C_SMB_FACK_SHIFT 7
2263 /* A2 Bit Fields */
2264 #define I2C_A2_SAD_MASK 0xFEu
2265 #define I2C_A2_SAD_SHIFT 1
2266 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
2267 /* SLTH Bit Fields */
2268 #define I2C_SLTH_SSLT_MASK 0xFFu
2269 #define I2C_SLTH_SSLT_SHIFT 0
2270 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
2271 /* SLTL Bit Fields */
2272 #define I2C_SLTL_SSLT_MASK 0xFFu
2273 #define I2C_SLTL_SSLT_SHIFT 0
2274 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
2275
2276 /**
2277 * @}
2278 */ /* end of group I2C_Register_Masks */
2279
2280
2281 /* I2C - Peripheral instance base addresses */
2282 /** Peripheral I2C0 base address */
2283 #define I2C0_BASE (0x40066000u)
2284 /** Peripheral I2C0 base pointer */
2285 #define I2C0 ((I2C_Type *)I2C0_BASE)
2286
2287 /**
2288 * @}
2289 */ /* end of group I2C_Peripheral_Access_Layer */
2290
2291
2292 /* ----------------------------------------------------------------------------
2293 -- I2S Peripheral Access Layer
2294 ---------------------------------------------------------------------------- */
2295
2296 /**
2297 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
2298 * @{
2299 */
2300
2301 /** I2S - Register Layout Typedef */
2302 typedef struct {
2303 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
2304 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
2305 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
2306 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
2307 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
2308 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
2309 uint8_t RESERVED_0[8];
2310 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
2311 uint8_t RESERVED_1[24];
2312 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
2313 uint8_t RESERVED_2[24];
2314 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
2315 uint8_t RESERVED_3[28];
2316 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
2317 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
2318 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
2319 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
2320 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
2321 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
2322 uint8_t RESERVED_4[8];
2323 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
2324 uint8_t RESERVED_5[24];
2325 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
2326 uint8_t RESERVED_6[24];
2327 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
2328 uint8_t RESERVED_7[28];
2329 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
2330 __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
2331 } I2S_Type;
2332
2333 /* ----------------------------------------------------------------------------
2334 -- I2S Register Masks
2335 ---------------------------------------------------------------------------- */
2336
2337 /**
2338 * @addtogroup I2S_Register_Masks I2S Register Masks
2339 * @{
2340 */
2341
2342 /* TCSR Bit Fields */
2343 #define I2S_TCSR_FRDE_MASK 0x1u
2344 #define I2S_TCSR_FRDE_SHIFT 0
2345 #define I2S_TCSR_FWDE_MASK 0x2u
2346 #define I2S_TCSR_FWDE_SHIFT 1
2347 #define I2S_TCSR_FRIE_MASK 0x100u
2348 #define I2S_TCSR_FRIE_SHIFT 8
2349 #define I2S_TCSR_FWIE_MASK 0x200u
2350 #define I2S_TCSR_FWIE_SHIFT 9
2351 #define I2S_TCSR_FEIE_MASK 0x400u
2352 #define I2S_TCSR_FEIE_SHIFT 10
2353 #define I2S_TCSR_SEIE_MASK 0x800u
2354 #define I2S_TCSR_SEIE_SHIFT 11
2355 #define I2S_TCSR_WSIE_MASK 0x1000u
2356 #define I2S_TCSR_WSIE_SHIFT 12
2357 #define I2S_TCSR_FRF_MASK 0x10000u
2358 #define I2S_TCSR_FRF_SHIFT 16
2359 #define I2S_TCSR_FWF_MASK 0x20000u
2360 #define I2S_TCSR_FWF_SHIFT 17
2361 #define I2S_TCSR_FEF_MASK 0x40000u
2362 #define I2S_TCSR_FEF_SHIFT 18
2363 #define I2S_TCSR_SEF_MASK 0x80000u
2364 #define I2S_TCSR_SEF_SHIFT 19
2365 #define I2S_TCSR_WSF_MASK 0x100000u
2366 #define I2S_TCSR_WSF_SHIFT 20
2367 #define I2S_TCSR_SR_MASK 0x1000000u
2368 #define I2S_TCSR_SR_SHIFT 24
2369 #define I2S_TCSR_FR_MASK 0x2000000u
2370 #define I2S_TCSR_FR_SHIFT 25
2371 #define I2S_TCSR_BCE_MASK 0x10000000u
2372 #define I2S_TCSR_BCE_SHIFT 28
2373 #define I2S_TCSR_DBGE_MASK 0x20000000u
2374 #define I2S_TCSR_DBGE_SHIFT 29
2375 #define I2S_TCSR_STOPE_MASK 0x40000000u
2376 #define I2S_TCSR_STOPE_SHIFT 30
2377 #define I2S_TCSR_TE_MASK 0x80000000u
2378 #define I2S_TCSR_TE_SHIFT 31
2379 /* TCR1 Bit Fields */
2380 #define I2S_TCR1_TFW_MASK 0x7u
2381 #define I2S_TCR1_TFW_SHIFT 0
2382 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
2383 /* TCR2 Bit Fields */
2384 #define I2S_TCR2_DIV_MASK 0xFFu
2385 #define I2S_TCR2_DIV_SHIFT 0
2386 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
2387 #define I2S_TCR2_BCD_MASK 0x1000000u
2388 #define I2S_TCR2_BCD_SHIFT 24
2389 #define I2S_TCR2_BCP_MASK 0x2000000u
2390 #define I2S_TCR2_BCP_SHIFT 25
2391 #define I2S_TCR2_MSEL_MASK 0xC000000u
2392 #define I2S_TCR2_MSEL_SHIFT 26
2393 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
2394 #define I2S_TCR2_BCI_MASK 0x10000000u
2395 #define I2S_TCR2_BCI_SHIFT 28
2396 #define I2S_TCR2_BCS_MASK 0x20000000u
2397 #define I2S_TCR2_BCS_SHIFT 29
2398 #define I2S_TCR2_SYNC_MASK 0xC0000000u
2399 #define I2S_TCR2_SYNC_SHIFT 30
2400 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
2401 /* TCR3 Bit Fields */
2402 #define I2S_TCR3_WDFL_MASK 0x1Fu
2403 #define I2S_TCR3_WDFL_SHIFT 0
2404 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
2405 #define I2S_TCR3_TCE_MASK 0x30000u
2406 #define I2S_TCR3_TCE_SHIFT 16
2407 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
2408 /* TCR4 Bit Fields */
2409 #define I2S_TCR4_FSD_MASK 0x1u
2410 #define I2S_TCR4_FSD_SHIFT 0
2411 #define I2S_TCR4_FSP_MASK 0x2u
2412 #define I2S_TCR4_FSP_SHIFT 1
2413 #define I2S_TCR4_FSE_MASK 0x8u
2414 #define I2S_TCR4_FSE_SHIFT 3
2415 #define I2S_TCR4_MF_MASK 0x10u
2416 #define I2S_TCR4_MF_SHIFT 4
2417 #define I2S_TCR4_SYWD_MASK 0x1F00u
2418 #define I2S_TCR4_SYWD_SHIFT 8
2419 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
2420 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
2421 #define I2S_TCR4_FRSZ_SHIFT 16
2422 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
2423 /* TCR5 Bit Fields */
2424 #define I2S_TCR5_FBT_MASK 0x1F00u
2425 #define I2S_TCR5_FBT_SHIFT 8
2426 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
2427 #define I2S_TCR5_W0W_MASK 0x1F0000u
2428 #define I2S_TCR5_W0W_SHIFT 16
2429 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
2430 #define I2S_TCR5_WNW_MASK 0x1F000000u
2431 #define I2S_TCR5_WNW_SHIFT 24
2432 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
2433 /* TDR Bit Fields */
2434 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
2435 #define I2S_TDR_TDR_SHIFT 0
2436 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
2437 /* TFR Bit Fields */
2438 #define I2S_TFR_RFP_MASK 0xFu
2439 #define I2S_TFR_RFP_SHIFT 0
2440 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
2441 #define I2S_TFR_WFP_MASK 0xF0000u
2442 #define I2S_TFR_WFP_SHIFT 16
2443 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
2444 /* TMR Bit Fields */
2445 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
2446 #define I2S_TMR_TWM_SHIFT 0
2447 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
2448 /* RCSR Bit Fields */
2449 #define I2S_RCSR_FRDE_MASK 0x1u
2450 #define I2S_RCSR_FRDE_SHIFT 0
2451 #define I2S_RCSR_FWDE_MASK 0x2u
2452 #define I2S_RCSR_FWDE_SHIFT 1
2453 #define I2S_RCSR_FRIE_MASK 0x100u
2454 #define I2S_RCSR_FRIE_SHIFT 8
2455 #define I2S_RCSR_FWIE_MASK 0x200u
2456 #define I2S_RCSR_FWIE_SHIFT 9
2457 #define I2S_RCSR_FEIE_MASK 0x400u
2458 #define I2S_RCSR_FEIE_SHIFT 10
2459 #define I2S_RCSR_SEIE_MASK 0x800u
2460 #define I2S_RCSR_SEIE_SHIFT 11
2461 #define I2S_RCSR_WSIE_MASK 0x1000u
2462 #define I2S_RCSR_WSIE_SHIFT 12
2463 #define I2S_RCSR_FRF_MASK 0x10000u
2464 #define I2S_RCSR_FRF_SHIFT 16
2465 #define I2S_RCSR_FWF_MASK 0x20000u
2466 #define I2S_RCSR_FWF_SHIFT 17
2467 #define I2S_RCSR_FEF_MASK 0x40000u
2468 #define I2S_RCSR_FEF_SHIFT 18
2469 #define I2S_RCSR_SEF_MASK 0x80000u
2470 #define I2S_RCSR_SEF_SHIFT 19
2471 #define I2S_RCSR_WSF_MASK 0x100000u
2472 #define I2S_RCSR_WSF_SHIFT 20
2473 #define I2S_RCSR_SR_MASK 0x1000000u
2474 #define I2S_RCSR_SR_SHIFT 24
2475 #define I2S_RCSR_FR_MASK 0x2000000u
2476 #define I2S_RCSR_FR_SHIFT 25
2477 #define I2S_RCSR_BCE_MASK 0x10000000u
2478 #define I2S_RCSR_BCE_SHIFT 28
2479 #define I2S_RCSR_DBGE_MASK 0x20000000u
2480 #define I2S_RCSR_DBGE_SHIFT 29
2481 #define I2S_RCSR_STOPE_MASK 0x40000000u
2482 #define I2S_RCSR_STOPE_SHIFT 30
2483 #define I2S_RCSR_RE_MASK 0x80000000u
2484 #define I2S_RCSR_RE_SHIFT 31
2485 /* RCR1 Bit Fields */
2486 #define I2S_RCR1_RFW_MASK 0x7u
2487 #define I2S_RCR1_RFW_SHIFT 0
2488 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
2489 /* RCR2 Bit Fields */
2490 #define I2S_RCR2_DIV_MASK 0xFFu
2491 #define I2S_RCR2_DIV_SHIFT 0
2492 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
2493 #define I2S_RCR2_BCD_MASK 0x1000000u
2494 #define I2S_RCR2_BCD_SHIFT 24
2495 #define I2S_RCR2_BCP_MASK 0x2000000u
2496 #define I2S_RCR2_BCP_SHIFT 25
2497 #define I2S_RCR2_MSEL_MASK 0xC000000u
2498 #define I2S_RCR2_MSEL_SHIFT 26
2499 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
2500 #define I2S_RCR2_BCI_MASK 0x10000000u
2501 #define I2S_RCR2_BCI_SHIFT 28
2502 #define I2S_RCR2_BCS_MASK 0x20000000u
2503 #define I2S_RCR2_BCS_SHIFT 29
2504 #define I2S_RCR2_SYNC_MASK 0xC0000000u
2505 #define I2S_RCR2_SYNC_SHIFT 30
2506 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
2507 /* RCR3 Bit Fields */
2508 #define I2S_RCR3_WDFL_MASK 0x1Fu
2509 #define I2S_RCR3_WDFL_SHIFT 0
2510 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
2511 #define I2S_RCR3_RCE_MASK 0x30000u
2512 #define I2S_RCR3_RCE_SHIFT 16
2513 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
2514 /* RCR4 Bit Fields */
2515 #define I2S_RCR4_FSD_MASK 0x1u
2516 #define I2S_RCR4_FSD_SHIFT 0
2517 #define I2S_RCR4_FSP_MASK 0x2u
2518 #define I2S_RCR4_FSP_SHIFT 1
2519 #define I2S_RCR4_FSE_MASK 0x8u
2520 #define I2S_RCR4_FSE_SHIFT 3
2521 #define I2S_RCR4_MF_MASK 0x10u
2522 #define I2S_RCR4_MF_SHIFT 4
2523 #define I2S_RCR4_SYWD_MASK 0x1F00u
2524 #define I2S_RCR4_SYWD_SHIFT 8
2525 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
2526 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
2527 #define I2S_RCR4_FRSZ_SHIFT 16
2528 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
2529 /* RCR5 Bit Fields */
2530 #define I2S_RCR5_FBT_MASK 0x1F00u
2531 #define I2S_RCR5_FBT_SHIFT 8
2532 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
2533 #define I2S_RCR5_W0W_MASK 0x1F0000u
2534 #define I2S_RCR5_W0W_SHIFT 16
2535 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
2536 #define I2S_RCR5_WNW_MASK 0x1F000000u
2537 #define I2S_RCR5_WNW_SHIFT 24
2538 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
2539 /* RDR Bit Fields */
2540 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
2541 #define I2S_RDR_RDR_SHIFT 0
2542 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
2543 /* RFR Bit Fields */
2544 #define I2S_RFR_RFP_MASK 0xFu
2545 #define I2S_RFR_RFP_SHIFT 0
2546 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
2547 #define I2S_RFR_WFP_MASK 0xF0000u
2548 #define I2S_RFR_WFP_SHIFT 16
2549 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
2550 /* RMR Bit Fields */
2551 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
2552 #define I2S_RMR_RWM_SHIFT 0
2553 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
2554 /* MCR Bit Fields */
2555 #define I2S_MCR_MICS_MASK 0x3000000u
2556 #define I2S_MCR_MICS_SHIFT 24
2557 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
2558 #define I2S_MCR_MOE_MASK 0x40000000u
2559 #define I2S_MCR_MOE_SHIFT 30
2560 #define I2S_MCR_DUF_MASK 0x80000000u
2561 #define I2S_MCR_DUF_SHIFT 31
2562 /* MDR Bit Fields */
2563 #define I2S_MDR_DIVIDE_MASK 0xFFFu
2564 #define I2S_MDR_DIVIDE_SHIFT 0
2565 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
2566 #define I2S_MDR_FRACT_MASK 0xFF000u
2567 #define I2S_MDR_FRACT_SHIFT 12
2568 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
2569
2570 /**
2571 * @}
2572 */ /* end of group I2S_Register_Masks */
2573
2574
2575 /* I2S - Peripheral instance base addresses */
2576 /** Peripheral I2S0 base address */
2577 #define I2S0_BASE (0x4002F000u)
2578 /** Peripheral I2S0 base pointer */
2579 #define I2S0 ((I2S_Type *)I2S0_BASE)
2580
2581 /**
2582 * @}
2583 */ /* end of group I2S_Peripheral_Access_Layer */
2584
2585
2586 /* ----------------------------------------------------------------------------
2587 -- LLWU Peripheral Access Layer
2588 ---------------------------------------------------------------------------- */
2589
2590 /**
2591 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
2592 * @{
2593 */
2594
2595 /** LLWU - Register Layout Typedef */
2596 typedef struct {
2597 __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
2598 __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
2599 __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
2600 __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
2601 __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
2602 __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
2603 __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
2604 __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
2605 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
2606 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
2607 __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
2608 } LLWU_Type;
2609
2610 /* ----------------------------------------------------------------------------
2611 -- LLWU Register Masks
2612 ---------------------------------------------------------------------------- */
2613
2614 /**
2615 * @addtogroup LLWU_Register_Masks LLWU Register Masks
2616 * @{
2617 */
2618
2619 /* PE1 Bit Fields */
2620 #define LLWU_PE1_WUPE0_MASK 0x3u
2621 #define LLWU_PE1_WUPE0_SHIFT 0
2622 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
2623 #define LLWU_PE1_WUPE1_MASK 0xCu
2624 #define LLWU_PE1_WUPE1_SHIFT 2
2625 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
2626 #define LLWU_PE1_WUPE2_MASK 0x30u
2627 #define LLWU_PE1_WUPE2_SHIFT 4
2628 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
2629 #define LLWU_PE1_WUPE3_MASK 0xC0u
2630 #define LLWU_PE1_WUPE3_SHIFT 6
2631 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
2632 /* PE2 Bit Fields */
2633 #define LLWU_PE2_WUPE4_MASK 0x3u
2634 #define LLWU_PE2_WUPE4_SHIFT 0
2635 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
2636 #define LLWU_PE2_WUPE5_MASK 0xCu
2637 #define LLWU_PE2_WUPE5_SHIFT 2
2638 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
2639 #define LLWU_PE2_WUPE6_MASK 0x30u
2640 #define LLWU_PE2_WUPE6_SHIFT 4
2641 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
2642 #define LLWU_PE2_WUPE7_MASK 0xC0u
2643 #define LLWU_PE2_WUPE7_SHIFT 6
2644 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
2645 /* PE3 Bit Fields */
2646 #define LLWU_PE3_WUPE8_MASK 0x3u
2647 #define LLWU_PE3_WUPE8_SHIFT 0
2648 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
2649 #define LLWU_PE3_WUPE9_MASK 0xCu
2650 #define LLWU_PE3_WUPE9_SHIFT 2
2651 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
2652 #define LLWU_PE3_WUPE10_MASK 0x30u
2653 #define LLWU_PE3_WUPE10_SHIFT 4
2654 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
2655 #define LLWU_PE3_WUPE11_MASK 0xC0u
2656 #define LLWU_PE3_WUPE11_SHIFT 6
2657 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
2658 /* PE4 Bit Fields */
2659 #define LLWU_PE4_WUPE12_MASK 0x3u
2660 #define LLWU_PE4_WUPE12_SHIFT 0
2661 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
2662 #define LLWU_PE4_WUPE13_MASK 0xCu
2663 #define LLWU_PE4_WUPE13_SHIFT 2
2664 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
2665 #define LLWU_PE4_WUPE14_MASK 0x30u
2666 #define LLWU_PE4_WUPE14_SHIFT 4
2667 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
2668 #define LLWU_PE4_WUPE15_MASK 0xC0u
2669 #define LLWU_PE4_WUPE15_SHIFT 6
2670 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
2671 /* ME Bit Fields */
2672 #define LLWU_ME_WUME0_MASK 0x1u
2673 #define LLWU_ME_WUME0_SHIFT 0
2674 #define LLWU_ME_WUME1_MASK 0x2u
2675 #define LLWU_ME_WUME1_SHIFT 1
2676 #define LLWU_ME_WUME2_MASK 0x4u
2677 #define LLWU_ME_WUME2_SHIFT 2
2678 #define LLWU_ME_WUME3_MASK 0x8u
2679 #define LLWU_ME_WUME3_SHIFT 3
2680 #define LLWU_ME_WUME4_MASK 0x10u
2681 #define LLWU_ME_WUME4_SHIFT 4
2682 #define LLWU_ME_WUME5_MASK 0x20u
2683 #define LLWU_ME_WUME5_SHIFT 5
2684 #define LLWU_ME_WUME6_MASK 0x40u
2685 #define LLWU_ME_WUME6_SHIFT 6
2686 #define LLWU_ME_WUME7_MASK 0x80u
2687 #define LLWU_ME_WUME7_SHIFT 7
2688 /* F1 Bit Fields */
2689 #define LLWU_F1_WUF0_MASK 0x1u
2690 #define LLWU_F1_WUF0_SHIFT 0
2691 #define LLWU_F1_WUF1_MASK 0x2u
2692 #define LLWU_F1_WUF1_SHIFT 1
2693 #define LLWU_F1_WUF2_MASK 0x4u
2694 #define LLWU_F1_WUF2_SHIFT 2
2695 #define LLWU_F1_WUF3_MASK 0x8u
2696 #define LLWU_F1_WUF3_SHIFT 3
2697 #define LLWU_F1_WUF4_MASK 0x10u
2698 #define LLWU_F1_WUF4_SHIFT 4
2699 #define LLWU_F1_WUF5_MASK 0x20u
2700 #define LLWU_F1_WUF5_SHIFT 5
2701 #define LLWU_F1_WUF6_MASK 0x40u
2702 #define LLWU_F1_WUF6_SHIFT 6
2703 #define LLWU_F1_WUF7_MASK 0x80u
2704 #define LLWU_F1_WUF7_SHIFT 7
2705 /* F2 Bit Fields */
2706 #define LLWU_F2_WUF8_MASK 0x1u
2707 #define LLWU_F2_WUF8_SHIFT 0
2708 #define LLWU_F2_WUF9_MASK 0x2u
2709 #define LLWU_F2_WUF9_SHIFT 1
2710 #define LLWU_F2_WUF10_MASK 0x4u
2711 #define LLWU_F2_WUF10_SHIFT 2
2712 #define LLWU_F2_WUF11_MASK 0x8u
2713 #define LLWU_F2_WUF11_SHIFT 3
2714 #define LLWU_F2_WUF12_MASK 0x10u
2715 #define LLWU_F2_WUF12_SHIFT 4
2716 #define LLWU_F2_WUF13_MASK 0x20u
2717 #define LLWU_F2_WUF13_SHIFT 5
2718 #define LLWU_F2_WUF14_MASK 0x40u
2719 #define LLWU_F2_WUF14_SHIFT 6
2720 #define LLWU_F2_WUF15_MASK 0x80u
2721 #define LLWU_F2_WUF15_SHIFT 7
2722 /* F3 Bit Fields */
2723 #define LLWU_F3_MWUF0_MASK 0x1u
2724 #define LLWU_F3_MWUF0_SHIFT 0
2725 #define LLWU_F3_MWUF1_MASK 0x2u
2726 #define LLWU_F3_MWUF1_SHIFT 1
2727 #define LLWU_F3_MWUF2_MASK 0x4u
2728 #define LLWU_F3_MWUF2_SHIFT 2
2729 #define LLWU_F3_MWUF3_MASK 0x8u
2730 #define LLWU_F3_MWUF3_SHIFT 3
2731 #define LLWU_F3_MWUF4_MASK 0x10u
2732 #define LLWU_F3_MWUF4_SHIFT 4
2733 #define LLWU_F3_MWUF5_MASK 0x20u
2734 #define LLWU_F3_MWUF5_SHIFT 5
2735 #define LLWU_F3_MWUF6_MASK 0x40u
2736 #define LLWU_F3_MWUF6_SHIFT 6
2737 #define LLWU_F3_MWUF7_MASK 0x80u
2738 #define LLWU_F3_MWUF7_SHIFT 7
2739 /* FILT1 Bit Fields */
2740 #define LLWU_FILT1_FILTSEL_MASK 0xFu
2741 #define LLWU_FILT1_FILTSEL_SHIFT 0
2742 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
2743 #define LLWU_FILT1_FILTE_MASK 0x60u
2744 #define LLWU_FILT1_FILTE_SHIFT 5
2745 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
2746 #define LLWU_FILT1_FILTF_MASK 0x80u
2747 #define LLWU_FILT1_FILTF_SHIFT 7
2748 /* FILT2 Bit Fields */
2749 #define LLWU_FILT2_FILTSEL_MASK 0xFu
2750 #define LLWU_FILT2_FILTSEL_SHIFT 0
2751 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
2752 #define LLWU_FILT2_FILTE_MASK 0x60u
2753 #define LLWU_FILT2_FILTE_SHIFT 5
2754 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
2755 #define LLWU_FILT2_FILTF_MASK 0x80u
2756 #define LLWU_FILT2_FILTF_SHIFT 7
2757 /* RST Bit Fields */
2758 #define LLWU_RST_RSTFILT_MASK 0x1u
2759 #define LLWU_RST_RSTFILT_SHIFT 0
2760 #define LLWU_RST_LLRSTE_MASK 0x2u
2761 #define LLWU_RST_LLRSTE_SHIFT 1
2762
2763 /**
2764 * @}
2765 */ /* end of group LLWU_Register_Masks */
2766
2767
2768 /* LLWU - Peripheral instance base addresses */
2769 /** Peripheral LLWU base address */
2770 #define LLWU_BASE (0x4007C000u)
2771 /** Peripheral LLWU base pointer */
2772 #define LLWU ((LLWU_Type *)LLWU_BASE)
2773
2774 /**
2775 * @}
2776 */ /* end of group LLWU_Peripheral_Access_Layer */
2777
2778
2779 /* ----------------------------------------------------------------------------
2780 -- LPTMR Peripheral Access Layer
2781 ---------------------------------------------------------------------------- */
2782
2783 /**
2784 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
2785 * @{
2786 */
2787
2788 /** LPTMR - Register Layout Typedef */
2789 typedef struct {
2790 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
2791 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
2792 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
2793 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
2794 } LPTMR_Type;
2795
2796 /* ----------------------------------------------------------------------------
2797 -- LPTMR Register Masks
2798 ---------------------------------------------------------------------------- */
2799
2800 /**
2801 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
2802 * @{
2803 */
2804
2805 /* CSR Bit Fields */
2806 #define LPTMR_CSR_TEN_MASK 0x1u
2807 #define LPTMR_CSR_TEN_SHIFT 0
2808 #define LPTMR_CSR_TMS_MASK 0x2u
2809 #define LPTMR_CSR_TMS_SHIFT 1
2810 #define LPTMR_CSR_TFC_MASK 0x4u
2811 #define LPTMR_CSR_TFC_SHIFT 2
2812 #define LPTMR_CSR_TPP_MASK 0x8u
2813 #define LPTMR_CSR_TPP_SHIFT 3
2814 #define LPTMR_CSR_TPS_MASK 0x30u
2815 #define LPTMR_CSR_TPS_SHIFT 4
2816 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
2817 #define LPTMR_CSR_TIE_MASK 0x40u
2818 #define LPTMR_CSR_TIE_SHIFT 6
2819 #define LPTMR_CSR_TCF_MASK 0x80u
2820 #define LPTMR_CSR_TCF_SHIFT 7
2821 /* PSR Bit Fields */
2822 #define LPTMR_PSR_PCS_MASK 0x3u
2823 #define LPTMR_PSR_PCS_SHIFT 0
2824 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
2825 #define LPTMR_PSR_PBYP_MASK 0x4u
2826 #define LPTMR_PSR_PBYP_SHIFT 2
2827 #define LPTMR_PSR_PRESCALE_MASK 0x78u
2828 #define LPTMR_PSR_PRESCALE_SHIFT 3
2829 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
2830 /* CMR Bit Fields */
2831 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
2832 #define LPTMR_CMR_COMPARE_SHIFT 0
2833 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
2834 /* CNR Bit Fields */
2835 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
2836 #define LPTMR_CNR_COUNTER_SHIFT 0
2837 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
2838
2839 /**
2840 * @}
2841 */ /* end of group LPTMR_Register_Masks */
2842
2843
2844 /* LPTMR - Peripheral instance base addresses */
2845 /** Peripheral LPTMR0 base address */
2846 #define LPTMR0_BASE (0x40040000u)
2847 /** Peripheral LPTMR0 base pointer */
2848 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
2849
2850 /**
2851 * @}
2852 */ /* end of group LPTMR_Peripheral_Access_Layer */
2853
2854
2855 /* ----------------------------------------------------------------------------
2856 -- MCG Peripheral Access Layer
2857 ---------------------------------------------------------------------------- */
2858
2859 /**
2860 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
2861 * @{
2862 */
2863
2864 /** MCG - Register Layout Typedef */
2865 typedef struct {
2866 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
2867 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
2868 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
2869 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
2870 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
2871 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
2872 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
2873 uint8_t RESERVED_0[1];
2874 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
2875 uint8_t RESERVED_1[1];
2876 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
2877 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
2878 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
2879 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
2880 } MCG_Type;
2881
2882 /* ----------------------------------------------------------------------------
2883 -- MCG Register Masks
2884 ---------------------------------------------------------------------------- */
2885
2886 /**
2887 * @addtogroup MCG_Register_Masks MCG Register Masks
2888 * @{
2889 */
2890
2891 /* C1 Bit Fields */
2892 #define MCG_C1_IREFSTEN_MASK 0x1u
2893 #define MCG_C1_IREFSTEN_SHIFT 0
2894 #define MCG_C1_IRCLKEN_MASK 0x2u
2895 #define MCG_C1_IRCLKEN_SHIFT 1
2896 #define MCG_C1_IREFS_MASK 0x4u
2897 #define MCG_C1_IREFS_SHIFT 2
2898 #define MCG_C1_FRDIV_MASK 0x38u
2899 #define MCG_C1_FRDIV_SHIFT 3
2900 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
2901 #define MCG_C1_CLKS_MASK 0xC0u
2902 #define MCG_C1_CLKS_SHIFT 6
2903 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
2904 /* C2 Bit Fields */
2905 #define MCG_C2_IRCS_MASK 0x1u
2906 #define MCG_C2_IRCS_SHIFT 0
2907 #define MCG_C2_LP_MASK 0x2u
2908 #define MCG_C2_LP_SHIFT 1
2909 #define MCG_C2_EREFS0_MASK 0x4u
2910 #define MCG_C2_EREFS0_SHIFT 2
2911 #define MCG_C2_HGO0_MASK 0x8u
2912 #define MCG_C2_HGO0_SHIFT 3
2913 #define MCG_C2_RANGE0_MASK 0x30u
2914 #define MCG_C2_RANGE0_SHIFT 4
2915 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
2916 #define MCG_C2_LOCRE0_MASK 0x80u
2917 #define MCG_C2_LOCRE0_SHIFT 7
2918 /* C3 Bit Fields */
2919 #define MCG_C3_SCTRIM_MASK 0xFFu
2920 #define MCG_C3_SCTRIM_SHIFT 0
2921 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
2922 /* C4 Bit Fields */
2923 #define MCG_C4_SCFTRIM_MASK 0x1u
2924 #define MCG_C4_SCFTRIM_SHIFT 0
2925 #define MCG_C4_FCTRIM_MASK 0x1Eu
2926 #define MCG_C4_FCTRIM_SHIFT 1
2927 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
2928 #define MCG_C4_DRST_DRS_MASK 0x60u
2929 #define MCG_C4_DRST_DRS_SHIFT 5
2930 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
2931 #define MCG_C4_DMX32_MASK 0x80u
2932 #define MCG_C4_DMX32_SHIFT 7
2933 /* C5 Bit Fields */
2934 #define MCG_C5_PRDIV0_MASK 0x1Fu
2935 #define MCG_C5_PRDIV0_SHIFT 0
2936 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
2937 #define MCG_C5_PLLSTEN0_MASK 0x20u
2938 #define MCG_C5_PLLSTEN0_SHIFT 5
2939 #define MCG_C5_PLLCLKEN0_MASK 0x40u
2940 #define MCG_C5_PLLCLKEN0_SHIFT 6
2941 /* C6 Bit Fields */
2942 #define MCG_C6_VDIV0_MASK 0x1Fu
2943 #define MCG_C6_VDIV0_SHIFT 0
2944 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
2945 #define MCG_C6_CME0_MASK 0x20u
2946 #define MCG_C6_CME0_SHIFT 5
2947 #define MCG_C6_PLLS_MASK 0x40u
2948 #define MCG_C6_PLLS_SHIFT 6
2949 #define MCG_C6_LOLIE0_MASK 0x80u
2950 #define MCG_C6_LOLIE0_SHIFT 7
2951 /* S Bit Fields */
2952 #define MCG_S_IRCST_MASK 0x1u
2953 #define MCG_S_IRCST_SHIFT 0
2954 #define MCG_S_OSCINIT0_MASK 0x2u
2955 #define MCG_S_OSCINIT0_SHIFT 1
2956 #define MCG_S_CLKST_MASK 0xCu
2957 #define MCG_S_CLKST_SHIFT 2
2958 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
2959 #define MCG_S_IREFST_MASK 0x10u
2960 #define MCG_S_IREFST_SHIFT 4
2961 #define MCG_S_PLLST_MASK 0x20u
2962 #define MCG_S_PLLST_SHIFT 5
2963 #define MCG_S_LOCK0_MASK 0x40u
2964 #define MCG_S_LOCK0_SHIFT 6
2965 #define MCG_S_LOLS0_MASK 0x80u
2966 #define MCG_S_LOLS0_SHIFT 7
2967 /* SC Bit Fields */
2968 #define MCG_SC_LOCS0_MASK 0x1u
2969 #define MCG_SC_LOCS0_SHIFT 0
2970 #define MCG_SC_FCRDIV_MASK 0xEu
2971 #define MCG_SC_FCRDIV_SHIFT 1
2972 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
2973 #define MCG_SC_FLTPRSRV_MASK 0x10u
2974 #define MCG_SC_FLTPRSRV_SHIFT 4
2975 #define MCG_SC_ATMF_MASK 0x20u
2976 #define MCG_SC_ATMF_SHIFT 5
2977 #define MCG_SC_ATMS_MASK 0x40u
2978 #define MCG_SC_ATMS_SHIFT 6
2979 #define MCG_SC_ATME_MASK 0x80u
2980 #define MCG_SC_ATME_SHIFT 7
2981 /* ATCVH Bit Fields */
2982 #define MCG_ATCVH_ATCVH_MASK 0xFFu
2983 #define MCG_ATCVH_ATCVH_SHIFT 0
2984 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
2985 /* ATCVL Bit Fields */
2986 #define MCG_ATCVL_ATCVL_MASK 0xFFu
2987 #define MCG_ATCVL_ATCVL_SHIFT 0
2988 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
2989 /* C7 Bit Fields */
2990 #define MCG_C7_OSCSEL_MASK 0x1u
2991 #define MCG_C7_OSCSEL_SHIFT 0
2992 /* C8 Bit Fields */
2993 #define MCG_C8_LOCS1_MASK 0x1u
2994 #define MCG_C8_LOCS1_SHIFT 0
2995 #define MCG_C8_CME1_MASK 0x20u
2996 #define MCG_C8_CME1_SHIFT 5
2997 #define MCG_C8_LOLRE_MASK 0x40u
2998 #define MCG_C8_LOLRE_SHIFT 6
2999 #define MCG_C8_LOCRE1_MASK 0x80u
3000 #define MCG_C8_LOCRE1_SHIFT 7
3001
3002 /**
3003 * @}
3004 */ /* end of group MCG_Register_Masks */
3005
3006
3007 /* MCG - Peripheral instance base addresses */
3008 /** Peripheral MCG base address */
3009 #define MCG_BASE (0x40064000u)
3010 /** Peripheral MCG base pointer */
3011 #define MCG ((MCG_Type *)MCG_BASE)
3012
3013 /**
3014 * @}
3015 */ /* end of group MCG_Peripheral_Access_Layer */
3016
3017
3018 /* ----------------------------------------------------------------------------
3019 -- NV Peripheral Access Layer
3020 ---------------------------------------------------------------------------- */
3021
3022 /**
3023 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
3024 * @{
3025 */
3026
3027 /** NV - Register Layout Typedef */
3028 typedef struct {
3029 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
3030 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
3031 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
3032 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
3033 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
3034 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
3035 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
3036 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
3037 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
3038 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
3039 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
3040 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
3041 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
3042 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
3043 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
3044 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
3045 } NV_Type;
3046
3047 /* ----------------------------------------------------------------------------
3048 -- NV Register Masks
3049 ---------------------------------------------------------------------------- */
3050
3051 /**
3052 * @addtogroup NV_Register_Masks NV Register Masks
3053 * @{
3054 */
3055
3056 /* BACKKEY3 Bit Fields */
3057 #define NV_BACKKEY3_KEY_MASK 0xFFu
3058 #define NV_BACKKEY3_KEY_SHIFT 0
3059 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
3060 /* BACKKEY2 Bit Fields */
3061 #define NV_BACKKEY2_KEY_MASK 0xFFu
3062 #define NV_BACKKEY2_KEY_SHIFT 0
3063 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
3064 /* BACKKEY1 Bit Fields */
3065 #define NV_BACKKEY1_KEY_MASK 0xFFu
3066 #define NV_BACKKEY1_KEY_SHIFT 0
3067 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
3068 /* BACKKEY0 Bit Fields */
3069 #define NV_BACKKEY0_KEY_MASK 0xFFu
3070 #define NV_BACKKEY0_KEY_SHIFT 0
3071 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
3072 /* BACKKEY7 Bit Fields */
3073 #define NV_BACKKEY7_KEY_MASK 0xFFu
3074 #define NV_BACKKEY7_KEY_SHIFT 0
3075 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
3076 /* BACKKEY6 Bit Fields */
3077 #define NV_BACKKEY6_KEY_MASK 0xFFu
3078 #define NV_BACKKEY6_KEY_SHIFT 0
3079 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
3080 /* BACKKEY5 Bit Fields */
3081 #define NV_BACKKEY5_KEY_MASK 0xFFu
3082 #define NV_BACKKEY5_KEY_SHIFT 0
3083 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
3084 /* BACKKEY4 Bit Fields */
3085 #define NV_BACKKEY4_KEY_MASK 0xFFu
3086 #define NV_BACKKEY4_KEY_SHIFT 0
3087 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
3088 /* FPROT3 Bit Fields */
3089 #define NV_FPROT3_PROT_MASK 0xFFu
3090 #define NV_FPROT3_PROT_SHIFT 0
3091 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
3092 /* FPROT2 Bit Fields */
3093 #define NV_FPROT2_PROT_MASK 0xFFu
3094 #define NV_FPROT2_PROT_SHIFT 0
3095 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
3096 /* FPROT1 Bit Fields */
3097 #define NV_FPROT1_PROT_MASK 0xFFu
3098 #define NV_FPROT1_PROT_SHIFT 0
3099 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
3100 /* FPROT0 Bit Fields */
3101 #define NV_FPROT0_PROT_MASK 0xFFu
3102 #define NV_FPROT0_PROT_SHIFT 0
3103 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
3104 /* FSEC Bit Fields */
3105 #define NV_FSEC_SEC_MASK 0x3u
3106 #define NV_FSEC_SEC_SHIFT 0
3107 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
3108 #define NV_FSEC_FSLACC_MASK 0xCu
3109 #define NV_FSEC_FSLACC_SHIFT 2
3110 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
3111 #define NV_FSEC_MEEN_MASK 0x30u
3112 #define NV_FSEC_MEEN_SHIFT 4
3113 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
3114 #define NV_FSEC_KEYEN_MASK 0xC0u
3115 #define NV_FSEC_KEYEN_SHIFT 6
3116 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
3117 /* FOPT Bit Fields */
3118 #define NV_FOPT_LPBOOT_MASK 0x1u
3119 #define NV_FOPT_LPBOOT_SHIFT 0
3120 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
3121 #define NV_FOPT_EZPORT_DIS_SHIFT 1
3122 /* FEPROT Bit Fields */
3123 #define NV_FEPROT_EPROT_MASK 0xFFu
3124 #define NV_FEPROT_EPROT_SHIFT 0
3125 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
3126 /* FDPROT Bit Fields */
3127 #define NV_FDPROT_DPROT_MASK 0xFFu
3128 #define NV_FDPROT_DPROT_SHIFT 0
3129 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
3130
3131 /**
3132 * @}
3133 */ /* end of group NV_Register_Masks */
3134
3135
3136 /* NV - Peripheral instance base addresses */
3137 /** Peripheral FTFL_FlashConfig base address */
3138 #define FTFL_FlashConfig_BASE (0x400u)
3139 /** Peripheral FTFL_FlashConfig base pointer */
3140 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
3141
3142 /**
3143 * @}
3144 */ /* end of group NV_Peripheral_Access_Layer */
3145
3146
3147 /* ----------------------------------------------------------------------------
3148 -- OSC Peripheral Access Layer
3149 ---------------------------------------------------------------------------- */
3150
3151 /**
3152 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
3153 * @{
3154 */
3155
3156 /** OSC - Register Layout Typedef */
3157 typedef struct {
3158 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
3159 } OSC_Type;
3160
3161 /* ----------------------------------------------------------------------------
3162 -- OSC Register Masks
3163 ---------------------------------------------------------------------------- */
3164
3165 /**
3166 * @addtogroup OSC_Register_Masks OSC Register Masks
3167 * @{
3168 */
3169
3170 /* CR Bit Fields */
3171 #define OSC_CR_SC16P_MASK 0x1u
3172 #define OSC_CR_SC16P_SHIFT 0
3173 #define OSC_CR_SC8P_MASK 0x2u
3174 #define OSC_CR_SC8P_SHIFT 1
3175 #define OSC_CR_SC4P_MASK 0x4u
3176 #define OSC_CR_SC4P_SHIFT 2
3177 #define OSC_CR_SC2P_MASK 0x8u
3178 #define OSC_CR_SC2P_SHIFT 3
3179 #define OSC_CR_EREFSTEN_MASK 0x20u
3180 #define OSC_CR_EREFSTEN_SHIFT 5
3181 #define OSC_CR_ERCLKEN_MASK 0x80u
3182 #define OSC_CR_ERCLKEN_SHIFT 7
3183
3184 /**
3185 * @}
3186 */ /* end of group OSC_Register_Masks */
3187
3188
3189 /* OSC - Peripheral instance base addresses */
3190 /** Peripheral OSC0 base address */
3191 #define OSC0_BASE (0x40065000u)
3192 /** Peripheral OSC0 base pointer */
3193 #define OSC0 ((OSC_Type *)OSC0_BASE)
3194
3195 /**
3196 * @}
3197 */ /* end of group OSC_Peripheral_Access_Layer */
3198
3199
3200 /* ----------------------------------------------------------------------------
3201 -- PDB Peripheral Access Layer
3202 ---------------------------------------------------------------------------- */
3203
3204 /**
3205 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
3206 * @{
3207 */
3208
3209 /** PDB - Register Layout Typedef */
3210 typedef struct {
3211 __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
3212 __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
3213 __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
3214 __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
3215 struct { /* offset: 0x10, array step: 0x10 */
3216 __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
3217 __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
3218 __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
3219 } CH[1];
3220 uint8_t RESERVED_0[368];
3221 __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
3222 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
3223 } PDB_Type;
3224
3225 /* ----------------------------------------------------------------------------
3226 -- PDB Register Masks
3227 ---------------------------------------------------------------------------- */
3228
3229 /**
3230 * @addtogroup PDB_Register_Masks PDB Register Masks
3231 * @{
3232 */
3233
3234 /* SC Bit Fields */
3235 #define PDB_SC_LDOK_MASK 0x1u
3236 #define PDB_SC_LDOK_SHIFT 0
3237 #define PDB_SC_CONT_MASK 0x2u
3238 #define PDB_SC_CONT_SHIFT 1
3239 #define PDB_SC_MULT_MASK 0xCu
3240 #define PDB_SC_MULT_SHIFT 2
3241 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
3242 #define PDB_SC_PDBIE_MASK 0x20u
3243 #define PDB_SC_PDBIE_SHIFT 5
3244 #define PDB_SC_PDBIF_MASK 0x40u
3245 #define PDB_SC_PDBIF_SHIFT 6
3246 #define PDB_SC_PDBEN_MASK 0x80u
3247 #define PDB_SC_PDBEN_SHIFT 7
3248 #define PDB_SC_TRGSEL_MASK 0xF00u
3249 #define PDB_SC_TRGSEL_SHIFT 8
3250 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
3251 #define PDB_SC_PRESCALER_MASK 0x7000u
3252 #define PDB_SC_PRESCALER_SHIFT 12
3253 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
3254 #define PDB_SC_DMAEN_MASK 0x8000u
3255 #define PDB_SC_DMAEN_SHIFT 15
3256 #define PDB_SC_SWTRIG_MASK 0x10000u
3257 #define PDB_SC_SWTRIG_SHIFT 16
3258 #define PDB_SC_PDBEIE_MASK 0x20000u
3259 #define PDB_SC_PDBEIE_SHIFT 17
3260 #define PDB_SC_LDMOD_MASK 0xC0000u
3261 #define PDB_SC_LDMOD_SHIFT 18
3262 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
3263 /* MOD Bit Fields */
3264 #define PDB_MOD_MOD_MASK 0xFFFFu
3265 #define PDB_MOD_MOD_SHIFT 0
3266 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
3267 /* CNT Bit Fields */
3268 #define PDB_CNT_CNT_MASK 0xFFFFu
3269 #define PDB_CNT_CNT_SHIFT 0
3270 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
3271 /* IDLY Bit Fields */
3272 #define PDB_IDLY_IDLY_MASK 0xFFFFu
3273 #define PDB_IDLY_IDLY_SHIFT 0
3274 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
3275 /* C1 Bit Fields */
3276 #define PDB_C1_EN_MASK 0xFFu
3277 #define PDB_C1_EN_SHIFT 0
3278 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
3279 #define PDB_C1_TOS_MASK 0xFF00u
3280 #define PDB_C1_TOS_SHIFT 8
3281 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
3282 #define PDB_C1_BB_MASK 0xFF0000u
3283 #define PDB_C1_BB_SHIFT 16
3284 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
3285 /* S Bit Fields */
3286 #define PDB_S_ERR_MASK 0xFFu
3287 #define PDB_S_ERR_SHIFT 0
3288 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
3289 #define PDB_S_CF_MASK 0xFF0000u
3290 #define PDB_S_CF_SHIFT 16
3291 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
3292 /* DLY Bit Fields */
3293 #define PDB_DLY_DLY_MASK 0xFFFFu
3294 #define PDB_DLY_DLY_SHIFT 0
3295 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
3296 /* POEN Bit Fields */
3297 #define PDB_POEN_POEN_MASK 0xFFu
3298 #define PDB_POEN_POEN_SHIFT 0
3299 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
3300 /* PODLY Bit Fields */
3301 #define PDB_PODLY_DLY2_MASK 0xFFFFu
3302 #define PDB_PODLY_DLY2_SHIFT 0
3303 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
3304 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
3305 #define PDB_PODLY_DLY1_SHIFT 16
3306 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
3307
3308 /**
3309 * @}
3310 */ /* end of group PDB_Register_Masks */
3311
3312
3313 /* PDB - Peripheral instance base addresses */
3314 /** Peripheral PDB0 base address */
3315 #define PDB0_BASE (0x40036000u)
3316 /** Peripheral PDB0 base pointer */
3317 #define PDB0 ((PDB_Type *)PDB0_BASE)
3318
3319 /**
3320 * @}
3321 */ /* end of group PDB_Peripheral_Access_Layer */
3322
3323
3324 /* ----------------------------------------------------------------------------
3325 -- PIT Peripheral Access Layer
3326 ---------------------------------------------------------------------------- */
3327
3328 /**
3329 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
3330 * @{
3331 */
3332
3333 /** PIT - Register Layout Typedef */
3334 typedef struct {
3335 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
3336 uint8_t RESERVED_0[252];
3337 struct { /* offset: 0x100, array step: 0x10 */
3338 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
3339 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
3340 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
3341 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
3342 } CHANNEL[4];
3343 } PIT_Type;
3344
3345 /* ----------------------------------------------------------------------------
3346 -- PIT Register Masks
3347 ---------------------------------------------------------------------------- */
3348
3349 /**
3350 * @addtogroup PIT_Register_Masks PIT Register Masks
3351 * @{
3352 */
3353
3354 /* MCR Bit Fields */
3355 #define PIT_MCR_FRZ_MASK 0x1u
3356 #define PIT_MCR_FRZ_SHIFT 0
3357 #define PIT_MCR_MDIS_MASK 0x2u
3358 #define PIT_MCR_MDIS_SHIFT 1
3359 /* LDVAL Bit Fields */
3360 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
3361 #define PIT_LDVAL_TSV_SHIFT 0
3362 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
3363 /* CVAL Bit Fields */
3364 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
3365 #define PIT_CVAL_TVL_SHIFT 0
3366 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
3367 /* TCTRL Bit Fields */
3368 #define PIT_TCTRL_TEN_MASK 0x1u
3369 #define PIT_TCTRL_TEN_SHIFT 0
3370 #define PIT_TCTRL_TIE_MASK 0x2u
3371 #define PIT_TCTRL_TIE_SHIFT 1
3372 /* TFLG Bit Fields */
3373 #define PIT_TFLG_TIF_MASK 0x1u
3374 #define PIT_TFLG_TIF_SHIFT 0
3375
3376 /**
3377 * @}
3378 */ /* end of group PIT_Register_Masks */
3379
3380
3381 /* PIT - Peripheral instance base addresses */
3382 /** Peripheral PIT base address */
3383 #define PIT_BASE (0x40037000u)
3384 /** Peripheral PIT base pointer */
3385 #define PIT ((PIT_Type *)PIT_BASE)
3386
3387 /**
3388 * @}
3389 */ /* end of group PIT_Peripheral_Access_Layer */
3390
3391
3392 /* ----------------------------------------------------------------------------
3393 -- PMC Peripheral Access Layer
3394 ---------------------------------------------------------------------------- */
3395
3396 /**
3397 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
3398 * @{
3399 */
3400
3401 /** PMC - Register Layout Typedef */
3402 typedef struct {
3403 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
3404 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
3405 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
3406 } PMC_Type;
3407
3408 /* ----------------------------------------------------------------------------
3409 -- PMC Register Masks
3410 ---------------------------------------------------------------------------- */
3411
3412 /**
3413 * @addtogroup PMC_Register_Masks PMC Register Masks
3414 * @{
3415 */
3416
3417 /* LVDSC1 Bit Fields */
3418 #define PMC_LVDSC1_LVDV_MASK 0x3u
3419 #define PMC_LVDSC1_LVDV_SHIFT 0
3420 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
3421 #define PMC_LVDSC1_LVDRE_MASK 0x10u
3422 #define PMC_LVDSC1_LVDRE_SHIFT 4
3423 #define PMC_LVDSC1_LVDIE_MASK 0x20u
3424 #define PMC_LVDSC1_LVDIE_SHIFT 5
3425 #define PMC_LVDSC1_LVDACK_MASK 0x40u
3426 #define PMC_LVDSC1_LVDACK_SHIFT 6
3427 #define PMC_LVDSC1_LVDF_MASK 0x80u
3428 #define PMC_LVDSC1_LVDF_SHIFT 7
3429 /* LVDSC2 Bit Fields */
3430 #define PMC_LVDSC2_LVWV_MASK 0x3u
3431 #define PMC_LVDSC2_LVWV_SHIFT 0
3432 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
3433 #define PMC_LVDSC2_LVWIE_MASK 0x20u
3434 #define PMC_LVDSC2_LVWIE_SHIFT 5
3435 #define PMC_LVDSC2_LVWACK_MASK 0x40u
3436 #define PMC_LVDSC2_LVWACK_SHIFT 6
3437 #define PMC_LVDSC2_LVWF_MASK 0x80u
3438 #define PMC_LVDSC2_LVWF_SHIFT 7
3439 /* REGSC Bit Fields */
3440 #define PMC_REGSC_BGBE_MASK 0x1u
3441 #define PMC_REGSC_BGBE_SHIFT 0
3442 #define PMC_REGSC_REGONS_MASK 0x4u
3443 #define PMC_REGSC_REGONS_SHIFT 2
3444 #define PMC_REGSC_ACKISO_MASK 0x8u
3445 #define PMC_REGSC_ACKISO_SHIFT 3
3446
3447 /**
3448 * @}
3449 */ /* end of group PMC_Register_Masks */
3450
3451
3452 /* PMC - Peripheral instance base addresses */
3453 /** Peripheral PMC base address */
3454 #define PMC_BASE (0x4007D000u)
3455 /** Peripheral PMC base pointer */
3456 #define PMC ((PMC_Type *)PMC_BASE)
3457
3458 /**
3459 * @}
3460 */ /* end of group PMC_Peripheral_Access_Layer */
3461
3462
3463 /* ----------------------------------------------------------------------------
3464 -- PORT Peripheral Access Layer
3465 ---------------------------------------------------------------------------- */
3466
3467 /**
3468 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
3469 * @{
3470 */
3471
3472 /** PORT - Register Layout Typedef */
3473 typedef struct {
3474 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
3475 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
3476 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
3477 uint8_t RESERVED_0[24];
3478 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
3479 uint8_t RESERVED_1[28];
3480 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
3481 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
3482 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
3483 } PORT_Type;
3484
3485 /* ----------------------------------------------------------------------------
3486 -- PORT Register Masks
3487 ---------------------------------------------------------------------------- */
3488
3489 /**
3490 * @addtogroup PORT_Register_Masks PORT Register Masks
3491 * @{
3492 */
3493
3494 /* PCR Bit Fields */
3495 #define PORT_PCR_PS_MASK 0x1u
3496 #define PORT_PCR_PS_SHIFT 0
3497 #define PORT_PCR_PE_MASK 0x2u
3498 #define PORT_PCR_PE_SHIFT 1
3499 #define PORT_PCR_SRE_MASK 0x4u
3500 #define PORT_PCR_SRE_SHIFT 2
3501 #define PORT_PCR_PFE_MASK 0x10u
3502 #define PORT_PCR_PFE_SHIFT 4
3503 #define PORT_PCR_ODE_MASK 0x20u
3504 #define PORT_PCR_ODE_SHIFT 5
3505 #define PORT_PCR_DSE_MASK 0x40u
3506 #define PORT_PCR_DSE_SHIFT 6
3507 #define PORT_PCR_MUX_MASK 0x700u
3508 #define PORT_PCR_MUX_SHIFT 8
3509 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
3510 #define PORT_PCR_LK_MASK 0x8000u
3511 #define PORT_PCR_LK_SHIFT 15
3512 #define PORT_PCR_IRQC_MASK 0xF0000u
3513 #define PORT_PCR_IRQC_SHIFT 16
3514 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
3515 #define PORT_PCR_ISF_MASK 0x1000000u
3516 #define PORT_PCR_ISF_SHIFT 24
3517 /* GPCLR Bit Fields */
3518 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
3519 #define PORT_GPCLR_GPWD_SHIFT 0
3520 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
3521 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
3522 #define PORT_GPCLR_GPWE_SHIFT 16
3523 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
3524 /* GPCHR Bit Fields */
3525 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
3526 #define PORT_GPCHR_GPWD_SHIFT 0
3527 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
3528 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
3529 #define PORT_GPCHR_GPWE_SHIFT 16
3530 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
3531 /* ISFR Bit Fields */
3532 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
3533 #define PORT_ISFR_ISF_SHIFT 0
3534 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
3535 /* DFER Bit Fields */
3536 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
3537 #define PORT_DFER_DFE_SHIFT 0
3538 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
3539 /* DFCR Bit Fields */
3540 #define PORT_DFCR_CS_MASK 0x1u
3541 #define PORT_DFCR_CS_SHIFT 0
3542 /* DFWR Bit Fields */
3543 #define PORT_DFWR_FILT_MASK 0x1Fu
3544 #define PORT_DFWR_FILT_SHIFT 0
3545 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
3546
3547 /**
3548 * @}
3549 */ /* end of group PORT_Register_Masks */
3550
3551
3552 /* PORT - Peripheral instance base addresses */
3553 /** Peripheral PORTA base address */
3554 #define PORTA_BASE (0x40049000u)
3555 /** Peripheral PORTA base pointer */
3556 #define PORTA ((PORT_Type *)PORTA_BASE)
3557 /** Peripheral PORTB base address */
3558 #define PORTB_BASE (0x4004A000u)
3559 /** Peripheral PORTB base pointer */
3560 #define PORTB ((PORT_Type *)PORTB_BASE)
3561 /** Peripheral PORTC base address */
3562 #define PORTC_BASE (0x4004B000u)
3563 /** Peripheral PORTC base pointer */
3564 #define PORTC ((PORT_Type *)PORTC_BASE)
3565 /** Peripheral PORTD base address */
3566 #define PORTD_BASE (0x4004C000u)
3567 /** Peripheral PORTD base pointer */
3568 #define PORTD ((PORT_Type *)PORTD_BASE)
3569 /** Peripheral PORTE base address */
3570 #define PORTE_BASE (0x4004D000u)
3571 /** Peripheral PORTE base pointer */
3572 #define PORTE ((PORT_Type *)PORTE_BASE)
3573
3574 /**
3575 * @}
3576 */ /* end of group PORT_Peripheral_Access_Layer */
3577
3578
3579 /* ----------------------------------------------------------------------------
3580 -- RCM Peripheral Access Layer
3581 ---------------------------------------------------------------------------- */
3582
3583 /**
3584 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
3585 * @{
3586 */
3587
3588 /** RCM - Register Layout Typedef */
3589 typedef struct {
3590 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
3591 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
3592 uint8_t RESERVED_0[2];
3593 __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
3594 __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
3595 uint8_t RESERVED_1[1];
3596 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
3597 } RCM_Type;
3598
3599 /* ----------------------------------------------------------------------------
3600 -- RCM Register Masks
3601 ---------------------------------------------------------------------------- */
3602
3603 /**
3604 * @addtogroup RCM_Register_Masks RCM Register Masks
3605 * @{
3606 */
3607
3608 /* SRS0 Bit Fields */
3609 #define RCM_SRS0_WAKEUP_MASK 0x1u
3610 #define RCM_SRS0_WAKEUP_SHIFT 0
3611 #define RCM_SRS0_LVD_MASK 0x2u
3612 #define RCM_SRS0_LVD_SHIFT 1
3613 #define RCM_SRS0_LOC_MASK 0x4u
3614 #define RCM_SRS0_LOC_SHIFT 2
3615 #define RCM_SRS0_LOL_MASK 0x8u
3616 #define RCM_SRS0_LOL_SHIFT 3
3617 #define RCM_SRS0_WDOG_MASK 0x20u
3618 #define RCM_SRS0_WDOG_SHIFT 5
3619 #define RCM_SRS0_PIN_MASK 0x40u
3620 #define RCM_SRS0_PIN_SHIFT 6
3621 #define RCM_SRS0_POR_MASK 0x80u
3622 #define RCM_SRS0_POR_SHIFT 7
3623 /* SRS1 Bit Fields */
3624 #define RCM_SRS1_JTAG_MASK 0x1u
3625 #define RCM_SRS1_JTAG_SHIFT 0
3626 #define RCM_SRS1_LOCKUP_MASK 0x2u
3627 #define RCM_SRS1_LOCKUP_SHIFT 1
3628 #define RCM_SRS1_SW_MASK 0x4u
3629 #define RCM_SRS1_SW_SHIFT 2
3630 #define RCM_SRS1_MDM_AP_MASK 0x8u
3631 #define RCM_SRS1_MDM_AP_SHIFT 3
3632 #define RCM_SRS1_EZPT_MASK 0x10u
3633 #define RCM_SRS1_EZPT_SHIFT 4
3634 #define RCM_SRS1_SACKERR_MASK 0x20u
3635 #define RCM_SRS1_SACKERR_SHIFT 5
3636 /* RPFC Bit Fields */
3637 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
3638 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
3639 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
3640 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
3641 #define RCM_RPFC_RSTFLTSS_SHIFT 2
3642 /* RPFW Bit Fields */
3643 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
3644 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
3645 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
3646 /* MR Bit Fields */
3647 #define RCM_MR_EZP_MS_MASK 0x2u
3648 #define RCM_MR_EZP_MS_SHIFT 1
3649
3650 /**
3651 * @}
3652 */ /* end of group RCM_Register_Masks */
3653
3654
3655 /* RCM - Peripheral instance base addresses */
3656 /** Peripheral RCM base address */
3657 #define RCM_BASE (0x4007F000u)
3658 /** Peripheral RCM base pointer */
3659 #define RCM ((RCM_Type *)RCM_BASE)
3660
3661 /**
3662 * @}
3663 */ /* end of group RCM_Peripheral_Access_Layer */
3664
3665
3666 /* ----------------------------------------------------------------------------
3667 -- RFSYS Peripheral Access Layer
3668 ---------------------------------------------------------------------------- */
3669
3670 /**
3671 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
3672 * @{
3673 */
3674
3675 /** RFSYS - Register Layout Typedef */
3676 typedef struct {
3677 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
3678 } RFSYS_Type;
3679
3680 /* ----------------------------------------------------------------------------
3681 -- RFSYS Register Masks
3682 ---------------------------------------------------------------------------- */
3683
3684 /**
3685 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
3686 * @{
3687 */
3688
3689 /* REG Bit Fields */
3690 #define RFSYS_REG_LL_MASK 0xFFu
3691 #define RFSYS_REG_LL_SHIFT 0
3692 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
3693 #define RFSYS_REG_LH_MASK 0xFF00u
3694 #define RFSYS_REG_LH_SHIFT 8
3695 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
3696 #define RFSYS_REG_HL_MASK 0xFF0000u
3697 #define RFSYS_REG_HL_SHIFT 16
3698 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
3699 #define RFSYS_REG_HH_MASK 0xFF000000u
3700 #define RFSYS_REG_HH_SHIFT 24
3701 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
3702
3703 /**
3704 * @}
3705 */ /* end of group RFSYS_Register_Masks */
3706
3707
3708 /* RFSYS - Peripheral instance base addresses */
3709 /** Peripheral RFSYS base address */
3710 #define RFSYS_BASE (0x40041000u)
3711 /** Peripheral RFSYS base pointer */
3712 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
3713
3714 /**
3715 * @}
3716 */ /* end of group RFSYS_Peripheral_Access_Layer */
3717
3718
3719 /* ----------------------------------------------------------------------------
3720 -- RFVBAT Peripheral Access Layer
3721 ---------------------------------------------------------------------------- */
3722
3723 /**
3724 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
3725 * @{
3726 */
3727
3728 /** RFVBAT - Register Layout Typedef */
3729 typedef struct {
3730 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
3731 } RFVBAT_Type;
3732
3733 /* ----------------------------------------------------------------------------
3734 -- RFVBAT Register Masks
3735 ---------------------------------------------------------------------------- */
3736
3737 /**
3738 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
3739 * @{
3740 */
3741
3742 /* REG Bit Fields */
3743 #define RFVBAT_REG_LL_MASK 0xFFu
3744 #define RFVBAT_REG_LL_SHIFT 0
3745 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
3746 #define RFVBAT_REG_LH_MASK 0xFF00u
3747 #define RFVBAT_REG_LH_SHIFT 8
3748 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
3749 #define RFVBAT_REG_HL_MASK 0xFF0000u
3750 #define RFVBAT_REG_HL_SHIFT 16
3751 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
3752 #define RFVBAT_REG_HH_MASK 0xFF000000u
3753 #define RFVBAT_REG_HH_SHIFT 24
3754 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
3755
3756 /**
3757 * @}
3758 */ /* end of group RFVBAT_Register_Masks */
3759
3760
3761 /* RFVBAT - Peripheral instance base addresses */
3762 /** Peripheral RFVBAT base address */
3763 #define RFVBAT_BASE (0x4003E000u)
3764 /** Peripheral RFVBAT base pointer */
3765 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
3766
3767 /**
3768 * @}
3769 */ /* end of group RFVBAT_Peripheral_Access_Layer */
3770
3771
3772 /* ----------------------------------------------------------------------------
3773 -- RTC Peripheral Access Layer
3774 ---------------------------------------------------------------------------- */
3775
3776 /**
3777 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
3778 * @{
3779 */
3780
3781 /** RTC - Register Layout Typedef */
3782 typedef struct {
3783 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
3784 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
3785 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
3786 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
3787 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
3788 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
3789 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
3790 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
3791 uint8_t RESERVED_0[2016];
3792 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
3793 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
3794 } RTC_Type;
3795
3796 /* ----------------------------------------------------------------------------
3797 -- RTC Register Masks
3798 ---------------------------------------------------------------------------- */
3799
3800 /**
3801 * @addtogroup RTC_Register_Masks RTC Register Masks
3802 * @{
3803 */
3804
3805 /* TSR Bit Fields */
3806 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
3807 #define RTC_TSR_TSR_SHIFT 0
3808 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
3809 /* TPR Bit Fields */
3810 #define RTC_TPR_TPR_MASK 0xFFFFu
3811 #define RTC_TPR_TPR_SHIFT 0
3812 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
3813 /* TAR Bit Fields */
3814 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
3815 #define RTC_TAR_TAR_SHIFT 0
3816 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
3817 /* TCR Bit Fields */
3818 #define RTC_TCR_TCR_MASK 0xFFu
3819 #define RTC_TCR_TCR_SHIFT 0
3820 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
3821 #define RTC_TCR_CIR_MASK 0xFF00u
3822 #define RTC_TCR_CIR_SHIFT 8
3823 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
3824 #define RTC_TCR_TCV_MASK 0xFF0000u
3825 #define RTC_TCR_TCV_SHIFT 16
3826 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
3827 #define RTC_TCR_CIC_MASK 0xFF000000u
3828 #define RTC_TCR_CIC_SHIFT 24
3829 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
3830 /* CR Bit Fields */
3831 #define RTC_CR_SWR_MASK 0x1u
3832 #define RTC_CR_SWR_SHIFT 0
3833 #define RTC_CR_WPE_MASK 0x2u
3834 #define RTC_CR_WPE_SHIFT 1
3835 #define RTC_CR_SUP_MASK 0x4u
3836 #define RTC_CR_SUP_SHIFT 2
3837 #define RTC_CR_UM_MASK 0x8u
3838 #define RTC_CR_UM_SHIFT 3
3839 #define RTC_CR_OSCE_MASK 0x100u
3840 #define RTC_CR_OSCE_SHIFT 8
3841 #define RTC_CR_CLKO_MASK 0x200u
3842 #define RTC_CR_CLKO_SHIFT 9
3843 #define RTC_CR_SC16P_MASK 0x400u
3844 #define RTC_CR_SC16P_SHIFT 10
3845 #define RTC_CR_SC8P_MASK 0x800u
3846 #define RTC_CR_SC8P_SHIFT 11
3847 #define RTC_CR_SC4P_MASK 0x1000u
3848 #define RTC_CR_SC4P_SHIFT 12
3849 #define RTC_CR_SC2P_MASK 0x2000u
3850 #define RTC_CR_SC2P_SHIFT 13
3851 /* SR Bit Fields */
3852 #define RTC_SR_TIF_MASK 0x1u
3853 #define RTC_SR_TIF_SHIFT 0
3854 #define RTC_SR_TOF_MASK 0x2u
3855 #define RTC_SR_TOF_SHIFT 1
3856 #define RTC_SR_TAF_MASK 0x4u
3857 #define RTC_SR_TAF_SHIFT 2
3858 #define RTC_SR_TCE_MASK 0x10u
3859 #define RTC_SR_TCE_SHIFT 4
3860 /* LR Bit Fields */
3861 #define RTC_LR_TCL_MASK 0x8u
3862 #define RTC_LR_TCL_SHIFT 3
3863 #define RTC_LR_CRL_MASK 0x10u
3864 #define RTC_LR_CRL_SHIFT 4
3865 #define RTC_LR_SRL_MASK 0x20u
3866 #define RTC_LR_SRL_SHIFT 5
3867 #define RTC_LR_LRL_MASK 0x40u
3868 #define RTC_LR_LRL_SHIFT 6
3869 /* IER Bit Fields */
3870 #define RTC_IER_TIIE_MASK 0x1u
3871 #define RTC_IER_TIIE_SHIFT 0
3872 #define RTC_IER_TOIE_MASK 0x2u
3873 #define RTC_IER_TOIE_SHIFT 1
3874 #define RTC_IER_TAIE_MASK 0x4u
3875 #define RTC_IER_TAIE_SHIFT 2
3876 #define RTC_IER_TSIE_MASK 0x10u
3877 #define RTC_IER_TSIE_SHIFT 4
3878 /* WAR Bit Fields */
3879 #define RTC_WAR_TSRW_MASK 0x1u
3880 #define RTC_WAR_TSRW_SHIFT 0
3881 #define RTC_WAR_TPRW_MASK 0x2u
3882 #define RTC_WAR_TPRW_SHIFT 1
3883 #define RTC_WAR_TARW_MASK 0x4u
3884 #define RTC_WAR_TARW_SHIFT 2
3885 #define RTC_WAR_TCRW_MASK 0x8u
3886 #define RTC_WAR_TCRW_SHIFT 3
3887 #define RTC_WAR_CRW_MASK 0x10u
3888 #define RTC_WAR_CRW_SHIFT 4
3889 #define RTC_WAR_SRW_MASK 0x20u
3890 #define RTC_WAR_SRW_SHIFT 5
3891 #define RTC_WAR_LRW_MASK 0x40u
3892 #define RTC_WAR_LRW_SHIFT 6
3893 #define RTC_WAR_IERW_MASK 0x80u
3894 #define RTC_WAR_IERW_SHIFT 7
3895 /* RAR Bit Fields */
3896 #define RTC_RAR_TSRR_MASK 0x1u
3897 #define RTC_RAR_TSRR_SHIFT 0
3898 #define RTC_RAR_TPRR_MASK 0x2u
3899 #define RTC_RAR_TPRR_SHIFT 1
3900 #define RTC_RAR_TARR_MASK 0x4u
3901 #define RTC_RAR_TARR_SHIFT 2
3902 #define RTC_RAR_TCRR_MASK 0x8u
3903 #define RTC_RAR_TCRR_SHIFT 3
3904 #define RTC_RAR_CRR_MASK 0x10u
3905 #define RTC_RAR_CRR_SHIFT 4
3906 #define RTC_RAR_SRR_MASK 0x20u
3907 #define RTC_RAR_SRR_SHIFT 5
3908 #define RTC_RAR_LRR_MASK 0x40u
3909 #define RTC_RAR_LRR_SHIFT 6
3910 #define RTC_RAR_IERR_MASK 0x80u
3911 #define RTC_RAR_IERR_SHIFT 7
3912
3913 /**
3914 * @}
3915 */ /* end of group RTC_Register_Masks */
3916
3917
3918 /* RTC - Peripheral instance base addresses */
3919 /** Peripheral RTC base address */
3920 #define RTC_BASE (0x4003D000u)
3921 /** Peripheral RTC base pointer */
3922 #define RTC ((RTC_Type *)RTC_BASE)
3923
3924 /**
3925 * @}
3926 */ /* end of group RTC_Peripheral_Access_Layer */
3927
3928
3929 /* ----------------------------------------------------------------------------
3930 -- SIM Peripheral Access Layer
3931 ---------------------------------------------------------------------------- */
3932
3933 /**
3934 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
3935 * @{
3936 */
3937
3938 /** SIM - Register Layout Typedef */
3939 typedef struct {
3940 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
3941 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
3942 uint8_t RESERVED_0[4092];
3943 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
3944 uint8_t RESERVED_1[4];
3945 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
3946 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
3947 uint8_t RESERVED_2[4];
3948 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
3949 uint8_t RESERVED_3[8];
3950 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
3951 uint8_t RESERVED_4[12];
3952 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
3953 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
3954 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
3955 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
3956 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
3957 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
3958 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
3959 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
3960 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
3961 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
3962 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
3963 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
3964 } SIM_Type;
3965
3966 /* ----------------------------------------------------------------------------
3967 -- SIM Register Masks
3968 ---------------------------------------------------------------------------- */
3969
3970 /**
3971 * @addtogroup SIM_Register_Masks SIM Register Masks
3972 * @{
3973 */
3974
3975 /* SOPT1 Bit Fields */
3976 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
3977 #define SIM_SOPT1_RAMSIZE_SHIFT 12
3978 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
3979 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
3980 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
3981 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
3982 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
3983 #define SIM_SOPT1_USBVSTBY_SHIFT 29
3984 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
3985 #define SIM_SOPT1_USBSSTBY_SHIFT 30
3986 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
3987 #define SIM_SOPT1_USBREGEN_SHIFT 31
3988 /* SOPT1CFG Bit Fields */
3989 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
3990 #define SIM_SOPT1CFG_URWE_SHIFT 24
3991 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
3992 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
3993 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
3994 #define SIM_SOPT1CFG_USSWE_SHIFT 26
3995 /* SOPT2 Bit Fields */
3996 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
3997 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
3998 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
3999 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
4000 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
4001 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
4002 #define SIM_SOPT2_PTD7PAD_SHIFT 11
4003 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
4004 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
4005 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
4006 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
4007 #define SIM_SOPT2_USBSRC_MASK 0x40000u
4008 #define SIM_SOPT2_USBSRC_SHIFT 18
4009 /* SOPT4 Bit Fields */
4010 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
4011 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
4012 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
4013 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
4014 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
4015 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
4016 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
4017 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
4018 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
4019 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
4020 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
4021 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
4022 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
4023 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
4024 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
4025 /* SOPT5 Bit Fields */
4026 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
4027 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
4028 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
4029 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
4030 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
4031 #define SIM_SOPT5_UART1TXSRC_MASK 0x10u
4032 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
4033 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
4034 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
4035 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
4036 /* SOPT7 Bit Fields */
4037 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
4038 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
4039 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
4040 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
4041 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
4042 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
4043 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
4044 /* SDID Bit Fields */
4045 #define SIM_SDID_PINID_MASK 0xFu
4046 #define SIM_SDID_PINID_SHIFT 0
4047 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
4048 #define SIM_SDID_FAMID_MASK 0x70u
4049 #define SIM_SDID_FAMID_SHIFT 4
4050 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
4051 #define SIM_SDID_REVID_MASK 0xF000u
4052 #define SIM_SDID_REVID_SHIFT 12
4053 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
4054 /* SCGC4 Bit Fields */
4055 #define SIM_SCGC4_EWM_MASK 0x2u
4056 #define SIM_SCGC4_EWM_SHIFT 1
4057 #define SIM_SCGC4_CMT_MASK 0x4u
4058 #define SIM_SCGC4_CMT_SHIFT 2
4059 #define SIM_SCGC4_I2C0_MASK 0x40u
4060 #define SIM_SCGC4_I2C0_SHIFT 6
4061 #define SIM_SCGC4_UART0_MASK 0x400u
4062 #define SIM_SCGC4_UART0_SHIFT 10
4063 #define SIM_SCGC4_UART1_MASK 0x800u
4064 #define SIM_SCGC4_UART1_SHIFT 11
4065 #define SIM_SCGC4_UART2_MASK 0x1000u
4066 #define SIM_SCGC4_UART2_SHIFT 12
4067 #define SIM_SCGC4_USBOTG_MASK 0x40000u
4068 #define SIM_SCGC4_USBOTG_SHIFT 18
4069 #define SIM_SCGC4_CMP_MASK 0x80000u
4070 #define SIM_SCGC4_CMP_SHIFT 19
4071 #define SIM_SCGC4_VREF_MASK 0x100000u
4072 #define SIM_SCGC4_VREF_SHIFT 20
4073 /* SCGC5 Bit Fields */
4074 #define SIM_SCGC5_LPTIMER_MASK 0x1u
4075 #define SIM_SCGC5_LPTIMER_SHIFT 0
4076 #define SIM_SCGC5_TSI_MASK 0x20u
4077 #define SIM_SCGC5_TSI_SHIFT 5
4078 #define SIM_SCGC5_PORTA_MASK 0x200u
4079 #define SIM_SCGC5_PORTA_SHIFT 9
4080 #define SIM_SCGC5_PORTB_MASK 0x400u
4081 #define SIM_SCGC5_PORTB_SHIFT 10
4082 #define SIM_SCGC5_PORTC_MASK 0x800u
4083 #define SIM_SCGC5_PORTC_SHIFT 11
4084 #define SIM_SCGC5_PORTD_MASK 0x1000u
4085 #define SIM_SCGC5_PORTD_SHIFT 12
4086 #define SIM_SCGC5_PORTE_MASK 0x2000u
4087 #define SIM_SCGC5_PORTE_SHIFT 13
4088 /* SCGC6 Bit Fields */
4089 #define SIM_SCGC6_FTFL_MASK 0x1u
4090 #define SIM_SCGC6_FTFL_SHIFT 0
4091 #define SIM_SCGC6_DMAMUX_MASK 0x2u
4092 #define SIM_SCGC6_DMAMUX_SHIFT 1
4093 #define SIM_SCGC6_SPI0_MASK 0x1000u
4094 #define SIM_SCGC6_SPI0_SHIFT 12
4095 #define SIM_SCGC6_I2S_MASK 0x8000u
4096 #define SIM_SCGC6_I2S_SHIFT 15
4097 #define SIM_SCGC6_CRC_MASK 0x40000u
4098 #define SIM_SCGC6_CRC_SHIFT 18
4099 #define SIM_SCGC6_USBDCD_MASK 0x200000u
4100 #define SIM_SCGC6_USBDCD_SHIFT 21
4101 #define SIM_SCGC6_PDB_MASK 0x400000u
4102 #define SIM_SCGC6_PDB_SHIFT 22
4103 #define SIM_SCGC6_PIT_MASK 0x800000u
4104 #define SIM_SCGC6_PIT_SHIFT 23
4105 #define SIM_SCGC6_FTM0_MASK 0x1000000u
4106 #define SIM_SCGC6_FTM0_SHIFT 24
4107 #define SIM_SCGC6_FTM1_MASK 0x2000000u
4108 #define SIM_SCGC6_FTM1_SHIFT 25
4109 #define SIM_SCGC6_ADC0_MASK 0x8000000u
4110 #define SIM_SCGC6_ADC0_SHIFT 27
4111 #define SIM_SCGC6_RTC_MASK 0x20000000u
4112 #define SIM_SCGC6_RTC_SHIFT 29
4113 /* SCGC7 Bit Fields */
4114 #define SIM_SCGC7_DMA_MASK 0x2u
4115 #define SIM_SCGC7_DMA_SHIFT 1
4116 /* CLKDIV1 Bit Fields */
4117 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
4118 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
4119 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
4120 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
4121 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
4122 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
4123 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
4124 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
4125 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
4126 /* CLKDIV2 Bit Fields */
4127 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
4128 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
4129 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
4130 #define SIM_CLKDIV2_USBDIV_SHIFT 1
4131 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
4132 /* FCFG1 Bit Fields */
4133 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
4134 #define SIM_FCFG1_FLASHDIS_SHIFT 0
4135 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
4136 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
4137 #define SIM_FCFG1_DEPART_MASK 0xF00u
4138 #define SIM_FCFG1_DEPART_SHIFT 8
4139 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
4140 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
4141 #define SIM_FCFG1_EESIZE_SHIFT 16
4142 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
4143 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
4144 #define SIM_FCFG1_PFSIZE_SHIFT 24
4145 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
4146 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
4147 #define SIM_FCFG1_NVMSIZE_SHIFT 28
4148 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
4149 /* FCFG2 Bit Fields */
4150 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
4151 #define SIM_FCFG2_MAXADDR1_SHIFT 16
4152 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
4153 #define SIM_FCFG2_PFLSH_MASK 0x800000u
4154 #define SIM_FCFG2_PFLSH_SHIFT 23
4155 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
4156 #define SIM_FCFG2_MAXADDR0_SHIFT 24
4157 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
4158 /* UIDH Bit Fields */
4159 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
4160 #define SIM_UIDH_UID_SHIFT 0
4161 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
4162 /* UIDMH Bit Fields */
4163 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
4164 #define SIM_UIDMH_UID_SHIFT 0
4165 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
4166 /* UIDML Bit Fields */
4167 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
4168 #define SIM_UIDML_UID_SHIFT 0
4169 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
4170 /* UIDL Bit Fields */
4171 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
4172 #define SIM_UIDL_UID_SHIFT 0
4173 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
4174
4175 /**
4176 * @}
4177 */ /* end of group SIM_Register_Masks */
4178
4179
4180 /* SIM - Peripheral instance base addresses */
4181 /** Peripheral SIM base address */
4182 #define SIM_BASE (0x40047000u)
4183 /** Peripheral SIM base pointer */
4184 #define SIM ((SIM_Type *)SIM_BASE)
4185
4186 /**
4187 * @}
4188 */ /* end of group SIM_Peripheral_Access_Layer */
4189
4190
4191 /* ----------------------------------------------------------------------------
4192 -- SMC Peripheral Access Layer
4193 ---------------------------------------------------------------------------- */
4194
4195 /**
4196 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
4197 * @{
4198 */
4199
4200 /** SMC - Register Layout Typedef */
4201 typedef struct {
4202 __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
4203 __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
4204 __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
4205 __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
4206 } SMC_Type;
4207
4208 /* ----------------------------------------------------------------------------
4209 -- SMC Register Masks
4210 ---------------------------------------------------------------------------- */
4211
4212 /**
4213 * @addtogroup SMC_Register_Masks SMC Register Masks
4214 * @{
4215 */
4216
4217 /* PMPROT Bit Fields */
4218 #define SMC_PMPROT_AVLLS_MASK 0x2u
4219 #define SMC_PMPROT_AVLLS_SHIFT 1
4220 #define SMC_PMPROT_ALLS_MASK 0x8u
4221 #define SMC_PMPROT_ALLS_SHIFT 3
4222 #define SMC_PMPROT_AVLP_MASK 0x20u
4223 #define SMC_PMPROT_AVLP_SHIFT 5
4224 /* PMCTRL Bit Fields */
4225 #define SMC_PMCTRL_STOPM_MASK 0x7u
4226 #define SMC_PMCTRL_STOPM_SHIFT 0
4227 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
4228 #define SMC_PMCTRL_STOPA_MASK 0x8u
4229 #define SMC_PMCTRL_STOPA_SHIFT 3
4230 #define SMC_PMCTRL_RUNM_MASK 0x60u
4231 #define SMC_PMCTRL_RUNM_SHIFT 5
4232 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
4233 #define SMC_PMCTRL_LPWUI_MASK 0x80u
4234 #define SMC_PMCTRL_LPWUI_SHIFT 7
4235 /* VLLSCTRL Bit Fields */
4236 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
4237 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
4238 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
4239 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
4240 #define SMC_VLLSCTRL_PORPO_SHIFT 5
4241 /* PMSTAT Bit Fields */
4242 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
4243 #define SMC_PMSTAT_PMSTAT_SHIFT 0
4244 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
4245
4246 /**
4247 * @}
4248 */ /* end of group SMC_Register_Masks */
4249
4250
4251 /* SMC - Peripheral instance base addresses */
4252 /** Peripheral SMC base address */
4253 #define SMC_BASE (0x4007E000u)
4254 /** Peripheral SMC base pointer */
4255 #define SMC ((SMC_Type *)SMC_BASE)
4256
4257 /**
4258 * @}
4259 */ /* end of group SMC_Peripheral_Access_Layer */
4260
4261
4262 /* ----------------------------------------------------------------------------
4263 -- SPI Peripheral Access Layer
4264 ---------------------------------------------------------------------------- */
4265
4266 /**
4267 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
4268 * @{
4269 */
4270
4271 /** SPI - Register Layout Typedef */
4272 typedef struct {
4273 __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
4274 uint8_t RESERVED_0[4];
4275 __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
4276 union { /* offset: 0xC */
4277 __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
4278 __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
4279 };
4280 uint8_t RESERVED_1[24];
4281 __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
4282 __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
4283 union { /* offset: 0x34 */
4284 __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
4285 __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
4286 };
4287 __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
4288 __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
4289 __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
4290 __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
4291 __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
4292 uint8_t RESERVED_2[48];
4293 __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
4294 __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
4295 __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
4296 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
4297 } SPI_Type;
4298
4299 /* ----------------------------------------------------------------------------
4300 -- SPI Register Masks
4301 ---------------------------------------------------------------------------- */
4302
4303 /**
4304 * @addtogroup SPI_Register_Masks SPI Register Masks
4305 * @{
4306 */
4307
4308 /* MCR Bit Fields */
4309 #define SPI_MCR_HALT_MASK 0x1u
4310 #define SPI_MCR_HALT_SHIFT 0
4311 #define SPI_MCR_SMPL_PT_MASK 0x300u
4312 #define SPI_MCR_SMPL_PT_SHIFT 8
4313 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
4314 #define SPI_MCR_CLR_RXF_MASK 0x400u
4315 #define SPI_MCR_CLR_RXF_SHIFT 10
4316 #define SPI_MCR_CLR_TXF_MASK 0x800u
4317 #define SPI_MCR_CLR_TXF_SHIFT 11
4318 #define SPI_MCR_DIS_RXF_MASK 0x1000u
4319 #define SPI_MCR_DIS_RXF_SHIFT 12
4320 #define SPI_MCR_DIS_TXF_MASK 0x2000u
4321 #define SPI_MCR_DIS_TXF_SHIFT 13
4322 #define SPI_MCR_MDIS_MASK 0x4000u
4323 #define SPI_MCR_MDIS_SHIFT 14
4324 #define SPI_MCR_DOZE_MASK 0x8000u
4325 #define SPI_MCR_DOZE_SHIFT 15
4326 #define SPI_MCR_PCSIS_MASK 0x3F0000u
4327 #define SPI_MCR_PCSIS_SHIFT 16
4328 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
4329 #define SPI_MCR_ROOE_MASK 0x1000000u
4330 #define SPI_MCR_ROOE_SHIFT 24
4331 #define SPI_MCR_PCSSE_MASK 0x2000000u
4332 #define SPI_MCR_PCSSE_SHIFT 25
4333 #define SPI_MCR_MTFE_MASK 0x4000000u
4334 #define SPI_MCR_MTFE_SHIFT 26
4335 #define SPI_MCR_FRZ_MASK 0x8000000u
4336 #define SPI_MCR_FRZ_SHIFT 27
4337 #define SPI_MCR_DCONF_MASK 0x30000000u
4338 #define SPI_MCR_DCONF_SHIFT 28
4339 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
4340 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
4341 #define SPI_MCR_CONT_SCKE_SHIFT 30
4342 #define SPI_MCR_MSTR_MASK 0x80000000u
4343 #define SPI_MCR_MSTR_SHIFT 31
4344 /* TCR Bit Fields */
4345 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
4346 #define SPI_TCR_SPI_TCNT_SHIFT 16
4347 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
4348 /* CTAR Bit Fields */
4349 #define SPI_CTAR_BR_MASK 0xFu
4350 #define SPI_CTAR_BR_SHIFT 0
4351 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
4352 #define SPI_CTAR_DT_MASK 0xF0u
4353 #define SPI_CTAR_DT_SHIFT 4
4354 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
4355 #define SPI_CTAR_ASC_MASK 0xF00u
4356 #define SPI_CTAR_ASC_SHIFT 8
4357 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
4358 #define SPI_CTAR_CSSCK_MASK 0xF000u
4359 #define SPI_CTAR_CSSCK_SHIFT 12
4360 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
4361 #define SPI_CTAR_PBR_MASK 0x30000u
4362 #define SPI_CTAR_PBR_SHIFT 16
4363 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
4364 #define SPI_CTAR_PDT_MASK 0xC0000u
4365 #define SPI_CTAR_PDT_SHIFT 18
4366 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
4367 #define SPI_CTAR_PASC_MASK 0x300000u
4368 #define SPI_CTAR_PASC_SHIFT 20
4369 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
4370 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
4371 #define SPI_CTAR_PCSSCK_SHIFT 22
4372 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
4373 #define SPI_CTAR_LSBFE_MASK 0x1000000u
4374 #define SPI_CTAR_LSBFE_SHIFT 24
4375 #define SPI_CTAR_CPHA_MASK 0x2000000u
4376 #define SPI_CTAR_CPHA_SHIFT 25
4377 #define SPI_CTAR_CPOL_MASK 0x4000000u
4378 #define SPI_CTAR_CPOL_SHIFT 26
4379 #define SPI_CTAR_FMSZ_MASK 0x78000000u
4380 #define SPI_CTAR_FMSZ_SHIFT 27
4381 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
4382 #define SPI_CTAR_DBR_MASK 0x80000000u
4383 #define SPI_CTAR_DBR_SHIFT 31
4384 /* CTAR_SLAVE Bit Fields */
4385 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
4386 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
4387 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
4388 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
4389 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
4390 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
4391 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
4392 /* SR Bit Fields */
4393 #define SPI_SR_POPNXTPTR_MASK 0xFu
4394 #define SPI_SR_POPNXTPTR_SHIFT 0
4395 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
4396 #define SPI_SR_RXCTR_MASK 0xF0u
4397 #define SPI_SR_RXCTR_SHIFT 4
4398 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
4399 #define SPI_SR_TXNXTPTR_MASK 0xF00u
4400 #define SPI_SR_TXNXTPTR_SHIFT 8
4401 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
4402 #define SPI_SR_TXCTR_MASK 0xF000u
4403 #define SPI_SR_TXCTR_SHIFT 12
4404 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
4405 #define SPI_SR_RFDF_MASK 0x20000u
4406 #define SPI_SR_RFDF_SHIFT 17
4407 #define SPI_SR_RFOF_MASK 0x80000u
4408 #define SPI_SR_RFOF_SHIFT 19
4409 #define SPI_SR_TFFF_MASK 0x2000000u
4410 #define SPI_SR_TFFF_SHIFT 25
4411 #define SPI_SR_TFUF_MASK 0x8000000u
4412 #define SPI_SR_TFUF_SHIFT 27
4413 #define SPI_SR_EOQF_MASK 0x10000000u
4414 #define SPI_SR_EOQF_SHIFT 28
4415 #define SPI_SR_TXRXS_MASK 0x40000000u
4416 #define SPI_SR_TXRXS_SHIFT 30
4417 #define SPI_SR_TCF_MASK 0x80000000u
4418 #define SPI_SR_TCF_SHIFT 31
4419 /* RSER Bit Fields */
4420 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
4421 #define SPI_RSER_RFDF_DIRS_SHIFT 16
4422 #define SPI_RSER_RFDF_RE_MASK 0x20000u
4423 #define SPI_RSER_RFDF_RE_SHIFT 17
4424 #define SPI_RSER_RFOF_RE_MASK 0x80000u
4425 #define SPI_RSER_RFOF_RE_SHIFT 19
4426 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
4427 #define SPI_RSER_TFFF_DIRS_SHIFT 24
4428 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
4429 #define SPI_RSER_TFFF_RE_SHIFT 25
4430 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
4431 #define SPI_RSER_TFUF_RE_SHIFT 27
4432 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
4433 #define SPI_RSER_EOQF_RE_SHIFT 28
4434 #define SPI_RSER_TCF_RE_MASK 0x80000000u
4435 #define SPI_RSER_TCF_RE_SHIFT 31
4436 /* PUSHR Bit Fields */
4437 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
4438 #define SPI_PUSHR_TXDATA_SHIFT 0
4439 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
4440 #define SPI_PUSHR_PCS_MASK 0x3F0000u
4441 #define SPI_PUSHR_PCS_SHIFT 16
4442 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
4443 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
4444 #define SPI_PUSHR_CTCNT_SHIFT 26
4445 #define SPI_PUSHR_EOQ_MASK 0x8000000u
4446 #define SPI_PUSHR_EOQ_SHIFT 27
4447 #define SPI_PUSHR_CTAS_MASK 0x70000000u
4448 #define SPI_PUSHR_CTAS_SHIFT 28
4449 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
4450 #define SPI_PUSHR_CONT_MASK 0x80000000u
4451 #define SPI_PUSHR_CONT_SHIFT 31
4452 /* PUSHR_SLAVE Bit Fields */
4453 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
4454 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
4455 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
4456 /* POPR Bit Fields */
4457 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
4458 #define SPI_POPR_RXDATA_SHIFT 0
4459 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
4460 /* TXFR0 Bit Fields */
4461 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
4462 #define SPI_TXFR0_TXDATA_SHIFT 0
4463 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
4464 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
4465 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
4466 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
4467 /* TXFR1 Bit Fields */
4468 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
4469 #define SPI_TXFR1_TXDATA_SHIFT 0
4470 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
4471 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
4472 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
4473 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
4474 /* TXFR2 Bit Fields */
4475 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
4476 #define SPI_TXFR2_TXDATA_SHIFT 0
4477 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
4478 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
4479 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
4480 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
4481 /* TXFR3 Bit Fields */
4482 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
4483 #define SPI_TXFR3_TXDATA_SHIFT 0
4484 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
4485 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
4486 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
4487 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
4488 /* RXFR0 Bit Fields */
4489 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
4490 #define SPI_RXFR0_RXDATA_SHIFT 0
4491 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
4492 /* RXFR1 Bit Fields */
4493 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
4494 #define SPI_RXFR1_RXDATA_SHIFT 0
4495 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
4496 /* RXFR2 Bit Fields */
4497 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
4498 #define SPI_RXFR2_RXDATA_SHIFT 0
4499 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
4500 /* RXFR3 Bit Fields */
4501 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
4502 #define SPI_RXFR3_RXDATA_SHIFT 0
4503 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
4504
4505 /**
4506 * @}
4507 */ /* end of group SPI_Register_Masks */
4508
4509
4510 /* SPI - Peripheral instance base addresses */
4511 /** Peripheral SPI0 base address */
4512 #define SPI0_BASE (0x4002C000u)
4513 /** Peripheral SPI0 base pointer */
4514 #define SPI0 ((SPI_Type *)SPI0_BASE)
4515
4516 /**
4517 * @}
4518 */ /* end of group SPI_Peripheral_Access_Layer */
4519
4520
4521 /* ----------------------------------------------------------------------------
4522 -- TSI Peripheral Access Layer
4523 ---------------------------------------------------------------------------- */
4524
4525 /**
4526 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
4527 * @{
4528 */
4529
4530 /** TSI - Register Layout Typedef */
4531 typedef struct {
4532 __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
4533 __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
4534 __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
4535 __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
4536 uint8_t RESERVED_0[240];
4537 __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
4538 __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
4539 __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
4540 __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
4541 __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
4542 __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
4543 __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
4544 __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
4545 __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
4546 } TSI_Type;
4547
4548 /* ----------------------------------------------------------------------------
4549 -- TSI Register Masks
4550 ---------------------------------------------------------------------------- */
4551
4552 /**
4553 * @addtogroup TSI_Register_Masks TSI Register Masks
4554 * @{
4555 */
4556
4557 /* GENCS Bit Fields */
4558 #define TSI_GENCS_STPE_MASK 0x1u
4559 #define TSI_GENCS_STPE_SHIFT 0
4560 #define TSI_GENCS_STM_MASK 0x2u
4561 #define TSI_GENCS_STM_SHIFT 1
4562 #define TSI_GENCS_ESOR_MASK 0x10u
4563 #define TSI_GENCS_ESOR_SHIFT 4
4564 #define TSI_GENCS_ERIE_MASK 0x20u
4565 #define TSI_GENCS_ERIE_SHIFT 5
4566 #define TSI_GENCS_TSIIE_MASK 0x40u
4567 #define TSI_GENCS_TSIIE_SHIFT 6
4568 #define TSI_GENCS_TSIEN_MASK 0x80u
4569 #define TSI_GENCS_TSIEN_SHIFT 7
4570 #define TSI_GENCS_SWTS_MASK 0x100u
4571 #define TSI_GENCS_SWTS_SHIFT 8
4572 #define TSI_GENCS_SCNIP_MASK 0x200u
4573 #define TSI_GENCS_SCNIP_SHIFT 9
4574 #define TSI_GENCS_OVRF_MASK 0x1000u
4575 #define TSI_GENCS_OVRF_SHIFT 12
4576 #define TSI_GENCS_EXTERF_MASK 0x2000u
4577 #define TSI_GENCS_EXTERF_SHIFT 13
4578 #define TSI_GENCS_OUTRGF_MASK 0x4000u
4579 #define TSI_GENCS_OUTRGF_SHIFT 14
4580 #define TSI_GENCS_EOSF_MASK 0x8000u
4581 #define TSI_GENCS_EOSF_SHIFT 15
4582 #define TSI_GENCS_PS_MASK 0x70000u
4583 #define TSI_GENCS_PS_SHIFT 16
4584 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
4585 #define TSI_GENCS_NSCN_MASK 0xF80000u
4586 #define TSI_GENCS_NSCN_SHIFT 19
4587 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
4588 #define TSI_GENCS_LPSCNITV_MASK 0xF000000u
4589 #define TSI_GENCS_LPSCNITV_SHIFT 24
4590 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
4591 #define TSI_GENCS_LPCLKS_MASK 0x10000000u
4592 #define TSI_GENCS_LPCLKS_SHIFT 28
4593 /* SCANC Bit Fields */
4594 #define TSI_SCANC_AMPSC_MASK 0x7u
4595 #define TSI_SCANC_AMPSC_SHIFT 0
4596 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
4597 #define TSI_SCANC_AMCLKS_MASK 0x18u
4598 #define TSI_SCANC_AMCLKS_SHIFT 3
4599 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
4600 #define TSI_SCANC_SMOD_MASK 0xFF00u
4601 #define TSI_SCANC_SMOD_SHIFT 8
4602 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
4603 #define TSI_SCANC_EXTCHRG_MASK 0xF0000u
4604 #define TSI_SCANC_EXTCHRG_SHIFT 16
4605 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
4606 #define TSI_SCANC_REFCHRG_MASK 0xF000000u
4607 #define TSI_SCANC_REFCHRG_SHIFT 24
4608 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
4609 /* PEN Bit Fields */
4610 #define TSI_PEN_PEN0_MASK 0x1u
4611 #define TSI_PEN_PEN0_SHIFT 0
4612 #define TSI_PEN_PEN1_MASK 0x2u
4613 #define TSI_PEN_PEN1_SHIFT 1
4614 #define TSI_PEN_PEN2_MASK 0x4u
4615 #define TSI_PEN_PEN2_SHIFT 2
4616 #define TSI_PEN_PEN3_MASK 0x8u
4617 #define TSI_PEN_PEN3_SHIFT 3
4618 #define TSI_PEN_PEN4_MASK 0x10u
4619 #define TSI_PEN_PEN4_SHIFT 4
4620 #define TSI_PEN_PEN5_MASK 0x20u
4621 #define TSI_PEN_PEN5_SHIFT 5
4622 #define TSI_PEN_PEN6_MASK 0x40u
4623 #define TSI_PEN_PEN6_SHIFT 6
4624 #define TSI_PEN_PEN7_MASK 0x80u
4625 #define TSI_PEN_PEN7_SHIFT 7
4626 #define TSI_PEN_PEN8_MASK 0x100u
4627 #define TSI_PEN_PEN8_SHIFT 8
4628 #define TSI_PEN_PEN9_MASK 0x200u
4629 #define TSI_PEN_PEN9_SHIFT 9
4630 #define TSI_PEN_PEN10_MASK 0x400u
4631 #define TSI_PEN_PEN10_SHIFT 10
4632 #define TSI_PEN_PEN11_MASK 0x800u
4633 #define TSI_PEN_PEN11_SHIFT 11
4634 #define TSI_PEN_PEN12_MASK 0x1000u
4635 #define TSI_PEN_PEN12_SHIFT 12
4636 #define TSI_PEN_PEN13_MASK 0x2000u
4637 #define TSI_PEN_PEN13_SHIFT 13
4638 #define TSI_PEN_PEN14_MASK 0x4000u
4639 #define TSI_PEN_PEN14_SHIFT 14
4640 #define TSI_PEN_PEN15_MASK 0x8000u
4641 #define TSI_PEN_PEN15_SHIFT 15
4642 #define TSI_PEN_LPSP_MASK 0xF0000u
4643 #define TSI_PEN_LPSP_SHIFT 16
4644 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
4645 /* WUCNTR Bit Fields */
4646 #define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
4647 #define TSI_WUCNTR_WUCNT_SHIFT 0
4648 #define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
4649 /* CNTR1 Bit Fields */
4650 #define TSI_CNTR1_CTN1_MASK 0xFFFFu
4651 #define TSI_CNTR1_CTN1_SHIFT 0
4652 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
4653 #define TSI_CNTR1_CTN_MASK 0xFFFF0000u
4654 #define TSI_CNTR1_CTN_SHIFT 16
4655 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
4656 /* CNTR3 Bit Fields */
4657 #define TSI_CNTR3_CTN1_MASK 0xFFFFu
4658 #define TSI_CNTR3_CTN1_SHIFT 0
4659 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
4660 #define TSI_CNTR3_CTN_MASK 0xFFFF0000u
4661 #define TSI_CNTR3_CTN_SHIFT 16
4662 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
4663 /* CNTR5 Bit Fields */
4664 #define TSI_CNTR5_CTN1_MASK 0xFFFFu
4665 #define TSI_CNTR5_CTN1_SHIFT 0
4666 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
4667 #define TSI_CNTR5_CTN_MASK 0xFFFF0000u
4668 #define TSI_CNTR5_CTN_SHIFT 16
4669 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
4670 /* CNTR7 Bit Fields */
4671 #define TSI_CNTR7_CTN1_MASK 0xFFFFu
4672 #define TSI_CNTR7_CTN1_SHIFT 0
4673 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
4674 #define TSI_CNTR7_CTN_MASK 0xFFFF0000u
4675 #define TSI_CNTR7_CTN_SHIFT 16
4676 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
4677 /* CNTR9 Bit Fields */
4678 #define TSI_CNTR9_CTN1_MASK 0xFFFFu
4679 #define TSI_CNTR9_CTN1_SHIFT 0
4680 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
4681 #define TSI_CNTR9_CTN_MASK 0xFFFF0000u
4682 #define TSI_CNTR9_CTN_SHIFT 16
4683 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
4684 /* CNTR11 Bit Fields */
4685 #define TSI_CNTR11_CTN1_MASK 0xFFFFu
4686 #define TSI_CNTR11_CTN1_SHIFT 0
4687 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
4688 #define TSI_CNTR11_CTN_MASK 0xFFFF0000u
4689 #define TSI_CNTR11_CTN_SHIFT 16
4690 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
4691 /* CNTR13 Bit Fields */
4692 #define TSI_CNTR13_CTN1_MASK 0xFFFFu
4693 #define TSI_CNTR13_CTN1_SHIFT 0
4694 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
4695 #define TSI_CNTR13_CTN_MASK 0xFFFF0000u
4696 #define TSI_CNTR13_CTN_SHIFT 16
4697 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
4698 /* CNTR15 Bit Fields */
4699 #define TSI_CNTR15_CTN1_MASK 0xFFFFu
4700 #define TSI_CNTR15_CTN1_SHIFT 0
4701 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
4702 #define TSI_CNTR15_CTN_MASK 0xFFFF0000u
4703 #define TSI_CNTR15_CTN_SHIFT 16
4704 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
4705 /* THRESHOLD Bit Fields */
4706 #define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
4707 #define TSI_THRESHOLD_HTHH_SHIFT 0
4708 #define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
4709 #define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
4710 #define TSI_THRESHOLD_LTHH_SHIFT 16
4711 #define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
4712
4713 /**
4714 * @}
4715 */ /* end of group TSI_Register_Masks */
4716
4717
4718 /* TSI - Peripheral instance base addresses */
4719 /** Peripheral TSI0 base address */
4720 #define TSI0_BASE (0x40045000u)
4721 /** Peripheral TSI0 base pointer */
4722 #define TSI0 ((TSI_Type *)TSI0_BASE)
4723
4724 /**
4725 * @}
4726 */ /* end of group TSI_Peripheral_Access_Layer */
4727
4728
4729 /* ----------------------------------------------------------------------------
4730 -- UART Peripheral Access Layer
4731 ---------------------------------------------------------------------------- */
4732
4733 /**
4734 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
4735 * @{
4736 */
4737
4738 /** UART - Register Layout Typedef */
4739 typedef struct {
4740 __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
4741 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
4742 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
4743 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
4744 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
4745 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
4746 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
4747 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
4748 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
4749 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
4750 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
4751 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
4752 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
4753 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
4754 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
4755 uint8_t RESERVED_0[1];
4756 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
4757 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
4758 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
4759 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
4760 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
4761 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
4762 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
4763 uint8_t RESERVED_1[1];
4764 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
4765 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
4766 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
4767 union { /* offset: 0x1B */
4768 __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
4769 __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
4770 };
4771 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
4772 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
4773 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
4774 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
4775 uint8_t RESERVED_2[1];
4776 __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
4777 __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
4778 __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
4779 __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
4780 __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
4781 __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
4782 __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
4783 __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
4784 __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
4785 __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
4786 __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
4787 __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
4788 __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
4789 __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
4790 __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
4791 __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
4792 __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
4793 } UART_Type;
4794
4795 /* ----------------------------------------------------------------------------
4796 -- UART Register Masks
4797 ---------------------------------------------------------------------------- */
4798
4799 /**
4800 * @addtogroup UART_Register_Masks UART Register Masks
4801 * @{
4802 */
4803
4804 /* BDH Bit Fields */
4805 #define UART_BDH_SBR_MASK 0x1Fu
4806 #define UART_BDH_SBR_SHIFT 0
4807 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
4808 #define UART_BDH_RXEDGIE_MASK 0x40u
4809 #define UART_BDH_RXEDGIE_SHIFT 6
4810 #define UART_BDH_LBKDIE_MASK 0x80u
4811 #define UART_BDH_LBKDIE_SHIFT 7
4812 /* BDL Bit Fields */
4813 #define UART_BDL_SBR_MASK 0xFFu
4814 #define UART_BDL_SBR_SHIFT 0
4815 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
4816 /* C1 Bit Fields */
4817 #define UART_C1_PT_MASK 0x1u
4818 #define UART_C1_PT_SHIFT 0
4819 #define UART_C1_PE_MASK 0x2u
4820 #define UART_C1_PE_SHIFT 1
4821 #define UART_C1_ILT_MASK 0x4u
4822 #define UART_C1_ILT_SHIFT 2
4823 #define UART_C1_WAKE_MASK 0x8u
4824 #define UART_C1_WAKE_SHIFT 3
4825 #define UART_C1_M_MASK 0x10u
4826 #define UART_C1_M_SHIFT 4
4827 #define UART_C1_RSRC_MASK 0x20u
4828 #define UART_C1_RSRC_SHIFT 5
4829 #define UART_C1_UARTSWAI_MASK 0x40u
4830 #define UART_C1_UARTSWAI_SHIFT 6
4831 #define UART_C1_LOOPS_MASK 0x80u
4832 #define UART_C1_LOOPS_SHIFT 7
4833 /* C2 Bit Fields */
4834 #define UART_C2_SBK_MASK 0x1u
4835 #define UART_C2_SBK_SHIFT 0
4836 #define UART_C2_RWU_MASK 0x2u
4837 #define UART_C2_RWU_SHIFT 1
4838 #define UART_C2_RE_MASK 0x4u
4839 #define UART_C2_RE_SHIFT 2
4840 #define UART_C2_TE_MASK 0x8u
4841 #define UART_C2_TE_SHIFT 3
4842 #define UART_C2_ILIE_MASK 0x10u
4843 #define UART_C2_ILIE_SHIFT 4
4844 #define UART_C2_RIE_MASK 0x20u
4845 #define UART_C2_RIE_SHIFT 5
4846 #define UART_C2_TCIE_MASK 0x40u
4847 #define UART_C2_TCIE_SHIFT 6
4848 #define UART_C2_TIE_MASK 0x80u
4849 #define UART_C2_TIE_SHIFT 7
4850 /* S1 Bit Fields */
4851 #define UART_S1_PF_MASK 0x1u
4852 #define UART_S1_PF_SHIFT 0
4853 #define UART_S1_FE_MASK 0x2u
4854 #define UART_S1_FE_SHIFT 1
4855 #define UART_S1_NF_MASK 0x4u
4856 #define UART_S1_NF_SHIFT 2
4857 #define UART_S1_OR_MASK 0x8u
4858 #define UART_S1_OR_SHIFT 3
4859 #define UART_S1_IDLE_MASK 0x10u
4860 #define UART_S1_IDLE_SHIFT 4
4861 #define UART_S1_RDRF_MASK 0x20u
4862 #define UART_S1_RDRF_SHIFT 5
4863 #define UART_S1_TC_MASK 0x40u
4864 #define UART_S1_TC_SHIFT 6
4865 #define UART_S1_TDRE_MASK 0x80u
4866 #define UART_S1_TDRE_SHIFT 7
4867 /* S2 Bit Fields */
4868 #define UART_S2_RAF_MASK 0x1u
4869 #define UART_S2_RAF_SHIFT 0
4870 #define UART_S2_LBKDE_MASK 0x2u
4871 #define UART_S2_LBKDE_SHIFT 1
4872 #define UART_S2_BRK13_MASK 0x4u
4873 #define UART_S2_BRK13_SHIFT 2
4874 #define UART_S2_RWUID_MASK 0x8u
4875 #define UART_S2_RWUID_SHIFT 3
4876 #define UART_S2_RXINV_MASK 0x10u
4877 #define UART_S2_RXINV_SHIFT 4
4878 #define UART_S2_MSBF_MASK 0x20u
4879 #define UART_S2_MSBF_SHIFT 5
4880 #define UART_S2_RXEDGIF_MASK 0x40u
4881 #define UART_S2_RXEDGIF_SHIFT 6
4882 #define UART_S2_LBKDIF_MASK 0x80u
4883 #define UART_S2_LBKDIF_SHIFT 7
4884 /* C3 Bit Fields */
4885 #define UART_C3_PEIE_MASK 0x1u
4886 #define UART_C3_PEIE_SHIFT 0
4887 #define UART_C3_FEIE_MASK 0x2u
4888 #define UART_C3_FEIE_SHIFT 1
4889 #define UART_C3_NEIE_MASK 0x4u
4890 #define UART_C3_NEIE_SHIFT 2
4891 #define UART_C3_ORIE_MASK 0x8u
4892 #define UART_C3_ORIE_SHIFT 3
4893 #define UART_C3_TXINV_MASK 0x10u
4894 #define UART_C3_TXINV_SHIFT 4
4895 #define UART_C3_TXDIR_MASK 0x20u
4896 #define UART_C3_TXDIR_SHIFT 5
4897 #define UART_C3_T8_MASK 0x40u
4898 #define UART_C3_T8_SHIFT 6
4899 #define UART_C3_R8_MASK 0x80u
4900 #define UART_C3_R8_SHIFT 7
4901 /* D Bit Fields */
4902 #define UART_D_RT_MASK 0xFFu
4903 #define UART_D_RT_SHIFT 0
4904 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
4905 /* MA1 Bit Fields */
4906 #define UART_MA1_MA_MASK 0xFFu
4907 #define UART_MA1_MA_SHIFT 0
4908 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
4909 /* MA2 Bit Fields */
4910 #define UART_MA2_MA_MASK 0xFFu
4911 #define UART_MA2_MA_SHIFT 0
4912 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
4913 /* C4 Bit Fields */
4914 #define UART_C4_BRFA_MASK 0x1Fu
4915 #define UART_C4_BRFA_SHIFT 0
4916 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
4917 #define UART_C4_M10_MASK 0x20u
4918 #define UART_C4_M10_SHIFT 5
4919 #define UART_C4_MAEN2_MASK 0x40u
4920 #define UART_C4_MAEN2_SHIFT 6
4921 #define UART_C4_MAEN1_MASK 0x80u
4922 #define UART_C4_MAEN1_SHIFT 7
4923 /* C5 Bit Fields */
4924 #define UART_C5_RDMAS_MASK 0x20u
4925 #define UART_C5_RDMAS_SHIFT 5
4926 #define UART_C5_TDMAS_MASK 0x80u
4927 #define UART_C5_TDMAS_SHIFT 7
4928 /* ED Bit Fields */
4929 #define UART_ED_PARITYE_MASK 0x40u
4930 #define UART_ED_PARITYE_SHIFT 6
4931 #define UART_ED_NOISY_MASK 0x80u
4932 #define UART_ED_NOISY_SHIFT 7
4933 /* MODEM Bit Fields */
4934 #define UART_MODEM_TXCTSE_MASK 0x1u
4935 #define UART_MODEM_TXCTSE_SHIFT 0
4936 #define UART_MODEM_TXRTSE_MASK 0x2u
4937 #define UART_MODEM_TXRTSE_SHIFT 1
4938 #define UART_MODEM_TXRTSPOL_MASK 0x4u
4939 #define UART_MODEM_TXRTSPOL_SHIFT 2
4940 #define UART_MODEM_RXRTSE_MASK 0x8u
4941 #define UART_MODEM_RXRTSE_SHIFT 3
4942 /* IR Bit Fields */
4943 #define UART_IR_TNP_MASK 0x3u
4944 #define UART_IR_TNP_SHIFT 0
4945 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
4946 #define UART_IR_IREN_MASK 0x4u
4947 #define UART_IR_IREN_SHIFT 2
4948 /* PFIFO Bit Fields */
4949 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
4950 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
4951 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
4952 #define UART_PFIFO_RXFE_MASK 0x8u
4953 #define UART_PFIFO_RXFE_SHIFT 3
4954 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
4955 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
4956 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
4957 #define UART_PFIFO_TXFE_MASK 0x80u
4958 #define UART_PFIFO_TXFE_SHIFT 7
4959 /* CFIFO Bit Fields */
4960 #define UART_CFIFO_RXUFE_MASK 0x1u
4961 #define UART_CFIFO_RXUFE_SHIFT 0
4962 #define UART_CFIFO_TXOFE_MASK 0x2u
4963 #define UART_CFIFO_TXOFE_SHIFT 1
4964 #define UART_CFIFO_RXFLUSH_MASK 0x40u
4965 #define UART_CFIFO_RXFLUSH_SHIFT 6
4966 #define UART_CFIFO_TXFLUSH_MASK 0x80u
4967 #define UART_CFIFO_TXFLUSH_SHIFT 7
4968 /* SFIFO Bit Fields */
4969 #define UART_SFIFO_RXUF_MASK 0x1u
4970 #define UART_SFIFO_RXUF_SHIFT 0
4971 #define UART_SFIFO_TXOF_MASK 0x2u
4972 #define UART_SFIFO_TXOF_SHIFT 1
4973 #define UART_SFIFO_RXEMPT_MASK 0x40u
4974 #define UART_SFIFO_RXEMPT_SHIFT 6
4975 #define UART_SFIFO_TXEMPT_MASK 0x80u
4976 #define UART_SFIFO_TXEMPT_SHIFT 7
4977 /* TWFIFO Bit Fields */
4978 #define UART_TWFIFO_TXWATER_MASK 0xFFu
4979 #define UART_TWFIFO_TXWATER_SHIFT 0
4980 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
4981 /* TCFIFO Bit Fields */
4982 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
4983 #define UART_TCFIFO_TXCOUNT_SHIFT 0
4984 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
4985 /* RWFIFO Bit Fields */
4986 #define UART_RWFIFO_RXWATER_MASK 0xFFu
4987 #define UART_RWFIFO_RXWATER_SHIFT 0
4988 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
4989 /* RCFIFO Bit Fields */
4990 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
4991 #define UART_RCFIFO_RXCOUNT_SHIFT 0
4992 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
4993 /* C7816 Bit Fields */
4994 #define UART_C7816_ISO_7816E_MASK 0x1u
4995 #define UART_C7816_ISO_7816E_SHIFT 0
4996 #define UART_C7816_TTYPE_MASK 0x2u
4997 #define UART_C7816_TTYPE_SHIFT 1
4998 #define UART_C7816_INIT_MASK 0x4u
4999 #define UART_C7816_INIT_SHIFT 2
5000 #define UART_C7816_ANACK_MASK 0x8u
5001 #define UART_C7816_ANACK_SHIFT 3
5002 #define UART_C7816_ONACK_MASK 0x10u
5003 #define UART_C7816_ONACK_SHIFT 4
5004 /* IE7816 Bit Fields */
5005 #define UART_IE7816_RXTE_MASK 0x1u
5006 #define UART_IE7816_RXTE_SHIFT 0
5007 #define UART_IE7816_TXTE_MASK 0x2u
5008 #define UART_IE7816_TXTE_SHIFT 1
5009 #define UART_IE7816_GTVE_MASK 0x4u
5010 #define UART_IE7816_GTVE_SHIFT 2
5011 #define UART_IE7816_INITDE_MASK 0x10u
5012 #define UART_IE7816_INITDE_SHIFT 4
5013 #define UART_IE7816_BWTE_MASK 0x20u
5014 #define UART_IE7816_BWTE_SHIFT 5
5015 #define UART_IE7816_CWTE_MASK 0x40u
5016 #define UART_IE7816_CWTE_SHIFT 6
5017 #define UART_IE7816_WTE_MASK 0x80u
5018 #define UART_IE7816_WTE_SHIFT 7
5019 /* IS7816 Bit Fields */
5020 #define UART_IS7816_RXT_MASK 0x1u
5021 #define UART_IS7816_RXT_SHIFT 0
5022 #define UART_IS7816_TXT_MASK 0x2u
5023 #define UART_IS7816_TXT_SHIFT 1
5024 #define UART_IS7816_GTV_MASK 0x4u
5025 #define UART_IS7816_GTV_SHIFT 2
5026 #define UART_IS7816_INITD_MASK 0x10u
5027 #define UART_IS7816_INITD_SHIFT 4
5028 #define UART_IS7816_BWT_MASK 0x20u
5029 #define UART_IS7816_BWT_SHIFT 5
5030 #define UART_IS7816_CWT_MASK 0x40u
5031 #define UART_IS7816_CWT_SHIFT 6
5032 #define UART_IS7816_WT_MASK 0x80u
5033 #define UART_IS7816_WT_SHIFT 7
5034 /* WP7816_T_TYPE0 Bit Fields */
5035 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
5036 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
5037 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
5038 /* WP7816_T_TYPE1 Bit Fields */
5039 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
5040 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
5041 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
5042 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
5043 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
5044 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
5045 /* WN7816 Bit Fields */
5046 #define UART_WN7816_GTN_MASK 0xFFu
5047 #define UART_WN7816_GTN_SHIFT 0
5048 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
5049 /* WF7816 Bit Fields */
5050 #define UART_WF7816_GTFD_MASK 0xFFu
5051 #define UART_WF7816_GTFD_SHIFT 0
5052 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
5053 /* ET7816 Bit Fields */
5054 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
5055 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
5056 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
5057 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
5058 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
5059 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
5060 /* TL7816 Bit Fields */
5061 #define UART_TL7816_TLEN_MASK 0xFFu
5062 #define UART_TL7816_TLEN_SHIFT 0
5063 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
5064 /* C6 Bit Fields */
5065 #define UART_C6_CP_MASK 0x10u
5066 #define UART_C6_CP_SHIFT 4
5067 #define UART_C6_CE_MASK 0x20u
5068 #define UART_C6_CE_SHIFT 5
5069 #define UART_C6_TX709_MASK 0x40u
5070 #define UART_C6_TX709_SHIFT 6
5071 #define UART_C6_EN709_MASK 0x80u
5072 #define UART_C6_EN709_SHIFT 7
5073 /* PCTH Bit Fields */
5074 #define UART_PCTH_PCTH_MASK 0xFFu
5075 #define UART_PCTH_PCTH_SHIFT 0
5076 #define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
5077 /* PCTL Bit Fields */
5078 #define UART_PCTL_PCTL_MASK 0xFFu
5079 #define UART_PCTL_PCTL_SHIFT 0
5080 #define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
5081 /* B1T Bit Fields */
5082 #define UART_B1T_B1T_MASK 0xFFu
5083 #define UART_B1T_B1T_SHIFT 0
5084 #define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
5085 /* SDTH Bit Fields */
5086 #define UART_SDTH_SDTH_MASK 0xFFu
5087 #define UART_SDTH_SDTH_SHIFT 0
5088 #define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
5089 /* SDTL Bit Fields */
5090 #define UART_SDTL_SDTL_MASK 0xFFu
5091 #define UART_SDTL_SDTL_SHIFT 0
5092 #define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
5093 /* PRE Bit Fields */
5094 #define UART_PRE_PREAMBLE_MASK 0xFFu
5095 #define UART_PRE_PREAMBLE_SHIFT 0
5096 #define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
5097 /* TPL Bit Fields */
5098 #define UART_TPL_TPL_MASK 0xFFu
5099 #define UART_TPL_TPL_SHIFT 0
5100 #define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
5101 /* IE Bit Fields */
5102 #define UART_IE_TXFIE_MASK 0x1u
5103 #define UART_IE_TXFIE_SHIFT 0
5104 #define UART_IE_PSIE_MASK 0x2u
5105 #define UART_IE_PSIE_SHIFT 1
5106 #define UART_IE_PCTEIE_MASK 0x4u
5107 #define UART_IE_PCTEIE_SHIFT 2
5108 #define UART_IE_PTXIE_MASK 0x8u
5109 #define UART_IE_PTXIE_SHIFT 3
5110 #define UART_IE_PRXIE_MASK 0x10u
5111 #define UART_IE_PRXIE_SHIFT 4
5112 #define UART_IE_ISDIE_MASK 0x20u
5113 #define UART_IE_ISDIE_SHIFT 5
5114 #define UART_IE_WBEIE_MASK 0x40u
5115 #define UART_IE_WBEIE_SHIFT 6
5116 /* WB Bit Fields */
5117 #define UART_WB_WBASE_MASK 0xFFu
5118 #define UART_WB_WBASE_SHIFT 0
5119 #define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
5120 /* S3 Bit Fields */
5121 #define UART_S3_TXFF_MASK 0x1u
5122 #define UART_S3_TXFF_SHIFT 0
5123 #define UART_S3_PSF_MASK 0x2u
5124 #define UART_S3_PSF_SHIFT 1
5125 #define UART_S3_PCTEF_MASK 0x4u
5126 #define UART_S3_PCTEF_SHIFT 2
5127 #define UART_S3_PTXF_MASK 0x8u
5128 #define UART_S3_PTXF_SHIFT 3
5129 #define UART_S3_PRXF_MASK 0x10u
5130 #define UART_S3_PRXF_SHIFT 4
5131 #define UART_S3_ISD_MASK 0x20u
5132 #define UART_S3_ISD_SHIFT 5
5133 #define UART_S3_WBEF_MASK 0x40u
5134 #define UART_S3_WBEF_SHIFT 6
5135 #define UART_S3_PEF_MASK 0x80u
5136 #define UART_S3_PEF_SHIFT 7
5137 /* S4 Bit Fields */
5138 #define UART_S4_FE_MASK 0x1u
5139 #define UART_S4_FE_SHIFT 0
5140 #define UART_S4_ILCV_MASK 0x2u
5141 #define UART_S4_ILCV_SHIFT 1
5142 #define UART_S4_CDET_MASK 0xCu
5143 #define UART_S4_CDET_SHIFT 2
5144 #define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
5145 #define UART_S4_INITF_MASK 0x10u
5146 #define UART_S4_INITF_SHIFT 4
5147 /* RPL Bit Fields */
5148 #define UART_RPL_RPL_MASK 0xFFu
5149 #define UART_RPL_RPL_SHIFT 0
5150 #define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
5151 /* RPREL Bit Fields */
5152 #define UART_RPREL_RPREL_MASK 0xFFu
5153 #define UART_RPREL_RPREL_SHIFT 0
5154 #define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
5155 /* CPW Bit Fields */
5156 #define UART_CPW_CPW_MASK 0xFFu
5157 #define UART_CPW_CPW_SHIFT 0
5158 #define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
5159 /* RIDT Bit Fields */
5160 #define UART_RIDT_RIDT_MASK 0xFFu
5161 #define UART_RIDT_RIDT_SHIFT 0
5162 #define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
5163 /* TIDT Bit Fields */
5164 #define UART_TIDT_TIDT_MASK 0xFFu
5165 #define UART_TIDT_TIDT_SHIFT 0
5166 #define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
5167
5168 /**
5169 * @}
5170 */ /* end of group UART_Register_Masks */
5171
5172
5173 /* UART - Peripheral instance base addresses */
5174 /** Peripheral UART0 base address */
5175 #define UART0_BASE (0x4006A000u)
5176 /** Peripheral UART0 base pointer */
5177 #define UART0 ((UART_Type *)UART0_BASE)
5178 /** Peripheral UART1 base address */
5179 #define UART1_BASE (0x4006B000u)
5180 /** Peripheral UART1 base pointer */
5181 #define UART1 ((UART_Type *)UART1_BASE)
5182 /** Peripheral UART2 base address */
5183 #define UART2_BASE (0x4006C000u)
5184 /** Peripheral UART2 base pointer */
5185 #define UART2 ((UART_Type *)UART2_BASE)
5186
5187 /**
5188 * @}
5189 */ /* end of group UART_Peripheral_Access_Layer */
5190
5191
5192 /* ----------------------------------------------------------------------------
5193 -- USB Peripheral Access Layer
5194 ---------------------------------------------------------------------------- */
5195
5196 /**
5197 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
5198 * @{
5199 */
5200
5201 /** USB - Register Layout Typedef */
5202 typedef struct {
5203 __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
5204 uint8_t RESERVED_0[3];
5205 __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
5206 uint8_t RESERVED_1[3];
5207 __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
5208 uint8_t RESERVED_2[3];
5209 __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
5210 uint8_t RESERVED_3[3];
5211 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
5212 uint8_t RESERVED_4[3];
5213 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
5214 uint8_t RESERVED_5[3];
5215 __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
5216 uint8_t RESERVED_6[3];
5217 __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
5218 uint8_t RESERVED_7[99];
5219 __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
5220 uint8_t RESERVED_8[3];
5221 __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
5222 uint8_t RESERVED_9[3];
5223 __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
5224 uint8_t RESERVED_10[3];
5225 __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
5226 uint8_t RESERVED_11[3];
5227 __I uint8_t STAT; /**< Status Register, offset: 0x90 */
5228 uint8_t RESERVED_12[3];
5229 __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
5230 uint8_t RESERVED_13[3];
5231 __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
5232 uint8_t RESERVED_14[3];
5233 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
5234 uint8_t RESERVED_15[3];
5235 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
5236 uint8_t RESERVED_16[3];
5237 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
5238 uint8_t RESERVED_17[3];
5239 __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
5240 uint8_t RESERVED_18[3];
5241 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
5242 uint8_t RESERVED_19[3];
5243 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
5244 uint8_t RESERVED_20[3];
5245 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
5246 uint8_t RESERVED_21[11];
5247 struct { /* offset: 0xC0, array step: 0x4 */
5248 __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
5249 uint8_t RESERVED_0[3];
5250 } ENDPOINT[16];
5251 __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
5252 uint8_t RESERVED_22[3];
5253 __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
5254 uint8_t RESERVED_23[3];
5255 __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
5256 uint8_t RESERVED_24[3];
5257 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
5258 uint8_t RESERVED_25[7];
5259 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
5260 } USB_Type;
5261
5262 /* ----------------------------------------------------------------------------
5263 -- USB Register Masks
5264 ---------------------------------------------------------------------------- */
5265
5266 /**
5267 * @addtogroup USB_Register_Masks USB Register Masks
5268 * @{
5269 */
5270
5271 /* PERID Bit Fields */
5272 #define USB_PERID_ID_MASK 0x3Fu
5273 #define USB_PERID_ID_SHIFT 0
5274 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
5275 /* IDCOMP Bit Fields */
5276 #define USB_IDCOMP_NID_MASK 0x3Fu
5277 #define USB_IDCOMP_NID_SHIFT 0
5278 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
5279 /* REV Bit Fields */
5280 #define USB_REV_REV_MASK 0xFFu
5281 #define USB_REV_REV_SHIFT 0
5282 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
5283 /* ADDINFO Bit Fields */
5284 #define USB_ADDINFO_IEHOST_MASK 0x1u
5285 #define USB_ADDINFO_IEHOST_SHIFT 0
5286 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
5287 #define USB_ADDINFO_IRQNUM_SHIFT 3
5288 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
5289 /* OTGISTAT Bit Fields */
5290 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
5291 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
5292 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
5293 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
5294 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
5295 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
5296 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
5297 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
5298 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
5299 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
5300 #define USB_OTGISTAT_IDCHG_MASK 0x80u
5301 #define USB_OTGISTAT_IDCHG_SHIFT 7
5302 /* OTGICR Bit Fields */
5303 #define USB_OTGICR_AVBUSEN_MASK 0x1u
5304 #define USB_OTGICR_AVBUSEN_SHIFT 0
5305 #define USB_OTGICR_BSESSEN_MASK 0x4u
5306 #define USB_OTGICR_BSESSEN_SHIFT 2
5307 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
5308 #define USB_OTGICR_SESSVLDEN_SHIFT 3
5309 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
5310 #define USB_OTGICR_LINESTATEEN_SHIFT 5
5311 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
5312 #define USB_OTGICR_ONEMSECEN_SHIFT 6
5313 #define USB_OTGICR_IDEN_MASK 0x80u
5314 #define USB_OTGICR_IDEN_SHIFT 7
5315 /* OTGSTAT Bit Fields */
5316 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
5317 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
5318 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
5319 #define USB_OTGSTAT_BSESSEND_SHIFT 2
5320 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
5321 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
5322 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
5323 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
5324 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
5325 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
5326 #define USB_OTGSTAT_ID_MASK 0x80u
5327 #define USB_OTGSTAT_ID_SHIFT 7
5328 /* OTGCTL Bit Fields */
5329 #define USB_OTGCTL_OTGEN_MASK 0x4u
5330 #define USB_OTGCTL_OTGEN_SHIFT 2
5331 #define USB_OTGCTL_DMLOW_MASK 0x10u
5332 #define USB_OTGCTL_DMLOW_SHIFT 4
5333 #define USB_OTGCTL_DPLOW_MASK 0x20u
5334 #define USB_OTGCTL_DPLOW_SHIFT 5
5335 #define USB_OTGCTL_DPHIGH_MASK 0x80u
5336 #define USB_OTGCTL_DPHIGH_SHIFT 7
5337 /* ISTAT Bit Fields */
5338 #define USB_ISTAT_USBRST_MASK 0x1u
5339 #define USB_ISTAT_USBRST_SHIFT 0
5340 #define USB_ISTAT_ERROR_MASK 0x2u
5341 #define USB_ISTAT_ERROR_SHIFT 1
5342 #define USB_ISTAT_SOFTOK_MASK 0x4u
5343 #define USB_ISTAT_SOFTOK_SHIFT 2
5344 #define USB_ISTAT_TOKDNE_MASK 0x8u
5345 #define USB_ISTAT_TOKDNE_SHIFT 3
5346 #define USB_ISTAT_SLEEP_MASK 0x10u
5347 #define USB_ISTAT_SLEEP_SHIFT 4
5348 #define USB_ISTAT_RESUME_MASK 0x20u
5349 #define USB_ISTAT_RESUME_SHIFT 5
5350 #define USB_ISTAT_ATTACH_MASK 0x40u
5351 #define USB_ISTAT_ATTACH_SHIFT 6
5352 #define USB_ISTAT_STALL_MASK 0x80u
5353 #define USB_ISTAT_STALL_SHIFT 7
5354 /* INTEN Bit Fields */
5355 #define USB_INTEN_USBRSTEN_MASK 0x1u
5356 #define USB_INTEN_USBRSTEN_SHIFT 0
5357 #define USB_INTEN_ERROREN_MASK 0x2u
5358 #define USB_INTEN_ERROREN_SHIFT 1
5359 #define USB_INTEN_SOFTOKEN_MASK 0x4u
5360 #define USB_INTEN_SOFTOKEN_SHIFT 2
5361 #define USB_INTEN_TOKDNEEN_MASK 0x8u
5362 #define USB_INTEN_TOKDNEEN_SHIFT 3
5363 #define USB_INTEN_SLEEPEN_MASK 0x10u
5364 #define USB_INTEN_SLEEPEN_SHIFT 4
5365 #define USB_INTEN_RESUMEEN_MASK 0x20u
5366 #define USB_INTEN_RESUMEEN_SHIFT 5
5367 #define USB_INTEN_ATTACHEN_MASK 0x40u
5368 #define USB_INTEN_ATTACHEN_SHIFT 6
5369 #define USB_INTEN_STALLEN_MASK 0x80u
5370 #define USB_INTEN_STALLEN_SHIFT 7
5371 /* ERRSTAT Bit Fields */
5372 #define USB_ERRSTAT_PIDERR_MASK 0x1u
5373 #define USB_ERRSTAT_PIDERR_SHIFT 0
5374 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
5375 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
5376 #define USB_ERRSTAT_CRC16_MASK 0x4u
5377 #define USB_ERRSTAT_CRC16_SHIFT 2
5378 #define USB_ERRSTAT_DFN8_MASK 0x8u
5379 #define USB_ERRSTAT_DFN8_SHIFT 3
5380 #define USB_ERRSTAT_BTOERR_MASK 0x10u
5381 #define USB_ERRSTAT_BTOERR_SHIFT 4
5382 #define USB_ERRSTAT_DMAERR_MASK 0x20u
5383 #define USB_ERRSTAT_DMAERR_SHIFT 5
5384 #define USB_ERRSTAT_BTSERR_MASK 0x80u
5385 #define USB_ERRSTAT_BTSERR_SHIFT 7
5386 /* ERREN Bit Fields */
5387 #define USB_ERREN_PIDERREN_MASK 0x1u
5388 #define USB_ERREN_PIDERREN_SHIFT 0
5389 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
5390 #define USB_ERREN_CRC5EOFEN_SHIFT 1
5391 #define USB_ERREN_CRC16EN_MASK 0x4u
5392 #define USB_ERREN_CRC16EN_SHIFT 2
5393 #define USB_ERREN_DFN8EN_MASK 0x8u
5394 #define USB_ERREN_DFN8EN_SHIFT 3
5395 #define USB_ERREN_BTOERREN_MASK 0x10u
5396 #define USB_ERREN_BTOERREN_SHIFT 4
5397 #define USB_ERREN_DMAERREN_MASK 0x20u
5398 #define USB_ERREN_DMAERREN_SHIFT 5
5399 #define USB_ERREN_BTSERREN_MASK 0x80u
5400 #define USB_ERREN_BTSERREN_SHIFT 7
5401 /* STAT Bit Fields */
5402 #define USB_STAT_ODD_MASK 0x4u
5403 #define USB_STAT_ODD_SHIFT 2
5404 #define USB_STAT_TX_MASK 0x8u
5405 #define USB_STAT_TX_SHIFT 3
5406 #define USB_STAT_ENDP_MASK 0xF0u
5407 #define USB_STAT_ENDP_SHIFT 4
5408 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
5409 /* CTL Bit Fields */
5410 #define USB_CTL_USBENSOFEN_MASK 0x1u
5411 #define USB_CTL_USBENSOFEN_SHIFT 0
5412 #define USB_CTL_ODDRST_MASK 0x2u
5413 #define USB_CTL_ODDRST_SHIFT 1
5414 #define USB_CTL_RESUME_MASK 0x4u
5415 #define USB_CTL_RESUME_SHIFT 2
5416 #define USB_CTL_HOSTMODEEN_MASK 0x8u
5417 #define USB_CTL_HOSTMODEEN_SHIFT 3
5418 #define USB_CTL_RESET_MASK 0x10u
5419 #define USB_CTL_RESET_SHIFT 4
5420 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
5421 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
5422 #define USB_CTL_SE0_MASK 0x40u
5423 #define USB_CTL_SE0_SHIFT 6
5424 #define USB_CTL_JSTATE_MASK 0x80u
5425 #define USB_CTL_JSTATE_SHIFT 7
5426 /* ADDR Bit Fields */
5427 #define USB_ADDR_ADDR_MASK 0x7Fu
5428 #define USB_ADDR_ADDR_SHIFT 0
5429 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
5430 #define USB_ADDR_LSEN_MASK 0x80u
5431 #define USB_ADDR_LSEN_SHIFT 7
5432 /* BDTPAGE1 Bit Fields */
5433 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
5434 #define USB_BDTPAGE1_BDTBA_SHIFT 1
5435 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
5436 /* FRMNUML Bit Fields */
5437 #define USB_FRMNUML_FRM_MASK 0xFFu
5438 #define USB_FRMNUML_FRM_SHIFT 0
5439 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
5440 /* FRMNUMH Bit Fields */
5441 #define USB_FRMNUMH_FRM_MASK 0x7u
5442 #define USB_FRMNUMH_FRM_SHIFT 0
5443 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
5444 /* TOKEN Bit Fields */
5445 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
5446 #define USB_TOKEN_TOKENENDPT_SHIFT 0
5447 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
5448 #define USB_TOKEN_TOKENPID_MASK 0xF0u
5449 #define USB_TOKEN_TOKENPID_SHIFT 4
5450 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
5451 /* SOFTHLD Bit Fields */
5452 #define USB_SOFTHLD_CNT_MASK 0xFFu
5453 #define USB_SOFTHLD_CNT_SHIFT 0
5454 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
5455 /* BDTPAGE2 Bit Fields */
5456 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
5457 #define USB_BDTPAGE2_BDTBA_SHIFT 0
5458 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
5459 /* BDTPAGE3 Bit Fields */
5460 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
5461 #define USB_BDTPAGE3_BDTBA_SHIFT 0
5462 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
5463 /* ENDPT Bit Fields */
5464 #define USB_ENDPT_EPHSHK_MASK 0x1u
5465 #define USB_ENDPT_EPHSHK_SHIFT 0
5466 #define USB_ENDPT_EPSTALL_MASK 0x2u
5467 #define USB_ENDPT_EPSTALL_SHIFT 1
5468 #define USB_ENDPT_EPTXEN_MASK 0x4u
5469 #define USB_ENDPT_EPTXEN_SHIFT 2
5470 #define USB_ENDPT_EPRXEN_MASK 0x8u
5471 #define USB_ENDPT_EPRXEN_SHIFT 3
5472 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
5473 #define USB_ENDPT_EPCTLDIS_SHIFT 4
5474 #define USB_ENDPT_RETRYDIS_MASK 0x40u
5475 #define USB_ENDPT_RETRYDIS_SHIFT 6
5476 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
5477 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
5478 /* USBCTRL Bit Fields */
5479 #define USB_USBCTRL_PDE_MASK 0x40u
5480 #define USB_USBCTRL_PDE_SHIFT 6
5481 #define USB_USBCTRL_SUSP_MASK 0x80u
5482 #define USB_USBCTRL_SUSP_SHIFT 7
5483 /* OBSERVE Bit Fields */
5484 #define USB_OBSERVE_DMPD_MASK 0x10u
5485 #define USB_OBSERVE_DMPD_SHIFT 4
5486 #define USB_OBSERVE_DPPD_MASK 0x40u
5487 #define USB_OBSERVE_DPPD_SHIFT 6
5488 #define USB_OBSERVE_DPPU_MASK 0x80u
5489 #define USB_OBSERVE_DPPU_SHIFT 7
5490 /* CONTROL Bit Fields */
5491 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
5492 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
5493 /* USBTRC0 Bit Fields */
5494 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
5495 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
5496 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
5497 #define USB_USBTRC0_SYNC_DET_SHIFT 1
5498 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
5499 #define USB_USBTRC0_USBRESMEN_SHIFT 5
5500 #define USB_USBTRC0_USBRESET_MASK 0x80u
5501 #define USB_USBTRC0_USBRESET_SHIFT 7
5502 /* USBFRMADJUST Bit Fields */
5503 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
5504 #define USB_USBFRMADJUST_ADJ_SHIFT 0
5505 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
5506
5507 /**
5508 * @}
5509 */ /* end of group USB_Register_Masks */
5510
5511
5512 /* USB - Peripheral instance base addresses */
5513 /** Peripheral USB0 base address */
5514 #define USB0_BASE (0x40072000u)
5515 /** Peripheral USB0 base pointer */
5516 #define USB0 ((USB_Type *)USB0_BASE)
5517
5518 /**
5519 * @}
5520 */ /* end of group USB_Peripheral_Access_Layer */
5521
5522
5523 /* ----------------------------------------------------------------------------
5524 -- USBDCD Peripheral Access Layer
5525 ---------------------------------------------------------------------------- */
5526
5527 /**
5528 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
5529 * @{
5530 */
5531
5532 /** USBDCD - Register Layout Typedef */
5533 typedef struct {
5534 __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
5535 __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
5536 __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
5537 uint8_t RESERVED_0[4];
5538 __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
5539 __IO uint32_t TIMER1; /**< , offset: 0x14 */
5540 __IO uint32_t TIMER2; /**< , offset: 0x18 */
5541 } USBDCD_Type;
5542
5543 /* ----------------------------------------------------------------------------
5544 -- USBDCD Register Masks
5545 ---------------------------------------------------------------------------- */
5546
5547 /**
5548 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
5549 * @{
5550 */
5551
5552 /* CONTROL Bit Fields */
5553 #define USBDCD_CONTROL_IACK_MASK 0x1u
5554 #define USBDCD_CONTROL_IACK_SHIFT 0
5555 #define USBDCD_CONTROL_IF_MASK 0x100u
5556 #define USBDCD_CONTROL_IF_SHIFT 8
5557 #define USBDCD_CONTROL_IE_MASK 0x10000u
5558 #define USBDCD_CONTROL_IE_SHIFT 16
5559 #define USBDCD_CONTROL_START_MASK 0x1000000u
5560 #define USBDCD_CONTROL_START_SHIFT 24
5561 #define USBDCD_CONTROL_SR_MASK 0x2000000u
5562 #define USBDCD_CONTROL_SR_SHIFT 25
5563 /* CLOCK Bit Fields */
5564 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
5565 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
5566 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
5567 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
5568 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
5569 /* STATUS Bit Fields */
5570 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
5571 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
5572 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
5573 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
5574 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
5575 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
5576 #define USBDCD_STATUS_ERR_MASK 0x100000u
5577 #define USBDCD_STATUS_ERR_SHIFT 20
5578 #define USBDCD_STATUS_TO_MASK 0x200000u
5579 #define USBDCD_STATUS_TO_SHIFT 21
5580 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
5581 #define USBDCD_STATUS_ACTIVE_SHIFT 22
5582 /* TIMER0 Bit Fields */
5583 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
5584 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
5585 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
5586 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
5587 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
5588 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
5589 /* TIMER1 Bit Fields */
5590 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
5591 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
5592 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
5593 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
5594 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
5595 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
5596 /* TIMER2 Bit Fields */
5597 #define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
5598 #define USBDCD_TIMER2_CHECK_DM_SHIFT 0
5599 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
5600 #define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
5601 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
5602 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
5603
5604 /**
5605 * @}
5606 */ /* end of group USBDCD_Register_Masks */
5607
5608
5609 /* USBDCD - Peripheral instance base addresses */
5610 /** Peripheral USBDCD base address */
5611 #define USBDCD_BASE (0x40035000u)
5612 /** Peripheral USBDCD base pointer */
5613 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
5614
5615 /**
5616 * @}
5617 */ /* end of group USBDCD_Peripheral_Access_Layer */
5618
5619
5620 /* ----------------------------------------------------------------------------
5621 -- VREF Peripheral Access Layer
5622 ---------------------------------------------------------------------------- */
5623
5624 /**
5625 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
5626 * @{
5627 */
5628
5629 /** VREF - Register Layout Typedef */
5630 typedef struct {
5631 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
5632 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
5633 } VREF_Type;
5634
5635 /* ----------------------------------------------------------------------------
5636 -- VREF Register Masks
5637 ---------------------------------------------------------------------------- */
5638
5639 /**
5640 * @addtogroup VREF_Register_Masks VREF Register Masks
5641 * @{
5642 */
5643
5644 /* TRM Bit Fields */
5645 #define VREF_TRM_TRIM_MASK 0x3Fu
5646 #define VREF_TRM_TRIM_SHIFT 0
5647 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
5648 #define VREF_TRM_CHOPEN_MASK 0x40u
5649 #define VREF_TRM_CHOPEN_SHIFT 6
5650 /* SC Bit Fields */
5651 #define VREF_SC_MODE_LV_MASK 0x3u
5652 #define VREF_SC_MODE_LV_SHIFT 0
5653 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
5654 #define VREF_SC_VREFST_MASK 0x4u
5655 #define VREF_SC_VREFST_SHIFT 2
5656 #define VREF_SC_REGEN_MASK 0x40u
5657 #define VREF_SC_REGEN_SHIFT 6
5658 #define VREF_SC_VREFEN_MASK 0x80u
5659 #define VREF_SC_VREFEN_SHIFT 7
5660
5661 /**
5662 * @}
5663 */ /* end of group VREF_Register_Masks */
5664
5665
5666 /* VREF - Peripheral instance base addresses */
5667 /** Peripheral VREF base address */
5668 #define VREF_BASE (0x40074000u)
5669 /** Peripheral VREF base pointer */
5670 #define VREF ((VREF_Type *)VREF_BASE)
5671
5672 /**
5673 * @}
5674 */ /* end of group VREF_Peripheral_Access_Layer */
5675
5676
5677 /* ----------------------------------------------------------------------------
5678 -- WDOG Peripheral Access Layer
5679 ---------------------------------------------------------------------------- */
5680
5681 /**
5682 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
5683 * @{
5684 */
5685
5686 /** WDOG - Register Layout Typedef */
5687 typedef struct {
5688 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
5689 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
5690 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
5691 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
5692 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
5693 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
5694 __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
5695 __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
5696 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
5697 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
5698 __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
5699 __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
5700 } WDOG_Type;
5701
5702 /* ----------------------------------------------------------------------------
5703 -- WDOG Register Masks
5704 ---------------------------------------------------------------------------- */
5705
5706 /**
5707 * @addtogroup WDOG_Register_Masks WDOG Register Masks
5708 * @{
5709 */
5710
5711 /* STCTRLH Bit Fields */
5712 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
5713 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
5714 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
5715 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
5716 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
5717 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
5718 #define WDOG_STCTRLH_WINEN_MASK 0x8u
5719 #define WDOG_STCTRLH_WINEN_SHIFT 3
5720 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
5721 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
5722 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
5723 #define WDOG_STCTRLH_DBGEN_SHIFT 5
5724 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
5725 #define WDOG_STCTRLH_STOPEN_SHIFT 6
5726 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
5727 #define WDOG_STCTRLH_WAITEN_SHIFT 7
5728 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
5729 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
5730 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
5731 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
5732 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
5733 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
5734 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
5735 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
5736 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
5737 /* STCTRLL Bit Fields */
5738 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
5739 #define WDOG_STCTRLL_INTFLG_SHIFT 15
5740 /* TOVALH Bit Fields */
5741 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
5742 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
5743 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
5744 /* TOVALL Bit Fields */
5745 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
5746 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
5747 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
5748 /* WINH Bit Fields */
5749 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
5750 #define WDOG_WINH_WINHIGH_SHIFT 0
5751 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
5752 /* WINL Bit Fields */
5753 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
5754 #define WDOG_WINL_WINLOW_SHIFT 0
5755 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
5756 /* REFRESH Bit Fields */
5757 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
5758 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
5759 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
5760 /* UNLOCK Bit Fields */
5761 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
5762 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
5763 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
5764 /* TMROUTH Bit Fields */
5765 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
5766 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
5767 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
5768 /* TMROUTL Bit Fields */
5769 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
5770 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
5771 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
5772 /* RSTCNT Bit Fields */
5773 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
5774 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
5775 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
5776 /* PRESC Bit Fields */
5777 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
5778 #define WDOG_PRESC_PRESCVAL_SHIFT 8
5779 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
5780
5781 /**
5782 * @}
5783 */ /* end of group WDOG_Register_Masks */
5784
5785
5786 /* WDOG - Peripheral instance base addresses */
5787 /** Peripheral WDOG base address */
5788 #define WDOG_BASE (0x40052000u)
5789 /** Peripheral WDOG base pointer */
5790 #define WDOG ((WDOG_Type *)WDOG_BASE)
5791
5792 /**
5793 * @}
5794 */ /* end of group WDOG_Peripheral_Access_Layer */
5795
5796
5797 /*
5798 ** End of section using anonymous unions
5799 */
5800
5801 #if defined(__ARMCC_VERSION)
5802 #pragma pop
5803 #elif defined(__CWCC__)
5804 #pragma pop
5805 #elif defined(__GNUC__)
5806 /* leave anonymous unions enabled */
5807 #elif defined(__IAR_SYSTEMS_ICC__)
5808 #pragma language=default
5809 #else
5810 #error Not supported compiler type
5811 #endif
5812
5813 /**
5814 * @}
5815 */ /* end of group Peripheral_access_layer */
5816
5817
5818 /* ----------------------------------------------------------------------------
5819 -- Backward Compatibility
5820 ---------------------------------------------------------------------------- */
5821
5822 /**
5823 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
5824 * @{
5825 */
5826
5827 /* No backward compatibility issues. */
5828
5829 /**
5830 * @}
5831 */ /* end of group Backward_Compatibility_Symbols */
5832
5833
5834 #endif /* #if !defined(MK20D5_H_) */
5835
5836 /* MK20D5.h, eof. */
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
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