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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_Freescale / TARGET_KLXX / TARGET_KL43Z / TOOLCHAIN_ARM_STD / startup_MKL43Z4.s
1 ; * ---------------------------------------------------------------------------------------
2 ; * @file: startup_MKL43Z4.s
3 ; * @purpose: CMSIS Cortex-M0P Core Device Startup File
4 ; * MKL43Z4
5 ; * @version: 1.3
6 ; * @date: 2014-8-21
7 ; * @build: b140821
8 ; * ---------------------------------------------------------------------------------------
9 ; *
10 ; * Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc.
11 ; * All rights reserved.
12 ; *
13 ; * Redistribution and use in source and binary forms, with or without modification,
14 ; * are permitted provided that the following conditions are met:
15 ; *
16 ; * o Redistributions of source code must retain the above copyright notice, this list
17 ; * of conditions and the following disclaimer.
18 ; *
19 ; * o Redistributions in binary form must reproduce the above copyright notice, this
20 ; * list of conditions and the following disclaimer in the documentation and/or
21 ; * other materials provided with the distribution.
22 ; *
23 ; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
24 ; * contributors may be used to endorse or promote products derived from this
25 ; * software without specific prior written permission.
26 ; *
27 ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
28 ; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
29 ; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 ; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
31 ; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 ; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 ; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 ; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 ; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 ; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 ; *
38 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
39 ; *
40 ; *****************************************************************************/
41
42
43 __initial_sp EQU 0x20006000 ; Top of RAM
44
45 PRESERVE8
46 THUMB
47
48
49 ; Vector Table Mapped to Address 0 at Reset
50
51 AREA RESET, DATA, READONLY
52 EXPORT __Vectors
53 EXPORT __Vectors_End
54 EXPORT __Vectors_Size
55
56 __Vectors DCD __initial_sp ; Top of Stack
57 DCD Reset_Handler ; Reset Handler
58 DCD NMI_Handler ;NMI Handler
59 DCD HardFault_Handler ;Hard Fault Handler
60 DCD 0 ;Reserved
61 DCD 0 ;Reserved
62 DCD 0 ;Reserved
63 DCD 0 ;Reserved
64 DCD 0 ;Reserved
65 DCD 0 ;Reserved
66 DCD 0 ;Reserved
67 DCD SVC_Handler ;SVCall Handler
68 DCD 0 ;Reserved
69 DCD 0 ;Reserved
70 DCD PendSV_Handler ;PendSV Handler
71 DCD SysTick_Handler ;SysTick Handler
72
73 ;External Interrupts
74 DCD DMA0_IRQHandler ;DMA channel 0 transfer complete
75 DCD DMA1_IRQHandler ;DMA channel 1 transfer complete
76 DCD DMA2_IRQHandler ;DMA channel 2 transfer complete
77 DCD DMA3_IRQHandler ;DMA channel 3 transfer complete
78 DCD Reserved20_IRQHandler ;Reserved interrupt
79 DCD FTFA_IRQHandler ;Command complete and read collision
80 DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
81 DCD LLWU_IRQHandler ;Low leakage wakeup
82 DCD I2C0_IRQHandler ;I2C0 interrupt
83 DCD I2C1_IRQHandler ;I2C1 interrupt
84 DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
85 DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
86 DCD LPUART0_IRQHandler ;LPUART0 status and error
87 DCD LPUART1_IRQHandler ;LPUART1 status and error
88 DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO
89 DCD ADC0_IRQHandler ;ADC0 interrupt
90 DCD CMP0_IRQHandler ;CMP0 interrupt
91 DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
92 DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
93 DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
94 DCD RTC_IRQHandler ;RTC alarm
95 DCD RTC_Seconds_IRQHandler ;RTC seconds
96 DCD PIT_IRQHandler ;PIT interrupt
97 DCD I2S0_IRQHandler ;I2S0 interrupt
98 DCD USB0_IRQHandler ;USB0 interrupt
99 DCD DAC0_IRQHandler ;DAC0 interrupt
100 DCD Reserved42_IRQHandler ;Reserved interrupt
101 DCD Reserved43_IRQHandler ;Reserved interrupt
102 DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
103 DCD LCD_IRQHandler ;LCD interrupt
104 DCD PORTA_IRQHandler ;PORTA Pin detect
105 DCD PORTCD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect
106 __Vectors_End
107
108 __Vectors_Size EQU __Vectors_End - __Vectors
109
110 ; <h> Flash Configuration
111 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
112 ; <i> and security information that allows the MCU to restrict access to the FTFL module.
113 ; <h> Backdoor Comparison Key
114 ; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
115 ; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
116 ; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
117 ; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
118 ; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
119 ; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
120 ; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
121 ; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
122 BackDoorK0 EQU 0xFF
123 BackDoorK1 EQU 0xFF
124 BackDoorK2 EQU 0xFF
125 BackDoorK3 EQU 0xFF
126 BackDoorK4 EQU 0xFF
127 BackDoorK5 EQU 0xFF
128 BackDoorK6 EQU 0xFF
129 BackDoorK7 EQU 0xFF
130 ; </h>
131 ; <h> Program flash protection bytes (FPROT)
132 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
133 ; <i> Each bit protects a 1/32 region of the program flash memory.
134 ; <h> FPROT0
135 ; <i> Program Flash Region Protect Register 0
136 ; <i> 1/32 - 8/32 region
137 ; <o.0> FPROT0.0
138 ; <o.1> FPROT0.1
139 ; <o.2> FPROT0.2
140 ; <o.3> FPROT0.3
141 ; <o.4> FPROT0.4
142 ; <o.5> FPROT0.5
143 ; <o.6> FPROT0.6
144 ; <o.7> FPROT0.7
145 nFPROT0 EQU 0x00
146 FPROT0 EQU nFPROT0:EOR:0xFF
147 ; </h>
148 ; <h> FPROT1
149 ; <i> Program Flash Region Protect Register 1
150 ; <i> 9/32 - 16/32 region
151 ; <o.0> FPROT1.0
152 ; <o.1> FPROT1.1
153 ; <o.2> FPROT1.2
154 ; <o.3> FPROT1.3
155 ; <o.4> FPROT1.4
156 ; <o.5> FPROT1.5
157 ; <o.6> FPROT1.6
158 ; <o.7> FPROT1.7
159 nFPROT1 EQU 0x00
160 FPROT1 EQU nFPROT1:EOR:0xFF
161 ; </h>
162 ; <h> FPROT2
163 ; <i> Program Flash Region Protect Register 2
164 ; <i> 17/32 - 24/32 region
165 ; <o.0> FPROT2.0
166 ; <o.1> FPROT2.1
167 ; <o.2> FPROT2.2
168 ; <o.3> FPROT2.3
169 ; <o.4> FPROT2.4
170 ; <o.5> FPROT2.5
171 ; <o.6> FPROT2.6
172 ; <o.7> FPROT2.7
173 nFPROT2 EQU 0x00
174 FPROT2 EQU nFPROT2:EOR:0xFF
175 ; </h>
176 ; <h> FPROT3
177 ; <i> Program Flash Region Protect Register 3
178 ; <i> 25/32 - 32/32 region
179 ; <o.0> FPROT3.0
180 ; <o.1> FPROT3.1
181 ; <o.2> FPROT3.2
182 ; <o.3> FPROT3.3
183 ; <o.4> FPROT3.4
184 ; <o.5> FPROT3.5
185 ; <o.6> FPROT3.6
186 ; <o.7> FPROT3.7
187 nFPROT3 EQU 0x00
188 FPROT3 EQU nFPROT3:EOR:0xFF
189 ; </h>
190 ; </h>
191 ; <h> Flash nonvolatile option byte (FOPT)
192 ; <i> Allows the user to customize the operation of the MCU at boot time.
193 ; <o.0> LPBOOT0
194 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
195 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
196 ; <o.1> BOOTPIN_OPT
197 ; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
198 ; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
199 ; <o.2> NMI_DIS
200 ; <0=> NMI interrupts are always blocked
201 ; <1=> NMI_b pin/interrupts reset default to enabled
202 ; <o.3> RESET_PIN_CFG
203 ; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
204 ; <1=> RESET_b pin is dedicated
205 ; <o.4> LPBOOT1
206 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
207 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
208 ; <o.5> FAST_INIT
209 ; <0=> Slower initialization
210 ; <1=> Fast Initialization
211 ; <o.6..7> BOOTSRC_SEL
212 ; <0=> Boot from Flash
213 ; <2=> Boot from ROM
214 ; <3=> Boot from ROM
215 ; <i> Boot source selection
216 FOPT EQU 0x3F
217 ; </h>
218 ; <h> Flash security byte (FSEC)
219 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
220 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
221 ; <o.0..1> SEC
222 ; <2=> MCU security status is unsecure
223 ; <3=> MCU security status is secure
224 ; <i> Flash Security
225 ; <o.2..3> FSLACC
226 ; <2=> Freescale factory access denied
227 ; <3=> Freescale factory access granted
228 ; <i> Freescale Failure Analysis Access Code
229 ; <o.4..5> MEEN
230 ; <2=> Mass erase is disabled
231 ; <3=> Mass erase is enabled
232 ; <o.6..7> KEYEN
233 ; <2=> Backdoor key access enabled
234 ; <3=> Backdoor key access disabled
235 ; <i> Backdoor Key Security Enable
236 FSEC EQU 0xFE
237 ; </h>
238 ; </h>
239 IF :LNOT::DEF:RAM_TARGET
240 AREA |.ARM.__at_0x400|, DATA, READONLY
241 __FlashConfig
242 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
243 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
244 DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
245 DCB FSEC , FOPT , 0xFF , 0xFF
246 ENDIF
247
248 AREA |.text|, CODE, READONLY
249
250 ; Reset Handler
251
252 Reset_Handler PROC
253 EXPORT Reset_Handler [WEAK]
254 IMPORT SystemInit
255 IMPORT __main
256 LDR R0, =SystemInit
257 BLX R0
258 LDR R0, =__main
259 BX R0
260 ENDP
261
262
263 ; Dummy Exception Handlers (infinite loops which can be modified)
264 NMI_Handler\
265 PROC
266 EXPORT NMI_Handler [WEAK]
267 B .
268 ENDP
269 HardFault_Handler\
270 PROC
271 EXPORT HardFault_Handler [WEAK]
272 B .
273 ENDP
274 SVC_Handler\
275 PROC
276 EXPORT SVC_Handler [WEAK]
277 B .
278 ENDP
279 PendSV_Handler\
280 PROC
281 EXPORT PendSV_Handler [WEAK]
282 B .
283 ENDP
284 SysTick_Handler\
285 PROC
286 EXPORT SysTick_Handler [WEAK]
287 B .
288 ENDP
289 Default_Handler\
290 PROC
291 EXPORT DMA0_IRQHandler [WEAK]
292 EXPORT DMA1_IRQHandler [WEAK]
293 EXPORT DMA2_IRQHandler [WEAK]
294 EXPORT DMA3_IRQHandler [WEAK]
295 EXPORT Reserved20_IRQHandler [WEAK]
296 EXPORT FTFA_IRQHandler [WEAK]
297 EXPORT PMC_IRQHandler [WEAK]
298 EXPORT LLWU_IRQHandler [WEAK]
299 EXPORT I2C0_IRQHandler [WEAK]
300 EXPORT I2C1_IRQHandler [WEAK]
301 EXPORT SPI0_IRQHandler [WEAK]
302 EXPORT SPI1_IRQHandler [WEAK]
303 EXPORT LPUART0_IRQHandler [WEAK]
304 EXPORT LPUART1_IRQHandler [WEAK]
305 EXPORT UART2_FLEXIO_IRQHandler [WEAK]
306 EXPORT ADC0_IRQHandler [WEAK]
307 EXPORT CMP0_IRQHandler [WEAK]
308 EXPORT TPM0_IRQHandler [WEAK]
309 EXPORT TPM1_IRQHandler [WEAK]
310 EXPORT TPM2_IRQHandler [WEAK]
311 EXPORT RTC_IRQHandler [WEAK]
312 EXPORT RTC_Seconds_IRQHandler [WEAK]
313 EXPORT PIT_IRQHandler [WEAK]
314 EXPORT I2S0_IRQHandler [WEAK]
315 EXPORT USB0_IRQHandler [WEAK]
316 EXPORT DAC0_IRQHandler [WEAK]
317 EXPORT Reserved42_IRQHandler [WEAK]
318 EXPORT Reserved43_IRQHandler [WEAK]
319 EXPORT LPTMR0_IRQHandler [WEAK]
320 EXPORT LCD_IRQHandler [WEAK]
321 EXPORT PORTA_IRQHandler [WEAK]
322 EXPORT PORTCD_IRQHandler [WEAK]
323 EXPORT DefaultISR [WEAK]
324 DMA0_IRQHandler
325 DMA1_IRQHandler
326 DMA2_IRQHandler
327 DMA3_IRQHandler
328 Reserved20_IRQHandler
329 FTFA_IRQHandler
330 PMC_IRQHandler
331 LLWU_IRQHandler
332 I2C0_IRQHandler
333 I2C1_IRQHandler
334 SPI0_IRQHandler
335 SPI1_IRQHandler
336 LPUART0_IRQHandler
337 LPUART1_IRQHandler
338 UART2_FLEXIO_IRQHandler
339 ADC0_IRQHandler
340 CMP0_IRQHandler
341 TPM0_IRQHandler
342 TPM1_IRQHandler
343 TPM2_IRQHandler
344 RTC_IRQHandler
345 RTC_Seconds_IRQHandler
346 PIT_IRQHandler
347 I2S0_IRQHandler
348 USB0_IRQHandler
349 DAC0_IRQHandler
350 Reserved42_IRQHandler
351 Reserved43_IRQHandler
352 LPTMR0_IRQHandler
353 LCD_IRQHandler
354 PORTA_IRQHandler
355 PORTCD_IRQHandler
356 DefaultISR
357 B .
358 ENDP
359 ALIGN
360
361
362 END
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