tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h

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  33
  34 #ifndef _MXC_TMR_REGS_H
  35 #define _MXC_TMR_REGS_H
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  tmr_regs.h
  45  * @addtogroup tmr TMR
  46  * @{
  47  */
  48
  49 /**
  50  * @brief Defines timer modes for 16 and 32-bit timers
  51  */
  52 typedef enum {
  53     /** 32-bit or 16-bit timer one-shot mode */
  54     MXC_E_TMR_MODE_ONE_SHOT = 0,
  55     /** 32-bit or 16-bit timer one-shot mode */
  56     MXC_E_TMR_MODE_CONTINUOUS,
  57     /** 32-bit timer counter mode */
  58     MXC_E_TMR_MODE_COUNTER,
  59     /** 32-bit timer pulse width modulation mode */
  60     MXC_E_TMR_MODE_PWM,
  61     /** 32-bit timer capture mode */
  62     MXC_E_TMR_MODE_CAPTURE,
  63     /** 32-bit timer compare mode */
  64     MXC_E_TMR_MODE_COMPARE,
  65     /** 32-bit timer gated mode */
  66     MXC_E_TMR_MODE_GATED,
  67     /** 32-bit timer measure mode */
  68     MXC_E_TMR_MODE_MEASURE
  69 } mxc_tmr_mode_t;
  70
  71 /*                                          Offset   Register Description
  72                                             ======   ============================================== */
  73 typedef struct {
  74     __IO uint32_t ctrl;                 /*  0x0000   Timer Control Register                         */
  75     __IO uint32_t count32;              /*  0x0004   [32 bit] Current Count Value                   */
  76     __IO uint32_t term_cnt32;           /*  0x0008   [32 bit] Terminal Count Setting                */
  77     __IO uint32_t pwm_cap32;            /*  0x000C   [32 bit] PWM Compare Setting or Capture/Measure Value */
  78     __IO uint32_t count16_0;            /*  0x0010   [16 bit] Current Count Value, 16-bit Timer0    */
  79     __IO uint32_t term_cnt16_0;         /*  0x0014   [16 bit] Terminal Count Setting, 16-bit Timer0 */
  80     __IO uint32_t count16_1;            /*  0x0018   [16 bit] Current Count Value, 16-bit Timer1    */
  81     __IO uint32_t term_cnt16_1;         /*  0x001C   [16 bit] Terminal Count Setting, 16-bit Timer1 */
  82     __IO uint32_t intfl;                /*  0x0020   Timer Module Interrupt Flags                   */
  83     __IO uint32_t inten;                /*  0x0024   Timer Module Interrupt Enable/Disable Settings */
  84 } mxc_tmr_regs_t;
  85
  86 /*
  87    Register offsets for module TMR.
  88 */
  89 #define MXC_R_TMR_OFFS_CTRL                       ((uint32_t)0x00000000UL)
  90 #define MXC_R_TMR_OFFS_COUNT32                    ((uint32_t)0x00000004UL)
  91 #define MXC_R_TMR_OFFS_TERM_CNT32                 ((uint32_t)0x00000008UL)
  92 #define MXC_R_TMR_OFFS_PWM_CAP32                  ((uint32_t)0x0000000CUL)
  93 #define MXC_R_TMR_OFFS_COUNT16_0                  ((uint32_t)0x00000010UL)
  94 #define MXC_R_TMR_OFFS_TERM_CNT16_0               ((uint32_t)0x00000014UL)
  95 #define MXC_R_TMR_OFFS_COUNT16_1                  ((uint32_t)0x00000018UL)
  96 #define MXC_R_TMR_OFFS_TERM_CNT16_1               ((uint32_t)0x0000001CUL)
  97 #define MXC_R_TMR_OFFS_INTFL                      ((uint32_t)0x00000020UL)
  98 #define MXC_R_TMR_OFFS_INTEN                      ((uint32_t)0x00000024UL)
  99
 100 /*
 101    Field positions and masks for module TMR.
 102 */
 103 #define MXC_F_TMR_CTRL_MODE_POS                             0
 104 #define MXC_F_TMR_CTRL_MODE                                 ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
 105 #define MXC_F_TMR_CTRL_TMR2X16_POS                          3
 106 #define MXC_F_TMR_CTRL_TMR2X16                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
 107 #define MXC_F_TMR_CTRL_PRESCALE_POS                         4
 108 #define MXC_F_TMR_CTRL_PRESCALE                             ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
 109 #define MXC_F_TMR_CTRL_POLARITY_POS                         8
 110 #define MXC_F_TMR_CTRL_POLARITY                             ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
 111 #define MXC_F_TMR_CTRL_ENABLE0_POS                          12
 112 #define MXC_F_TMR_CTRL_ENABLE0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
 113 #define MXC_F_TMR_CTRL_ENABLE1_POS                          13
 114 #define MXC_F_TMR_CTRL_ENABLE1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
 115
 116 #define MXC_F_TMR_COUNT16_0_VALUE_POS                       0
 117 #define MXC_F_TMR_COUNT16_0_VALUE                           ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
 118
 119 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS               0
 120 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT                   ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
 121
 122 #define MXC_F_TMR_COUNT16_1_VALUE_POS                       0
 123 #define MXC_F_TMR_COUNT16_1_VALUE                           ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
 124
 125 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS               0
 126 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT                   ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
 127
 128 #define MXC_F_TMR_INTFL_TIMER0_POS                          0
 129 #define MXC_F_TMR_INTFL_TIMER0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
 130 #define MXC_F_TMR_INTFL_TIMER1_POS                          1
 131 #define MXC_F_TMR_INTFL_TIMER1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
 132
 133 #define MXC_F_TMR_INTEN_TIMER0_POS                          0
 134 #define MXC_F_TMR_INTEN_TIMER0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
 135 #define MXC_F_TMR_INTEN_TIMER1_POS                          1
 136 #define MXC_F_TMR_INTEN_TIMER1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
 137
 138 #ifdef __cplusplus
 139 }
 140 #endif
 141
 142 /**
 143 * @}
 144 */
 145
 146 #endif /* _MXC_TMR_REGS_H */