25#define SYSPLLCTRL_MSEL_MASK 0x001F// Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.
73#define SYSAHBCLKCTRL_SYS (1 << 0)// Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.
74#define SYSAHBCLKCTRL_ROM (1 << 1)// Enables clock for ROM.
75#define SYSAHBCLKCTRL_RAM (1 << 2)// Enables clock for RAM.
158#define NMISRC_IRQNO_MASK 0x001F// The IRQ number of the interrupt that acts as the Non-Maskable Interrupt 0 (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers.
165#define STARTAPRP0_APRPIO1_0 (1 << 12)// Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge Reserved. Do not write a 1 to reserved bits in this register.
170#define STARTERP0_ERPIO1_0 (1 << 12)// Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled Reserved. Do not write a 1 to reserved bits in this register.
173#define STARTRSRP0CLR_RSRPIO0_N_MASK 0x0FFF// Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
178#define STARTSRP0_SRPIO0_N_MASK 0x0FFF// Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.
311#define IOCON_PIO0_4_I2CMODE_MASK 0x0300// Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
317#define IOCON_PIO0_5_I2CMODE_MASK 0x0300// Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
511#define IOCON_PIO1_4_FUNC_MASK 0x0007// Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
667#define IOCON_PIO0_4_I2CMODE_MASK 0x0300// Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
673#define IOCON_PIO0_5_I2CMODE_MASK 0x0300// Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
867#define IOCON_PIO1_4_FUNC_MASK 0x0007// Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
969#define GPIO0DIR_IO_MASK 0x0FFF// Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
973#define GPIO0IS_ISENSE_MASK 0x0FFF// Selects interrupt on pin x as level or edge sensitive (x = 0 to 0x00 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
977#define GPIO0IBE_IBE_MASK 0x0FFF// Selects interrupt on pin x to be triggered on both edges (x = 0 0x00 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
981#define GPIO0IEV_IEV_MASK 0x0FFF// Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 175), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 175), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
985#define GPIO0IE_MASK_MASK 0x0FFF// Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
993#define GPIO0MIS_MASK_MASK 0x0FFF// Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
997#define GPIO0IC_CLR_MASK 0x0FFF// Selects interrupt on pin x to be cleared (x = 0 to 11). Clears 0x00 the interrupt edge detection logic. This register is write-only. Remark: The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
1001#define U0IIR_INTSTATUS (1 << 0)// Interrupt status. Note that U0IIR[0] is active low. The pending interrupt can be determined by evaluating U0IIR[3:1].
1002#define U0IIR_INTID_MASK 0x000E// Interrupt identification. U0IER[3:1] identifies an interrupt 0 corresponding to the UART Rx FIFO. All other combinations of U0IER[3:1] not listed below are reserved (100,101,111).
1006#define U0IIR_ABEOINT (1 << 8)// End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
1007#define U0IIR_ABTOINT (1 << 9)// Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
1013#define U0FCR_RXTL_MASK 0x00C0// RX Trigger Level. These two bits determine how many 0 receiver UART FIFO characters must be written before an interrupt is activated.
1021#define U0LCR_PS_MASK 0x0030// Parity Select 0x0 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x2 Forced 1 stick parity. 0x3 Forced 0 stick parity.
1027#define U0MCR_DTRC (1 << 0)// DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
1028#define U0MCR_RTSC (1 << 1)// RTS Control. Source for modem output pin RTS. This bit reads as 0 0 when modem loopback mode is active.
1029#define U0MCR_LMS (1 << 4)// Loopback Mode Select. The modem loopback mode provides a 0 mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the U0MSR will be driven by the lower four bits of the U0MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of U0MCR.
1030#define U0MCR_RTSEN (1 << 6)// RTS flow control
1031#define U0MCR_CTSEN (1 << 7)// CTS flow control
1034#define U0LSR_RDR (1 << 0)// Receiver Data Ready. U0LSR[0] is set when the U0RBR holds 0 an unread character and is cleared when the UART RBR FIFO is empty.
1035#define U0LSR_OE (1 << 1)// Overrun Error. The overrun error condition is set as soon as it 0 occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
1036#define U0LSR_PE (1 << 2)// Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
1037#define U0LSR_FE (1 << 3)// Framing Error. When the stop bit of a received character is a 0 logic 0, a framing error occurs. A U0LSR read clears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
1038#define U0LSR_BI (1 << 4)// Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A U0LSR read clears this status bit. The time of break detection is dependent on U0FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
1039#define U0LSR_THRE (1 << 5)// Transmitter Holding Register Empty. THRE is set immediately 1 upon detection of an empty UART THR and is cleared on a U0THR write.
1040#define U0LSR_TEMT (1 << 6)// Transmitter Empty. TEMT is set when both U0THR and 1 U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. This bit is updated as soon as 50 % of the first stop bit has been transmitted or a byte has been written into the THR.
1041#define U0LSR_RXFE (1 << 7)// Error in RX FIFO. U0LSR[7] is set when a character with a RX 0 error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART FIFO.
1044#define U0MSR_DCTS (1 << 0)// Delta CTS. Set upon state change of input CTS. Cleared on a U0MSR read. 0 No change detected on modem input CTS. 1 State change detected on modem input CTS.
1045#define U0MSR_DDSR (1 << 1)// Delta DSR. Set upon state change of input DSR. Cleared on a U0MSR read. 0 No change detected on modem input DSR. 1 State change detected on modem input DSR.
1046#define U0MSR_TERI (1 << 2)// Trailing Edge RI. Set upon low to high transition of input RI. Cleared 0 on a U0MSR read. 0 No change detected on modem input, RI. 1 Low-to-high transition detected on RI.
1047#define U0MSR_DDCD (1 << 3)// Delta DCD. Set upon state change of input DCD. Cleared on a U0MSR read. 0 No change detected on modem input DCD. 1 State change detected on modem input DCD.
1048#define U0MSR_CTS (1 << 4)// Clear To Send State. Complement of input signal CTS. This bit is connected to U0MCR[1] in modem loopback mode.
1049#define U0MSR_DSR (1 << 5)// Data Set Ready State. Complement of input signal DSR. This bit is connected to U0MCR[0] in modem loopback mode.
1050#define U0MSR_RI (1 << 6)// Ring Indicator State. Complement of input RI. This bit is connected to U0MCR[2] in modem loopback mode.
1051#define U0MSR_DCD (1 << 7)// Data Carrier Detect State. Complement of input DCD. This bit is connected to U0MCR[3] in modem loopback mode.
1065#define U0TER_TXEN (1 << 7)// When this bit is 1, as it is after a Reset, data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. Reserved
1080#define U0RS485DLY_DLY_MASK 0x00FF// Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
1084#define SSP0CR0_DSS_MASK 0x000F// Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
1088#define SSP0CR0_CPOL (1 << 6)// Clock Out Polarity. This bit is only used in SPI mode.
1089#define SSP0CR0_CPHA (1 << 7)// Clock Out Phase. This bit is only used in SPI mode.
1090#define SSP0CR0_SCR_MASK 0xFF00// Serial Clock Rate. The number of prescaler output clocks per 0x00 bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR [SCR+1]). Reserved
1096#define SSP0CR1_MS (1 << 2)// Master/Slave Mode.This bit can only be written when the SSE bit is 0.
1097#define SSP0CR1_SOD (1 << 3)// Slave Output Disable. This bit is relevant only in slave 0 mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).
1100#define SSP0DR_DATA_MASK 0xFFFF// Write: software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. Reserved.
1104#define SSP0SR_TFE (1 << 0)// Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
1105#define SSP0SR_TNF (1 << 1)// Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
1106#define SSP0SR_RNE (1 << 2)// Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
1107#define SSP0SR_RFF (1 << 3)// Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
1108#define SSP0SR_BSY (1 << 4)// Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
1111#define SSP0CPSR_CPSDVSR_MASK 0x00FF// This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
1115#define SSP0IMSC_RORIM (1 << 0)// Software should set this bit to enable interrupt when a Receive 0 Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
1116#define SSP0IMSC_RTIM (1 << 1)// Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
1117#define SSP0IMSC_RXIM (1 << 2)// Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full.
1118#define SSP0IMSC_TXIM (1 << 3)// Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty.
1121#define SSP0RIS_RORRIS (1 << 0)// This bit is 1 if another frame was completely received while the 0 RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
1122#define SSP0RIS_RTRIS (1 << 1)// This bit is 1 if the Rx FIFO is not empty, and has not been read 0 for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
1123#define SSP0RIS_RXRIS (1 << 2)// This bit is 1 if the Rx FIFO is at least half full.
1124#define SSP0RIS_TXRIS (1 << 3)// This bit is 1 if the Tx FIFO is at least half empty.
1127#define SSP0MIS_RORMIS (1 << 0)// This bit is 1 if another frame was completely received while the 0 RxFIFO was full, and this interrupt is enabled.
1128#define SSP0MIS_RTMIS (1 << 1)// This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
1129#define SSP0MIS_RXMIS (1 << 2)// This bit is 1 if the Rx FIFO is at least half full, and this interrupt 0 is enabled.
1130#define SSP0MIS_TXMIS (1 << 3)// This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
1133#define SSP0ICR_RORIC (1 << 0)// Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt.
1134#define SSP0ICR_RTIC (1 << 1)// Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
1144#define I2C0STAT_STATUS_MASK 0x00F8// These bits give the actual status information about the I2 C interface. Reserved. The value read from a reserved bit is not defined.
1148#define I2C0DAT_DATA_MASK 0x00FF// This register holds data values that have been received or are to 0 be transmitted. Reserved. The value read from a reserved bit is not defined.
1175#define I2C0DATA_BUFFER_DATA_MASK 0x00FF// This register holds contents of the 8 MSBs of the DAT shift register. Reserved. The value read from a reserved bit is not defined.
1188#define CANSTAT_LEC_MASK 0x0007// Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to `0' when a message has been transferred (reception or transmission) without error. The unused code `111' may be written by the CPU to check for updates.
1204#define CANBT_BRP_MASK 0x003F// Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1]
1226#define CANBRPE_BRPE_MASK 0x000F// Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.
1230#define CANIFn_CMDREQ_MN_MASK 0x003F// Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]
1243#define CANIFn_CMDMSK_WR (1 << 7)// Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
1244#define CANIFn_CMDMSK_RD (0 << 7)// Read transfer Read data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
1265#define CANIFn_ARB2_MSGVAL (1 << 15)// Message valid Remark: The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.
1268#define CANIFn_MCTRL_DLC_MASK 0x000F// Data length code Remark: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.
1275#define CANIFn_MCTRL_UMASK (1 << 12)// Use acceptance mask Remark: If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.
1305#define CANTXREQ1_TXRQST_MASK 0xFFFF// Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
1309#define CANTXREQ2_TXRQST_MASK 0xFFFF// Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
1313#define CANND1_NEWDAT_MASK 0xFFFF// New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
1317#define CANND2_NEWDAT_MASK 0xFFFF// New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
1321#define CANIR1_INTPND_INTERRUPT_MASK 0xFFFF// pending bits of message objects 16 to 1. essage object is ignored by the message essage object is the source of an interrupt. Reserved
1325#define CANIR2_INTPND_MASK 0xFFFF// Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. Reserved
1329#define CANMSGV1_MSGVAL_MASK 0xFFFF// Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
1333#define CANMSGV2_MSGVAL_MASK 0xFFFF// Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
1348#define TMR16B0TCR_CEN (1 << 0)// Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
1349#define TMR16B0TCR_CRST (1 << 1)// Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
1382#define TMR16B0CCR_CAP0RE (1 << 0)// Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
1383#define TMR16B0CCR_CAP0FE (1 << 1)// Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
1384#define TMR16B0CCR_CAP0I (1 << 2)// Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1391#define TMR16B0EMR_EM0 (1 << 0)// External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1392#define TMR16B0EMR_EM1 (1 << 1)// External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1393#define TMR16B0EMR_EM2 (1 << 2)// External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1394#define TMR16B0EMR_EM3 (1 << 3)// External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
1395#define TMR16B0EMR_EMC0_MASK 0x0030// External Match Control 0. Determines the functionality of External Match 0.
1405#define TMR16B0CTCR_CTM_MASK 0x0003// Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
1412#define TMR16B0PWMC_PWMEN3 (1 << 3)// PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
1423#define TMR16B0TCR_CEN (1 << 0)// Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
1424#define TMR16B0TCR_CRST (1 << 1)// Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
1457#define TMR16B0CCR_CAP0RE (1 << 0)// Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
1458#define TMR16B0CCR_CAP0FE (1 << 1)// Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
1459#define TMR16B0CCR_CAP0I (1 << 2)// Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
1460#define TMR16B0CCR_CAP1RE (1 << 3)// Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
1461#define TMR16B0CCR_CAP1FE (1 << 4)// Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
1462#define TMR16B0CCR_CAP1I (1 << 5)// Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.
1465#define TMR16B0EMR_EM0 (1 << 0)// External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1466#define TMR16B0EMR_EM1 (1 << 1)// External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1467#define TMR16B0EMR_EM2 (1 << 2)// External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1468#define TMR16B0EMR_EM3 (1 << 3)// External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
1469#define TMR16B0EMR_EMC0_MASK 0x0030// External Match Control 0. Determines the functionality of External Match 0.
1479#define TMR16B0CTCR_CTM_MASK 0x0003// Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
1481#define TMR16B0CTCR_SELCC_MASK 0x00E0// When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
1488#define TMR16B0PWMC_PWMEN3 (1 << 3)// PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
1498#define TMR32B0TCR_CEN (1 << 0)// When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
1499#define TMR32B0TCR_CRST (1 << 1)// When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
1532#define TMR32B0CCR_CAP0RE (1 << 0)// Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
1533#define TMR32B0CCR_CAP0FE (1 << 1)// Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
1534#define TMR32B0CCR_CAP0I (1 << 2)// Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
1541#define TMR32B0EMR_EM0 (1 << 0)// External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1542#define TMR32B0EMR_EM1 (1 << 1)// External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1543#define TMR32B0EMR_EM2 (1 << 2)// External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1544#define TMR32B0EMR_EM3 (1 << 3)// External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1545#define TMR32B0EMR_EMC0_MASK 0x0030// External Match Control 0. Determines the functionality of External Match 0.
1555#define TMR32B0CTCR_CTM_MASK 0x0003// Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
1557#define TMR32B0CTCR_CIS_MASK 0x000C// Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
1575#define TMR32B0TCR_CEN (1 << 0)// When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
1576#define TMR32B0TCR_CRST (1 << 1)// When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
1609#define TMR32B0CCR_CAP0RE (1 << 0)// Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
1610#define TMR32B0CCR_CAP0FE (1 << 1)// Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
1611#define TMR32B0CCR_CAP0I (1 << 2)// Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
1612#define TMR32B0CCR_CAP1RE (1 << 3)// Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
1613#define TMR32B0CCR_CAP1FE (1 << 4)// Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
1614#define TMR32B0CCR_CAP1I (1 << 5)// Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.
1617#define TMR32B0EMR_EM0 (1 << 0)// External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1618#define TMR32B0EMR_EM1 (1 << 1)// External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1619#define TMR32B0EMR_EM2 (1 << 2)// External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1620#define TMR32B0EMR_EM3 (1 << 3)// External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
1621#define TMR32B0EMR_EMC0_MASK 0x0030// External Match Control 0. Determines the functionality of External Match 0.
1631#define TMR32B0CTCR_CTM_MASK 0x0003// Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
1633#define TMR32B0CTCR_CIS_MASK 0x000C// Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
1635#define TMR32B0CTCR_ENCC (1 << 4)// Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
1636#define TMR32B0CTCR_SELCC_MASK 0x00E0// When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
1646#define WDMOD_WDEN (1 << 0)// Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.
1647#define WDMOD_WDRESET (1 << 1)// Watchdog reset enable bit. This bit is Set Only.
1648#define WDMOD_WDTOF (1 << 2)// Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.
1649#define WDMOD_WDINT (1 << 3)// Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
1650#define WDMOD_WDPROTECT (1 << 4)// Watchdog update mode. This bit is Set Only.
1673#define WDMOD_WDEN (1 << 0)// WDEN Watchdog enable bit (Set Only). When 1, the watchdog timer is running. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. The clock source lock feature is not available on all parts, see Section 23.1).
1674#define WDMOD_WDRESET_WDRESET (1 << 1)// Watchdog reset enable bit (Set Only). When 1, og time-out will cause a chip reset.
1675#define WDMOD_WDTOF (1 << 2)// WDTOF Watchdog time-out flag. Set when the watchdog
1676#define WDMOD_WDINT (1 << 3)// WDINT Watchdog interrupt flag (Read Only, not clearable by software).
1691#define SYST_CSR_ENABLE (1 << 0)// System Tick counter enable. When 1, the counter is enabled. When 0, the counter is disabled.
1692#define SYST_CSR_TICKINT (1 << 1)// System Tick interrupt enable. When 1, the System Tick interrupt 0 is enabled. When 0, the System Tick interrupt is disabled. When enabled, the interrupt is generated when the System Tick counter counts down to 0.
1693#define SYST_CSR_CLKSOURCE (1 << 2)// System Tick clock source selection. When 1, the system clock (CPU) clock is selected. When 0, the system clock/2 is selected as the reference clock.
1694#define SYST_CSR_COUNTFLAG (1 << 16)// Returns 1 if the SysTick timer counted to 0 since the last read of this register. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
1701#define SYST_CVR_CURRENT_MASK 0xFFFFFF// Reading this register returns the current value of the System Tick counter. Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL.
1711#define AD0CR_SEL_MASK 0x00FF// Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin 0x00 AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).
1713#define AD0CR_CLKDIV_MASK 0xFF00// The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which 0 should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
1715#define AD0CR_BURST (1 << 16)// Burst mode Remark: If BURST is set to 1, the ADGINTEN bit in the AD0INTEN register (Table 365) must be set to 0.
1716#define AD0CR_CLKS_MASK 0xE0000// This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
1723#define AD0GDR_V_VREF_MASK 0xFFC0// When DONE is 1, this field contains a binary fraction representing X the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
1727#define AD0GDR_OVERRUN (1 << 30)// This bit is 1 in burst mode if the results of one or more conversions 0 was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.
1728#define AD0GDR_DONE (1 << 31)// This bit is set to 1 when an A/D conversion completes. It is cleared 0 when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
1731#define AD0INTEN_ADINTEN_MASK 0x00FF// These bits allow control over which A/D channels generate 0x00 interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
1733#define AD0INTEN_ADGINTEN (1 << 8)// When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. Remark: This bit must be set to 0 in burst mode (BURST = 1 in the AD0CR register). Reserved. Unused, always 0.
1735/* AD0DR0 to AD0DR7 - addresses 0x4001 C010 to 0x4001 C02C */
1736#define AD0DRn_V_VREF_MASK 0xFFC0// When DONE is 1, this field contains a binary fraction representing the NA voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. Reserved.
1738#define AD0DRn_OVERRUN (1 << 30)// This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
1739#define AD0DRn_DONE (1 << 31)// This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
1744#define AD0STAT_OVERRUN_MASK 0xFF00// These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
1746#define AD0STAT_ADINT (1 << 16)// This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. Reserved. Unused, always 0.
1762#define FMSTAT_SIG_DONE (1 << 2)// When 1, a previously started signature generation has 0 completed. See FMSTATCLR register description for clearing this flag.
1765#define FMSTATCLR_SIG_DONE_CLR (1 << 2)// Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.