]> git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h
git://git.gir.st / tmk_keyboard.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_NXP / TARGET_LPC13XX / LPC13Uxx.h
1
2 /****************************************************************************************************//**
3 * @file LPC13Uxx.h
4 *
5 *
6 *
7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
8 * default LPC13Uxx Device Series
9 *
10 * @version V0.1
11 * @date 18. Jan 2012
12 *
13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
14 *
15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
17 *
18 *******************************************************************************************************/
19
20 /** @addtogroup NXP
21 * @{
22 */
23
24 /** @addtogroup LPC13Uxx
25 * @{
26 */
27
28 #ifndef __LPC13UXX_H__
29 #define __LPC13UXX_H__
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 #if defined ( __CC_ARM )
37 #pragma anon_unions
38 #endif
39
40 /* Interrupt Number Definition */
41
42 typedef enum {
43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
63 GINT0_IRQn = 8, /*!< 8 GINT0 */
64 GINT1_IRQn = 9, /*!< 9 GINT1 */
65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
69 SSP1_IRQn = 14, /*!< 14 SSP1 */
70 I2C_IRQn = 15, /*!< 15 I2C */
71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
75 SSP0_IRQn = 20, /*!< 20 SSP0 */
76 USART_IRQn = 21, /*!< 21 USART */
77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
79 ADC_IRQn = 24, /*!< 24 ADC */
80 WDT_IRQn = 25, /*!< 25 WDT */
81 BOD_IRQn = 26, /*!< 26 BOD */
82 FMC_IRQn = 27, /*!< 27 FMC */
83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
87 } IRQn_Type;
88
89
90 /** @addtogroup Configuration_of_CMSIS
91 * @{
92 */
93
94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
95
96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
97 #define __MPU_PRESENT 0 /*!< MPU present or not */
98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
100 /** @} */ /* End of group Configuration_of_CMSIS */
101
102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
104
105 /** @addtogroup Device_Peripheral_Registers
106 * @{
107 */
108
109
110 // ------------------------------------------------------------------------------------------------
111 // ----- I2C -----
112 // ------------------------------------------------------------------------------------------------
113
114
115
116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
125 union{
126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
127 struct{
128 __IO uint32_t ADR1;
129 __IO uint32_t ADR2;
130 __IO uint32_t ADR3;
131 };
132 };
133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
134 union{
135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
136 struct{
137 __IO uint32_t MASK0;
138 __IO uint32_t MASK1;
139 __IO uint32_t MASK2;
140 __IO uint32_t MASK3;
141 };
142 };
143 } LPC_I2C_Type;
144
145
146 // ------------------------------------------------------------------------------------------------
147 // ----- WWDT -----
148 // ------------------------------------------------------------------------------------------------
149
150
151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
159 } LPC_WWDT_Type;
160
161
162 // ------------------------------------------------------------------------------------------------
163 // ----- USART -----
164 // ------------------------------------------------------------------------------------------------
165
166
167 typedef struct { /*!< (@ 0x40008000) USART Structure */
168
169 union {
170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
173 };
174
175 union {
176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
178 };
179
180 union {
181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
183 };
184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
194 __I uint32_t RESERVED0[3];
195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
196 __I uint32_t RESERVED1;
197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
202 } LPC_USART_Type;
203
204
205 // ------------------------------------------------------------------------------------------------
206 // ----- CT16B0 -----
207 // ------------------------------------------------------------------------------------------------
208
209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
216 union {
217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
218 struct{
219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
223 };
224 };
225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
226 union{
227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
228 struct{
229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
233 };
234 };
235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
236 __I uint32_t RESERVED0[12];
237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
239 } LPC_CTxxBx_Type;
240
241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
248 union {
249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
250 struct{
251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
255 };
256 };
257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
258 union{
259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
260 struct{
261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
265 };
266 };
267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
268 __I uint32_t RESERVED0[12];
269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
271 } LPC_CT16B0_Type;
272
273
274 // ------------------------------------------------------------------------------------------------
275 // ----- CT16B1 -----
276 // ------------------------------------------------------------------------------------------------
277
278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
285 union {
286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
287 struct{
288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
292 };
293 };
294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
295 union{
296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
297 struct{
298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
302 };
303 };
304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
305 __I uint32_t RESERVED0[12];
306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
308 } LPC_CT16B1_Type;
309
310
311 // ------------------------------------------------------------------------------------------------
312 // ----- CT32B0 -----
313 // ------------------------------------------------------------------------------------------------
314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
321 union {
322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
323 struct{
324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
328 };
329 };
330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
331 union{
332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
333 struct{
334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
338 };
339 };
340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
341 __I uint32_t RESERVED0[12];
342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
344 } LPC_CT32B0_Type;
345
346
347 // ------------------------------------------------------------------------------------------------
348 // ----- CT32B1 -----
349 // ------------------------------------------------------------------------------------------------
350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
357 union {
358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
359 struct{
360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
364 };
365 };
366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
367 union{
368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
369 struct{
370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
374 };
375 };
376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
377 __I uint32_t RESERVED0[12];
378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
380 } LPC_CT32B1_Type;
381
382
383 // ------------------------------------------------------------------------------------------------
384 // ----- ADC -----
385 // ------------------------------------------------------------------------------------------------
386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
389 __I uint32_t RESERVED0[1];
390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
391 union{
392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
393 struct{
394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
402 };
403 };
404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
405 } LPC_ADC_Type;
406
407
408 // ------------------------------------------------------------------------------------------------
409 // ----- PMU -----
410 // ------------------------------------------------------------------------------------------------
411
412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
414 union{
415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
416 struct{
417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
421 };
422 };
423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
424 } LPC_PMU_Type;
425
426
427 // ------------------------------------------------------------------------------------------------
428 // ----- FLASHCTRL -----
429 // ------------------------------------------------------------------------------------------------
430
431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
432 __I uint32_t RESERVED0[4];
433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
434 __I uint32_t RESERVED1[3];
435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
437 __I uint32_t RESERVED2[1];
438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
442 __I uint32_t RESERVED3[1001];
443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
444 __I uint32_t RESERVED4[1];
445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
446 } LPC_FLASHCTRL_Type;
447
448
449 // ------------------------------------------------------------------------------------------------
450 // ----- SSP -----
451 // ------------------------------------------------------------------------------------------------
452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
462 } LPC_SSPx_Type;
463
464
465 // ------------------------------------------------------------------------------------------------
466 // ----- IOCON -----
467 // ------------------------------------------------------------------------------------------------
468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
525 } LPC_IOCON_Type;
526
527
528 // ------------------------------------------------------------------------------------------------
529 // ----- SYSCON -----
530 // ------------------------------------------------------------------------------------------------
531
532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
539 __I uint32_t RESERVED0[2];
540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
542 __I uint32_t RESERVED1[2];
543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
544 __I uint32_t RESERVED2[3];
545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
546 __I uint32_t RESERVED3;
547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
548 __I uint32_t RESERVED4[9];
549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
550 __I uint32_t RESERVED5;
551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
552 __I uint32_t RESERVED6;
553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
554 __I uint32_t RESERVED7[4];
555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
558 __I uint32_t RESERVED8[3];
559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
561 __I uint32_t RESERVED9[3];
562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
563 __I uint32_t RESERVED10;
564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
565 __I uint32_t RESERVED11[5];
566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
567 __I uint32_t RESERVED12;
568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
569 __I uint32_t RESERVED13[5];
570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
572 __I uint32_t RESERVED14[18];
573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
575 __I uint32_t RESERVED15[6];
576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
581 __I uint32_t RESERVED16[25];
582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
583 __I uint32_t RESERVED17[3];
584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
585 __I uint32_t RESERVED18[6];
586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
589 __I uint32_t RESERVED19[111];
590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
591 } LPC_SYSCON_Type;
592
593
594 // ------------------------------------------------------------------------------------------------
595 // ----- GPIO_PIN_INT -----
596 // ------------------------------------------------------------------------------------------------
597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
608 } LPC_GPIO_PIN_INT_Type;
609
610
611 // ------------------------------------------------------------------------------------------------
612 // ----- GPIO_GROUP_INT0 -----
613 // ------------------------------------------------------------------------------------------------
614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
616 __I uint32_t RESERVED0[7];
617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
618 __I uint32_t RESERVED1[6];
619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
620 } LPC_GPIO_GROUP_INT0_Type;
621
622
623 // ------------------------------------------------------------------------------------------------
624 // ----- GPIO_GROUP_INT1 -----
625 // ------------------------------------------------------------------------------------------------
626
627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
629 __I uint32_t RESERVED0[7];
630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
631 __I uint32_t RESERVED1[6];
632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
633 } LPC_GPIO_GROUP_INT1_Type;
634
635
636 // ------------------------------------------------------------------------------------------------
637 // ----- Repetitive Interrupt Timer (RIT) -----
638 // ------------------------------------------------------------------------------------------------
639
640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
647 __I uint32_t RESERVED0[1];
648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
649 } LPC_RITIMER_Type;
650
651
652 // ------------------------------------------------------------------------------------------------
653 // ----- USB -----
654 // ------------------------------------------------------------------------------------------------
655 typedef struct { /*!< (@ 0x40020000) USB Structure */
656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
668 __I uint32_t RESERVED0[1];
669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
670 } LPC_USB_Type;
671
672
673 // ------------------------------------------------------------------------------------------------
674 // ----- GPIO_PORT -----
675 // ------------------------------------------------------------------------------------------------
676
677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
678 union {
679 struct {
680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
682 };
683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
684 };
685 __I uint32_t RESERVED0[1008];
686 union {
687 struct {
688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
690 };
691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
692 };
693 __I uint32_t RESERVED1[960];
694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
695 __I uint32_t RESERVED2[30];
696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
697 __I uint32_t RESERVED3[30];
698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
699 __I uint32_t RESERVED4[30];
700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
701 __I uint32_t RESERVED5[30];
702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
703 __I uint32_t RESERVED6[30];
704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
705 __I uint32_t RESERVED7[30];
706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
707 } LPC_GPIO_Type;
708
709
710 #if defined ( __CC_ARM )
711 #pragma no_anon_unions
712 #endif
713
714
715 // ------------------------------------------------------------------------------------------------
716 // ----- Peripheral memory map -----
717 // ------------------------------------------------------------------------------------------------
718
719 #define LPC_I2C_BASE (0x40000000)
720 #define LPC_WWDT_BASE (0x40004000)
721 #define LPC_USART_BASE (0x40008000)
722 #define LPC_CT16B0_BASE (0x4000C000)
723 #define LPC_CT16B1_BASE (0x40010000)
724 #define LPC_CT32B0_BASE (0x40014000)
725 #define LPC_CT32B1_BASE (0x40018000)
726 #define LPC_ADC_BASE (0x4001C000)
727 #define LPC_PMU_BASE (0x40038000)
728 #define LPC_FLASHCTRL_BASE (0x4003C000)
729 #define LPC_SSP0_BASE (0x40040000)
730 #define LPC_IOCON_BASE (0x40044000)
731 #define LPC_SYSCON_BASE (0x40048000)
732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
733 #define LPC_SSP1_BASE (0x40058000)
734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
736 #define LPC_RITIMER_BASE (0x40064000)
737 #define LPC_USB_BASE (0x40080000)
738 #define LPC_GPIO_BASE (0x50000000)
739
740
741 // ------------------------------------------------------------------------------------------------
742 // ----- Peripheral declaration -----
743 // ------------------------------------------------------------------------------------------------
744
745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
765
766
767 /** @} */ /* End of group Device_Peripheral_Registers */
768 /** @} */ /* End of group (null) */
769 /** @} */ /* End of group h1usf */
770
771 #ifdef __cplusplus
772 }
773 #endif
774
775
776 #endif // __LPC13UXX_H__
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
Imprint / Impressum