tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h

   1 /* mbed Microcontroller Library - Vectors
   2  * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
   3  */
   4
   5 #ifndef MBED_VECTOR_DEFNS_H
   6 #define MBED_VECTOR_DEFNS_H
   7
   8 // Assember Macros
   9 #ifdef __ARMCC_VERSION
  10 #define EXPORT(x) EXPORT x
  11 #define WEAK_EXPORT(x) EXPORT x [WEAK]
  12 #define IMPORT(x) IMPORT x
  13 #define LABEL(x) x
  14 #else
  15 #define EXPORT(x) .global x
  16 #define WEAK_EXPORT(x) .weak x
  17 #define IMPORT(x) .global x
  18 #define LABEL(x) x:
  19 #endif
  20
  21 // RealMonitor
  22 // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
  23
  24 // RealMonitor entry points
  25 #define rm_init_entry 0x7fffff91
  26 #define rm_undef_handler 0x7fffffa0
  27 #define rm_prefetchabort_handler 0x7fffffb0
  28 #define rm_dataabort_handler 0x7fffffc0
  29 #define rm_irqhandler2 0x7fffffe0
  30 //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
  31 #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
  32
  33 // Unofficial RealMonitor entry points and variables
  34 #define RM_MSG_SWI 0x00940000
  35 #define StateP 0x40000040
  36
  37 // VIC register addresses
  38 #define VIC_Base 0xfffff000
  39 #define VICAddress_Offset 0xf00
  40 #define VICVectAddr0_Offset 0x100
  41 #define VICVectAddr2_Offset 0x108
  42 #define VICVectAddr3_Offset 0x10c
  43 #define VICVectAddr31_Offset 0x17c
  44 #define VICIntEnClr_Offset 0x014
  45 #define VICIntEnClr    (*(volatile unsigned long *)(VIC_Base + 0x014))
  46 #define VICVectAddr2   (*(volatile unsigned long *)(VIC_Base + 0x108))
  47 #define VICVectAddr3   (*(volatile unsigned long *)(VIC_Base + 0x10C))
  48
  49 // ARM Mode bits and Interrupt flags in PSRs
  50 #define Mode_USR 0x10
  51 #define Mode_FIQ 0x11
  52 #define Mode_IRQ 0x12
  53 #define Mode_SVC 0x13
  54 #define Mode_ABT 0x17
  55 #define Mode_UND 0x1B
  56 #define Mode_SYS 0x1F
  57 #define I_Bit 0x80    // when I bit is set, IRQ is disabled
  58 #define F_Bit 0x40    // when F bit is set, FIQ is disabled
  59
  60 // MCU RAM
  61 #define LPC2368_RAM_ADDRESS 0x40000000  // RAM Base
  62 #define LPC2368_RAM_SIZE 0x8000         // 32KB
  63
  64 // ISR Stack Allocation
  65 #define UND_stack_size  0x00000040
  66 #define SVC_stack_size  0x00000040
  67 #define ABT_stack_size  0x00000040
  68 #define FIQ_stack_size  0x00000000
  69 #define IRQ_stack_size  0x00000040
  70
  71 #define ISR_stack_size  (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
  72
  73 // Full Descending Stack, so top-most stack points to just above the top of RAM
  74 #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
  75 #define USR_STACK_TOP     (LPC2368_STACK_TOP - ISR_stack_size)
  76
  77 #endif