tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c

   1 /******************************************************************************
   2  * @file:    system_LPC8xx.c
   3  * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
   4  *           for the NXP LPC8xx Device Series
   5  * @version: V1.0
   6  * @date:    16. Aug. 2012
   7  *----------------------------------------------------------------------------
   8  *
   9  * Copyright (C) 2012 ARM Limited. All rights reserved.
  10  *
  11  * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
  12  * processor based microcontrollers.  This file can be freely distributed
  13  * within development tools that are supporting such ARM based processors.
  14  *
  15  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  16  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  18  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  19  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  20  *
  21  ******************************************************************************/
  22 #include <stdint.h>
  23 #include "LPC8xx.h"
  24
  25 /*
  26 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  27 */
  28
  29 /*--------------------- Clock Configuration ----------------------------------
  30 //
  31 // <e> Clock Configuration
  32 //   <h> System Oscillator Control Register (SYSOSCCTRL)
  33 //     <o1.0>      BYPASS: System Oscillator Bypass Enable
  34 //                     <i> If enabled then PLL input (sys_osc_clk) is fed
  35 //                     <i> directly from XTALIN and XTALOUT pins.
  36 //     <o1.9>      FREQRANGE: System Oscillator Frequency Range
  37 //                     <i> Determines frequency range for Low-power oscillator.
  38 //                   <0=> 1 - 20 MHz
  39 //                   <1=> 15 - 25 MHz
  40 //   </h>
  41 //
  42 //   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
  43 //     <o2.0..4>   DIVSEL: Select Divider for Fclkana
  44 //                     <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
  45 //                   <0-31>
  46 //     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
  47 //                   <0=> Undefined
  48 //                   <1=> 0.5 MHz
  49 //                   <2=> 0.8 MHz
  50 //                   <3=> 1.1 MHz
  51 //                   <4=> 1.4 MHz
  52 //                   <5=> 1.6 MHz
  53 //                   <6=> 1.8 MHz
  54 //                   <7=> 2.0 MHz
  55 //                   <8=> 2.2 MHz
  56 //                   <9=> 2.4 MHz
  57 //                   <10=> 2.6 MHz
  58 //                   <11=> 2.7 MHz
  59 //                   <12=> 2.9 MHz
  60 //                   <13=> 3.1 MHz
  61 //                   <14=> 3.2 MHz
  62 //                   <15=> 3.4 MHz
  63 //   </h>
  64 //
  65 //   <h> System PLL Control Register (SYSPLLCTRL)
  66 //                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
  67 //                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
  68 //                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
  69 //     <o3.0..4>   MSEL: Feedback Divider Selection
  70 //                     <i> M = MSEL + 1
  71 //                   <0-31>
  72 //     <o3.5..6>   PSEL: Post Divider Selection
  73 //                   <0=> P = 1
  74 //                   <1=> P = 2
  75 //                   <2=> P = 4
  76 //                   <3=> P = 8
  77 //   </h>
  78 //
  79 //   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
  80 //     <o4.0..1>   SEL: System PLL Clock Source
  81 //                   <0=> IRC Oscillator
  82 //                   <1=> System Oscillator
  83 //                   <2=> Reserved
  84 //                   <3=> CLKIN pin
  85 //   </h>
  86 //
  87 //   <h> Main Clock Source Select Register (MAINCLKSEL)
  88 //     <o5.0..1>   SEL: Clock Source for Main Clock
  89 //                   <0=> IRC Oscillator
  90 //                   <1=> Input Clock to System PLL
  91 //                   <2=> WDT Oscillator
  92 //                   <3=> System PLL Clock Out
  93 //   </h>
  94 //
  95 //   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
  96 //     <o6.0..7>   DIV: System AHB Clock Divider
  97 //                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
  98 //                     <i> 0 = is disabled
  99 //                   <0-255>
 100 //   </h>
 101 // </e>
 102 */
 103
 104 // 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal:
 105 #define CLOCK_SETUP           1
 106 //use PLL for IRC
 107 #define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 108 #define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
 109 #define SYSPLLCTRL_Val        0x00000041              // Reset: 0x000  MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz
 110 //#define SYSPLLCTRL_Val        0x00000004              // Reset: 0x000  MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
 111 #define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000  Select IRC
 112 #define MAINCLKSEL_Val        0x00000003              // Reset: 0x000  MainClock = PLLCLKOUT
 113 #define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001  DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz
 114 //#define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001  DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
 115 /*
 116 //-------- <<< end of configuration section >>> ------------------------------
 117 */
 118
 119 /*----------------------------------------------------------------------------
 120   Check the register settings
 121  *----------------------------------------------------------------------------*/
 122 #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
 123 #define CHECK_RSVD(val, mask)                     (val & mask)
 124
 125 /* Clock Configuration -------------------------------------------------------*/
 126 #if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
 127    #error "SYSOSCCTRL: Invalid values of reserved bits!"
 128 #endif
 129
 130 #if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
 131    #error "WDTOSCCTRL: Invalid values of reserved bits!"
 132 #endif
 133
 134 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
 135    #error "SYSPLLCLKSEL: Value out of range!"
 136 #endif
 137
 138 #if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
 139    #error "SYSPLLCTRL: Invalid values of reserved bits!"
 140 #endif
 141
 142 #if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
 143    #error "MAINCLKSEL: Invalid values of reserved bits!"
 144 #endif
 145
 146 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
 147    #error "SYSAHBCLKDIV: Value out of range!"
 148 #endif
 149
 150
 151 /*----------------------------------------------------------------------------
 152   DEFINES
 153  *----------------------------------------------------------------------------*/
 154
 155 /*----------------------------------------------------------------------------
 156   Define clocks
 157  *----------------------------------------------------------------------------*/
 158 #define __XTAL            (12000000UL)    /* Oscillator frequency             */
 159 #define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
 160 #define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
 161 #define __CLKIN_CLK       (12000000UL)    /* CLKIN pin frequency              */
 162
 163
 164 #define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
 165 #define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
 166
 167 #if (CLOCK_SETUP)                         /* Clock Setup              */
 168   #if  (__FREQSEL ==  0)
 169     #define __WDT_OSC_CLK        ( 0)                  /* undefined */
 170   #elif (__FREQSEL ==  1)
 171     #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
 172   #elif (__FREQSEL ==  2)
 173     #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
 174   #elif (__FREQSEL ==  3)
 175     #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
 176   #elif (__FREQSEL ==  4)
 177     #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
 178   #elif (__FREQSEL ==  5)
 179     #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
 180   #elif (__FREQSEL ==  6)
 181     #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
 182   #elif (__FREQSEL ==  7)
 183     #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
 184   #elif (__FREQSEL ==  8)
 185     #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
 186   #elif (__FREQSEL ==  9)
 187     #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
 188   #elif (__FREQSEL == 10)
 189     #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
 190   #elif (__FREQSEL == 11)
 191     #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
 192   #elif (__FREQSEL == 12)
 193     #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
 194   #elif (__FREQSEL == 13)
 195     #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
 196   #elif (__FREQSEL == 14)
 197     #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
 198   #else
 199     #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
 200   #endif
 201
 202   /* sys_pllclkin calculation */
 203   #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
 204     #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
 205   #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
 206     #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
 207   #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
 208     #define __SYS_PLLCLKIN           (__CLKIN_CLK)
 209   #else
 210     #define __SYS_PLLCLKIN           (0)
 211   #endif
 212
 213   #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
 214
 215   /* main clock calculation */
 216   #if   ((MAINCLKSEL_Val & 0x03) == 0)
 217     #define __MAIN_CLOCK             (__IRC_OSC_CLK)
 218   #elif ((MAINCLKSEL_Val & 0x03) == 1)
 219     #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
 220   #elif ((MAINCLKSEL_Val & 0x03) == 2)
 221     #if (__FREQSEL ==  0)
 222       #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
 223     #else
 224       #define __MAIN_CLOCK           (__WDT_OSC_CLK)
 225     #endif
 226   #elif ((MAINCLKSEL_Val & 0x03) == 3)
 227     #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
 228   #else
 229     #define __MAIN_CLOCK             (0)
 230   #endif
 231
 232   #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
 233
 234 #else
 235   #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
 236 #endif  // CLOCK_SETUP
 237
 238
 239 /*----------------------------------------------------------------------------
 240   Clock Variable definitions
 241  *----------------------------------------------------------------------------*/
 242 uint32_t MainClock = __MAIN_CLOCK;         /*!< Main Clock Frequency */
 243 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
 244
 245 //Replaced SystemCoreClock with MainClock
 246 /*----------------------------------------------------------------------------
 247   Clock functions
 248  *----------------------------------------------------------------------------*/
 249 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
 250 {
 251   uint32_t wdt_osc = 0;
 252
 253   /* Determine clock frequency according to clock register values             */
 254   switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
 255     case 0:  wdt_osc =       0; break;
 256     case 1:  wdt_osc =  500000; break;
 257     case 2:  wdt_osc =  800000; break;
 258     case 3:  wdt_osc = 1100000; break;
 259     case 4:  wdt_osc = 1400000; break;
 260     case 5:  wdt_osc = 1600000; break;
 261     case 6:  wdt_osc = 1800000; break;
 262     case 7:  wdt_osc = 2000000; break;
 263     case 8:  wdt_osc = 2200000; break;
 264     case 9:  wdt_osc = 2400000; break;
 265     case 10: wdt_osc = 2600000; break;
 266     case 11: wdt_osc = 2700000; break;
 267     case 12: wdt_osc = 2900000; break;
 268     case 13: wdt_osc = 3100000; break;
 269     case 14: wdt_osc = 3200000; break;
 270     case 15: wdt_osc = 3400000; break;
 271   }
 272   wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
 273
 274   switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
 275     case 0:                             /* Internal RC oscillator             */
 276       MainClock = __IRC_OSC_CLK;
 277       break;
 278     case 1:                             /* Input Clock to System PLL          */
 279       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
 280           case 0:                       /* Internal RC oscillator             */
 281             MainClock = __IRC_OSC_CLK;
 282             break;
 283           case 1:                       /* System oscillator                  */
 284             MainClock = __SYS_OSC_CLK;
 285             break;
 286           case 2:                       /* Reserved                           */
 287             MainClock = 0;
 288             break;
 289           case 3:                       /* CLKIN pin                          */
 290             MainClock = __CLKIN_CLK;
 291             break;
 292       }
 293       break;
 294     case 2:                             /* WDT Oscillator                     */
 295       MainClock = wdt_osc;
 296       break;
 297     case 3:                             /* System PLL Clock Out               */
 298       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
 299           case 0:                       /* Internal RC oscillator             */
 300             MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 301             break;
 302           case 1:                       /* System oscillator                  */
 303             MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 304             break;
 305           case 2:                       /* Reserved                           */
 306             MainClock = 0;
 307             break;
 308           case 3:                       /* CLKIN pin                          */
 309             MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 310             break;
 311       }
 312       break;
 313   }
 314
 315   SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
 316
 317 }
 318
 319 /**
 320  * Initialize the system
 321  *
 322  * @param  none
 323  * @return none
 324  *
 325  * @brief  Setup the microcontroller system.
 326  *         Initialize the System.
 327  */
 328 void SystemInit (void) {
 329   volatile uint32_t i;
 330
 331   /* System clock to the IOCON & the SWM need to be enabled or
 332   most of the I/O related peripherals won't work. */
 333   LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
 334
 335 #if (CLOCK_SETUP)                                 /* Clock Setup              */
 336
 337 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
 338   LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
 339   LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
 340   LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
 341   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 5);        /* Power-up System Osc      */
 342   LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
 343   for (i = 0; i < 200; i++) __NOP();
 344 #endif
 345 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
 346   LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
 347   LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
 348   for (i = 0; i < 200; i++) __NOP();
 349 #endif
 350
 351   LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
 352   LPC_SYSCON->SYSPLLCLKUEN  = 0x01;               /* Update Clock Source      */
 353   while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
 354 #if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
 355   LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
 356   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 7);        /* Power-up SYSPLL          */
 357   while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));           /* Wait Until PLL Locked    */
 358 #endif
 359
 360 #if (((MAINCLKSEL_Val & 0x03) == 2) )
 361   LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
 362   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 6);        /* Power-up WDT Clock       */
 363   for (i = 0; i < 200; i++) __NOP();
 364 #endif
 365
 366   LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
 367   LPC_SYSCON->MAINCLKUEN    = 0x01;               /* Update MCLK Clock Source */
 368   while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
 369
 370   LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
 371 #endif
 372 }