tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.s

   1 /**************************************************
   2  *
   3  * Part one of the system initialization code, contains low-level
   4  * initialization, plain thumb variant.
   5  *
   6  * Copyright 2011 IAR Systems. All rights reserved.
   7  *
   8  * $Revision: 47876 $
   9  *
  10  **************************************************/
  11
  12 ;
  13 ; The modules in this file are included in the libraries, and may be replaced
  14 ; by any user-defined modules that define the PUBLIC symbol _program_start or
  15 ; a user defined start symbol.
  16 ; To override the cstartup defined in the library, simply add your modified
  17 ; version to the workbench project.
  18 ;
  19 ; The vector table is normally located at address 0.
  20 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
  21 ; The name "__vector_table" has special meaning for C-SPY:
  22 ; it is where the SP start value is found, and the NVIC vector
  23 ; table register (VTOR) is initialized to this address if != 0.
  24 ;
  25 ; Cortex-M version
  26 ;
  27
  28
  29         MODULE  ?cstartup
  30
  31         ;; Forward declaration of sections.
  32         SECTION CSTACK:DATA:NOROOT(3)
  33
  34         SECTION .intvec:CODE:NOROOT(2)
  35
  36         EXTERN  __iar_program_start
  37         EXTERN  SystemInit
  38         PUBLIC  __vector_table
  39         PUBLIC  __vector_table_0x1c
  40         PUBLIC  __Vectors
  41         PUBLIC  __Vectors_End
  42         PUBLIC  __Vectors_Size
  43
  44         DATA
  45
  46 __vector_table
  47         DCD     sfe(CSTACK)
  48         DCD     Reset_Handler
  49         DCD     NMI_Handler
  50         DCD     HardFault_Handler
  51         DCD     0
  52         DCD     0
  53         DCD     0
  54 __vector_table_0x1c
  55         DCD     0
  56         DCD     0
  57         DCD     0
  58         DCD     0
  59         DCD     SVC_Handler
  60         DCD     0
  61         DCD     0
  62         DCD     PendSV_Handler
  63         DCD     SysTick_Handler
  64
  65         ; External Interrupts
  66         DCD     SPI0_IRQHandler             ; SPI0 controller
  67         DCD     SPI1_IRQHandler             ; SPI1 controller
  68         DCD     0                           ; Reserved
  69         DCD     UART0_IRQHandler            ; UART0
  70         DCD     UART1_IRQHandler            ; UART1
  71         DCD     UART2_IRQHandler            ; UART2
  72         DCD     0                           ; Reserved
  73         DCD     0                           ; Reserved
  74         DCD     I2C_IRQHandler              ; I2C controller
  75         DCD     SCT_IRQHandler              ; Smart Counter Timer
  76         DCD     MRT_IRQHandler              ; Multi-Rate Timer
  77         DCD     CMP_IRQHandler              ; Comparator
  78         DCD     WDT_IRQHandler              ; PIO1 (0:11)
  79         DCD     BOD_IRQHandler              ; Brown Out Detect
  80         DCD     0                           ; Reserved
  81         DCD     WKT_IRQHandler              ; Wakeup timer
  82         DCD     0                           ; Reserved
  83         DCD     0                           ; Reserved
  84         DCD     0                           ; Reserved
  85         DCD     0                           ; Reserved
  86         DCD     0                           ; Reserved
  87         DCD     0                           ; Reserved
  88         DCD     0                           ; Reserved
  89         DCD     0                           ; Reserved
  90         DCD     PININT0_IRQHandler          ; PIO INT0
  91         DCD     PININT1_IRQHandler         ; PIO INT1
  92         DCD     PININT2_IRQHandler         ; PIO INT2
  93         DCD     PININT3_IRQHandler         ; PIO INT3
  94         DCD     PININT4_IRQHandler         ; PIO INT4
  95         DCD     PININT5_IRQHandler         ; PIO INT5
  96         DCD     PININT6_IRQHandler         ; PIO INT6
  97         DCD     PININT7_IRQHandler         ; PIO INT7
  98 __Vectors_End
  99
 100 __Vectors       EQU   __vector_table
 101 __Vectors_Size  EQU   __Vectors_End - __Vectors
 102
 103 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 104 ;;
 105 ;; Default interrupt handlers.
 106 ;;
 107 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 108
 109         THUMB
 110         PUBWEAK Reset_Handler
 111         SECTION .text:CODE:NOROOT:REORDER(2)
 112 Reset_Handler
 113         LDR     R0, =SystemInit
 114         BLX     R0
 115         LDR     R0, =__iar_program_start
 116         BX      R0
 117
 118         PUBWEAK NMI_Handler
 119         PUBWEAK HardFault_Handler
 120         PUBWEAK SVC_Handler
 121         PUBWEAK PendSV_Handler
 122         PUBWEAK SysTick_Handler
 123         PUBWEAK SPI0_IRQHandler
 124         PUBWEAK SPI1_IRQHandler
 125         PUBWEAK UART0_IRQHandler
 126         PUBWEAK UART1_IRQHandler
 127         PUBWEAK UART2_IRQHandler
 128         PUBWEAK I2C_IRQHandler
 129         PUBWEAK SCT_IRQHandler
 130         PUBWEAK MRT_IRQHandler
 131         PUBWEAK CMP_IRQHandler
 132         PUBWEAK WDT_IRQHandler
 133         PUBWEAK BOD_IRQHandler
 134         PUBWEAK WKT_IRQHandler
 135         PUBWEAK PININT0_IRQHandler
 136         PUBWEAK PININT1_IRQHandler
 137         PUBWEAK PININT2_IRQHandler
 138         PUBWEAK PININT3_IRQHandler
 139         PUBWEAK PININT4_IRQHandler
 140         PUBWEAK PININT5_IRQHandler
 141         PUBWEAK PININT6_IRQHandler
 142         PUBWEAK PININT7_IRQHandler
 143
 144       SECTION .text:CODE:REORDER:NOROOT(1)
 145       THUMB
 146
 147 NMI_Handler
 148 HardFault_Handler
 149 SVC_Handler
 150 PendSV_Handler
 151 SysTick_Handler
 152 SPI0_IRQHandler
 153 SPI1_IRQHandler
 154 UART0_IRQHandler
 155 UART1_IRQHandler
 156 UART2_IRQHandler
 157 I2C_IRQHandler
 158 SCT_IRQHandler
 159 MRT_IRQHandler
 160 CMP_IRQHandler
 161 WDT_IRQHandler
 162 BOD_IRQHandler
 163 WKT_IRQHandler
 164 PININT0_IRQHandler
 165 PININT1_IRQHandler
 166 PININT2_IRQHandler
 167 PININT3_IRQHandler
 168 PININT4_IRQHandler
 169 PININT5_IRQHandler
 170 PININT6_IRQHandler
 171 PININT7_IRQHandler
 172 Default_IRQHandler
 173         B Default_IRQHandler
 174
 175         SECTION .crp:CODE:ROOT(2)
 176         DATA
 177 /* Code Read Protection
 178 NO_ISP  0x4E697370 -  Prevents sampling of pin PIO0_1 for entering ISP mode
 179 CRP1    0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
 180                    - Copy RAM to flash command can not write to Sector 0.
 181                    - Erase command can erase Sector 0 only when all sectors
 182                      are selected for erase.
 183                    - Compare command is disabled.
 184                    - Read Memory command is disabled.
 185 CRP2    0x87654321 - Read Memory is disabled.
 186                    - Write to RAM is disabled.
 187                    - "Go" command is disabled.
 188                    - Copy RAM to flash is disabled.
 189                    - Compare is disabled.
 190 CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
 191                      by pulling PIO0_1 LOW is disabled if a valid user code is
 192                      present in flash sector 0.
 193 Caution: If CRP3 is selected, no future factory testing can be
 194 performed on the device.
 195 */
 196             DCD 0xFFFFFFFF
 197
 198         END