tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f0xx.c
   4   * @author  MCD Application Team
   5   * @version V2.2.0
   6   * @date    05-December-2014
   7   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
   8   *
   9   * 1. This file provides two functions and one global variable to be called from
  10   *    user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32f0xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24   *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
  25   *    configure the system clock before to branch to main program.
  26   *
  27   * 3. This file configures the system clock as follows:
  28   *=============================================================================
  29   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  30   *                                    | (external 8 MHz clock) | (internal 48 MHz)
  31   *                                    | 2- PLL_HSE_XTAL        |
  32   *                                    | (external 8 MHz xtal)  |
  33   *-----------------------------------------------------------------------------
  34   * SYSCLK(MHz)                        | 48                     | 48
  35   *-----------------------------------------------------------------------------
  36   * AHBCLK (MHz)                       | 48                     | 48
  37   *-----------------------------------------------------------------------------
  38   * APB1CLK (MHz)                      | 48                     | 48
  39   *-----------------------------------------------------------------------------
  40   * USB capable (48 MHz precise clock) | YES                    | YES
  41   *=============================================================================
  42   ******************************************************************************
  43   * @attention
  44   *
  45   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  46   *
  47   * Redistribution and use in source and binary forms, with or without modification,
  48   * are permitted provided that the following conditions are met:
  49   *   1. Redistributions of source code must retain the above copyright notice,
  50   *      this list of conditions and the following disclaimer.
  51   *   2. Redistributions in binary form must reproduce the above copyright notice,
  52   *      this list of conditions and the following disclaimer in the documentation
  53   *      and/or other materials provided with the distribution.
  54   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  55   *      may be used to endorse or promote products derived from this software
  56   *      without specific prior written permission.
  57   *
  58   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  59   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  60   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  61   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  62   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  63   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  64   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  65   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  66   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  67   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  68   *
  69   ******************************************************************************
  70   */
  71
  72 /** @addtogroup CMSIS
  73   * @{
  74   */
  75
  76 /** @addtogroup stm32f0xx_system
  77   * @{
  78   */
  79
  80 /** @addtogroup STM32F0xx_System_Private_Includes
  81   * @{
  82   */
  83
  84 #include "stm32f0xx.h"
  85
  86 /**
  87   * @}
  88   */
  89
  90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
  91   * @{
  92   */
  93
  94 /**
  95   * @}
  96   */
  97
  98 /** @addtogroup STM32F0xx_System_Private_Defines
  99   * @{
 100   */
 101 #if !defined  (HSE_VALUE)
 102   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
 103                                                 This value can be provided and adapted by the user application. */
 104 #endif /* HSE_VALUE */
 105
 106 #if !defined  (HSI_VALUE)
 107   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
 108                                                 This value can be provided and adapted by the user application. */
 109 #endif /* HSI_VALUE */
 110 /**
 111   * @}
 112   */
 113
 114 /** @addtogroup STM32F0xx_System_Private_Macros
 115   * @{
 116   */
 117
 118 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 119 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 120 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 121
 122 /**
 123   * @}
 124   */
 125
 126 /** @addtogroup STM32F0xx_System_Private_Variables
 127   * @{
 128   */
 129   /* This variable is updated in three ways:
 130       1) by calling CMSIS function SystemCoreClockUpdate()
 131       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 132       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 133          Note: If you use this function to configure the system clock there is no need to
 134                call the 2 first functions listed above, since SystemCoreClock variable is
 135                updated automatically.
 136   */
 137 uint32_t SystemCoreClock = 48000000;
 138
 139 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 140
 141 /**
 142   * @}
 143   */
 144
 145 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
 146   * @{
 147   */
 148
 149 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 150 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 151 #endif
 152
 153 uint8_t SetSysClock_PLL_HSI(void);
 154
 155 /**
 156   * @}
 157   */
 158
 159 /** @addtogroup STM32F0xx_System_Private_Functions
 160   * @{
 161   */
 162
 163 /**
 164   * @brief  Setup the microcontroller system.
 165   *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
 166   * @param  None
 167   * @retval None
 168   */
 169 void SystemInit(void)
 170 {
 171   /* Reset the RCC clock configuration to the default reset state ------------*/
 172   /* Set HSION bit */
 173   RCC->CR |= (uint32_t)0x00000001;
 174
 175 #if defined (STM32F051x8) || defined (STM32F058x8)
 176   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
 177   RCC->CFGR &= (uint32_t)0xF8FFB80C;
 178 #else
 179   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
 180   RCC->CFGR &= (uint32_t)0x08FFB80C;
 181 #endif /* STM32F051x8 or STM32F058x8 */
 182
 183   /* Reset HSEON, CSSON and PLLON bits */
 184   RCC->CR &= (uint32_t)0xFEF6FFFF;
 185
 186   /* Reset HSEBYP bit */
 187   RCC->CR &= (uint32_t)0xFFFBFFFF;
 188
 189   /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
 190   RCC->CFGR &= (uint32_t)0xFFC0FFFF;
 191
 192   /* Reset PREDIV[3:0] bits */
 193   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 194
 195 #if defined (STM32F072xB) || defined (STM32F078xB)
 196   /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
 197   RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
 198 #elif defined (STM32F071xB)
 199   /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
 200   RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
 201 #elif defined (STM32F091xC) || defined (STM32F098xx)
 202   /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
 203   RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
 204 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
 205   /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
 206   RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
 207 #elif defined (STM32F051x8) || defined (STM32F058xx)
 208   /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
 209   RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
 210 #elif defined (STM32F042x6) || defined (STM32F048xx)
 211   /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
 212   RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
 213 #elif defined (STM32F070x6) || defined (STM32F070xB)
 214   /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
 215   RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
 216   /* Set default USB clock to PLLCLK, since there is no HSI48 */
 217   RCC->CFGR3 |= (uint32_t)0x00000080;
 218 #else
 219  #warning "No target selected"
 220 #endif
 221
 222   /* Reset HSI14 bit */
 223   RCC->CR2 &= (uint32_t)0xFFFFFFFE;
 224
 225   /* Disable all interrupts */
 226   RCC->CIR = 0x00000000;
 227
 228   /* Configure the Cube driver */
 229   SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
 230   HAL_Init();
 231
 232   /* Configure the System clock source, PLL Multiplier and Divider factors,
 233      AHB/APBx prescalers and Flash settings */
 234   SetSysClock();
 235 }
 236
 237 /**
 238    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 239   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 240   *         be used by the user application to setup the SysTick timer or configure
 241   *         other parameters.
 242   *
 243   * @note   Each time the core clock (HCLK) changes, this function must be called
 244   *         to update SystemCoreClock variable value. Otherwise, any configuration
 245   *         based on this variable will be incorrect.
 246   *
 247   * @note   - The system frequency computed by this function is not the real
 248   *           frequency in the chip. It is calculated based on the predefined
 249   *           constant and the selected clock source:
 250   *
 251   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 252   *
 253   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 254   *
 255   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 256   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 257   *
 258   *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
 259   *             8 MHz) but the real value may vary depending on the variations
 260   *             in voltage and temperature.
 261   *
 262   *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
 263   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 264   *              frequency of the crystal used. Otherwise, this function may
 265   *              have wrong result.
 266   *
 267   *         - The result of this function could be not correct when using fractional
 268   *           value for HSE crystal.
 269   *
 270   * @param  None
 271   * @retval None
 272   */
 273 void SystemCoreClockUpdate (void)
 274 {
 275   uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
 276
 277   /* Get SYSCLK source -------------------------------------------------------*/
 278   tmp = RCC->CFGR & RCC_CFGR_SWS;
 279
 280   switch (tmp)
 281   {
 282     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
 283       SystemCoreClock = HSI_VALUE;
 284       break;
 285     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
 286       SystemCoreClock = HSE_VALUE;
 287       break;
 288     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 289       /* Get PLL clock source and multiplication factor ----------------------*/
 290       pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
 291       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 292       pllmull = ( pllmull >> 18) + 2;
 293       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 294
 295       if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
 296       {
 297         /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
 298         SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
 299       }
 300 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
 301       else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
 302       {
 303         /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
 304         SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
 305       }
 306 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
 307       else
 308       {
 309 #if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) || \
 310     defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) || defined(STM32F070xB) || \
 311     defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
 312         /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
 313         SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
 314 #else
 315         /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
 316         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 317 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
 318           STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
 319           STM32F091xC || STM32F098xx || STM32F030xC */
 320       }
 321       break;
 322     default: /* HSI used as system clock */
 323       SystemCoreClock = HSI_VALUE;
 324       break;
 325   }
 326   /* Compute HCLK clock frequency ----------------*/
 327   /* Get HCLK prescaler */
 328   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 329   /* HCLK clock frequency */
 330   SystemCoreClock >>= tmp;
 331 }
 332
 333 /**
 334   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 335   *               AHB/APBx prescalers and Flash settings
 336   * @note   This function should be called only once the RCC clock configuration
 337   *         is reset to the default reset state (done in SystemInit() function).
 338   * @param  None
 339   * @retval None
 340   */
 341 void SetSysClock(void)
 342 {
 343   /* 1- Try to start with HSE and external clock */
 344 #if USE_PLL_HSE_EXTC != 0
 345   if (SetSysClock_PLL_HSE(1) == 0)
 346 #endif
 347   {
 348     /* 2- If fail try to start with HSE and external xtal */
 349     #if USE_PLL_HSE_XTAL != 0
 350     if (SetSysClock_PLL_HSE(0) == 0)
 351     #endif
 352     {
 353       /* 3- If fail start with HSI clock */
 354       if (SetSysClock_PLL_HSI() == 0)
 355       {
 356         while(1)
 357         {
 358           // [TODO] Put something here to tell the user that a problem occured...
 359         }
 360       }
 361     }
 362   }
 363
 364   // Output clock on MCO pin(PA8) for debugging purpose
 365   //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
 366 }
 367
 368 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 369 /******************************************************************************/
 370 /*            PLL (clocked by HSE) used as System clock source                */
 371 /******************************************************************************/
 372 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 373 {
 374   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 375   RCC_OscInitTypeDef RCC_OscInitStruct;
 376
 377   // Select HSE oscillator as PLL source
 378   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
 379   if (bypass == 0) {
 380       RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
 381   } else {
 382       RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
 383   }
 384   RCC_OscInitStruct.HSI48State     = 0; // not used
 385   RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
 386   RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
 387   RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
 388   RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
 389   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 390       return 0; // FAIL
 391   }
 392
 393   // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
 394   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
 395   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
 396   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
 397   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
 398   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
 399       return 0; // FAIL
 400   }
 401
 402   return 1; // OK
 403 }
 404 #endif
 405
 406 /******************************************************************************/
 407 /*            PLL (clocked by HSI) used as System clock source                */
 408 /******************************************************************************/
 409 uint8_t SetSysClock_PLL_HSI(void)
 410 {
 411   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 412   RCC_OscInitTypeDef RCC_OscInitStruct;
 413
 414   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
 415   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 416         RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
 417   RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
 418   RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
 419   RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
 420   RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
 421   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 422       return 0; // FAIL
 423   }
 424
 425   // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
 426   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
 427   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
 428   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
 429   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
 430   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
 431       return 0; // FAIL
 432   }
 433
 434   return 1; // OK
 435 }
 436
 437 /* Used for the different timeouts in the HAL */
 438 void SysTick_Handler(void)
 439 {
 440   HAL_IncTick();
 441 }
 442
 443 /**
 444   * @}
 445   */
 446
 447 /**
 448   * @}
 449   */
 450
 451 /**
 452   * @}
 453   */
 454
 455 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 456