tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f0xx_hal_can.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    11-December-2014
   7   * @brief   Header file of CAN HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F0xx_HAL_CAN_H
  40 #define __STM32F0xx_HAL_CAN_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 #if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
  47
  48 /* Includes ------------------------------------------------------------------*/
  49 #include "stm32f0xx_hal_def.h"
  50
  51 /** @addtogroup STM32F0xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup CAN CAN HAL Module Driver
  56   * @{
  57   */
  58
  59 /* Exported types ------------------------------------------------------------*/
  60 /** @defgroup CAN_Exported_Types CAN Exported Types
  61   * @{
  62   */
  63 /**
  64   * @brief  HAL State structures definition
  65   */
  66 typedef enum
  67 {
  68   HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
  69   HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */
  70   HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */
  71   HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */
  72   HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */
  73   HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
  74   HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< CAN in Timeout state                */
  75   HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */
  76
  77 }HAL_CAN_StateTypeDef;
  78
  79 /**
  80   * @brief  CAN init structure definition
  81   */
  82 typedef struct
  83 {
  84   uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
  85                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
  86
  87   uint32_t Mode;       /*!< Specifies the CAN operating mode.
  88                             This parameter can be a value of @ref CAN_operating_mode */
  89
  90   uint32_t SJW;        /*!< Specifies the maximum number of time quanta
  91                             the CAN hardware is allowed to lengthen or
  92                             shorten a bit to perform resynchronization.
  93                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
  94
  95   uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
  96                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
  97
  98   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
  99                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
 100
 101   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
 102                             This parameter can be set to ENABLE or DISABLE. */
 103
 104   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
 105                             This parameter can be set to ENABLE or DISABLE. */
 106
 107   uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
 108                             This parameter can be set to ENABLE or DISABLE. */
 109
 110   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
 111                             This parameter can be set to ENABLE or DISABLE. */
 112
 113   uint32_t RFLM;       /*!< Enable or disable the Receive FIFO Locked mode.
 114                             This parameter can be set to ENABLE or DISABLE. */
 115
 116   uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
 117                             This parameter can be set to ENABLE or DISABLE. */
 118 }CAN_InitTypeDef;
 119
 120 /**
 121   * @brief  CAN filter configuration structure definition
 122   */
 123 typedef struct
 124 {
 125   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
 126                                        configuration, first one for a 16-bit configuration).
 127                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 128
 129   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
 130                                        configuration, second one for a 16-bit configuration).
 131                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 132
 133   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
 134                                        according to the mode (MSBs for a 32-bit configuration,
 135                                        first one for a 16-bit configuration).
 136                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 137
 138   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
 139                                        according to the mode (LSBs for a 32-bit configuration,
 140                                        second one for a 16-bit configuration).
 141                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 142
 143   uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
 144                                        This parameter can be a value of @ref CAN_filter_FIFO */
 145
 146   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
 147                                        This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
 148
 149   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
 150                                        This parameter can be a value of @ref CAN_filter_mode */
 151
 152   uint32_t FilterScale;           /*!< Specifies the filter scale.
 153                                        This parameter can be a value of @ref CAN_filter_scale */
 154
 155   uint32_t FilterActivation;      /*!< Enable or disable the filter.
 156                                        This parameter can be set to ENABLE or DISABLE. */
 157
 158   uint32_t BankNumber;            /*!< Select the start slave bank filter
 159                                        This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
 160
 161 }CAN_FilterConfTypeDef;
 162
 163 /**
 164   * @brief  CAN Tx message structure definition
 165   */
 166 typedef struct
 167 {
 168   uint32_t StdId;    /*!< Specifies the standard identifier.
 169                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
 170
 171   uint32_t ExtId;    /*!< Specifies the extended identifier.
 172                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
 173
 174   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
 175                           This parameter can be a value of @ref CAN_identifier_type */
 176
 177   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
 178                           This parameter can be a value of @ref CAN_remote_transmission_request */
 179
 180   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
 181                           This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 182
 183   uint32_t Data[8];  /*!< Contains the data to be transmitted.
 184                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
 185
 186 }CanTxMsgTypeDef;
 187
 188 /**
 189   * @brief  CAN Rx message structure definition
 190   */
 191 typedef struct
 192 {
 193   uint32_t StdId;       /*!< Specifies the standard identifier.
 194                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
 195
 196   uint32_t ExtId;       /*!< Specifies the extended identifier.
 197                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
 198
 199   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
 200                              This parameter can be a value of @ref CAN_identifier_type */
 201
 202   uint32_t RTR;         /*!< Specifies the type of frame for the received message.
 203                              This parameter can be a value of @ref CAN_remote_transmission_request */
 204
 205   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
 206                              This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 207
 208   uint32_t Data[8];     /*!< Contains the data to be received.
 209                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
 210
 211   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
 212                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
 213
 214   uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
 215                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
 216
 217 }CanRxMsgTypeDef;
 218
 219 /**
 220   * @brief  CAN handle Structure definition
 221   */
 222 typedef struct
 223 {
 224   CAN_TypeDef                 *Instance;  /*!< Register base address          */
 225
 226   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
 227
 228   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
 229
 230   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
 231
 232   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
 233
 234   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
 235
 236   __IO uint32_t               ErrorCode;  /*!< CAN Error code
 237                                                This parameter can be a value of @ref CAN_Error */
 238
 239 }CAN_HandleTypeDef;
 240 /**
 241   * @}
 242   */
 243
 244 /* Exported constants --------------------------------------------------------*/
 245
 246 /** @defgroup CAN_Exported_Constants CAN Exported Constants
 247   * @{
 248   */
 249
 250 /** @defgroup CAN_Error CAN Error
 251   * @{
 252   */
 253 #define HAL_CAN_ERROR_NONE              ((uint32_t)0x00000000)  /*!< No error             */
 254 #define HAL_CAN_ERROR_EWG               ((uint32_t)0x00000001)  /*!< EWG error            */
 255 #define HAL_CAN_ERROR_EPV               ((uint32_t)0x00000002)  /*!< EPV error            */
 256 #define HAL_CAN_ERROR_BOF               ((uint32_t)0x00000004)  /*!< BOF error            */
 257 #define HAL_CAN_ERROR_STF               ((uint32_t)0x00000008)  /*!< Stuff error          */
 258 #define HAL_CAN_ERROR_FOR               ((uint32_t)0x00000010)  /*!< Form error           */
 259 #define HAL_CAN_ERROR_ACK               ((uint32_t)0x00000020)  /*!< Acknowledgment error */
 260 #define HAL_CAN_ERROR_BR                ((uint32_t)0x00000040)  /*!< Bit recessive        */
 261 #define HAL_CAN_ERROR_BD                ((uint32_t)0x00000080)  /*!< LEC dominant         */
 262 #define HAL_CAN_ERROR_CRC               ((uint32_t)0x00000100)  /*!< LEC transfer error   */
 263 /**
 264   * @}
 265   */
 266
 267 /** @defgroup CAN_InitStatus CAN InitStatus
 268   * @{
 269   */
 270 #define CAN_INITSTATUS_FAILED       ((uint32_t)0x00000000)  /*!< CAN initialization failed */
 271 #define CAN_INITSTATUS_SUCCESS      ((uint32_t)0x00000001)  /*!< CAN initialization OK */
 272 /**
 273   * @}
 274   */
 275
 276 /** @defgroup CAN_operating_mode CAN operating mode
 277   * @{
 278   */
 279 #define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
 280 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
 281 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
 282 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
 283
 284 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
 285                            ((MODE) == CAN_MODE_LOOPBACK)|| \
 286                            ((MODE) == CAN_MODE_SILENT) || \
 287                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
 288 /**
 289   * @}
 290   */
 291
 292
 293 /** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width
 294   * @{
 295   */
 296 #define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
 297 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
 298 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
 299 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
 300
 301 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
 302                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
 303 /**
 304   * @}
 305   */
 306
 307 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1
 308   * @{
 309   */
 310 #define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
 311 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
 312 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
 313 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
 314 #define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
 315 #define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
 316 #define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
 317 #define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
 318 #define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
 319 #define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
 320 #define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
 321 #define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
 322 #define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
 323 #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
 324 #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
 325 #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
 326
 327 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
 328 /**
 329   * @}
 330   */
 331
 332 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2
 333   * @{
 334   */
 335 #define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
 336 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
 337 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
 338 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
 339 #define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
 340 #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
 341 #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
 342 #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
 343
 344 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
 345 /**
 346   * @}
 347   */
 348
 349 /** @defgroup CAN_clock_prescaler CAN clock prescaler
 350   * @{
 351   */
 352 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
 353 /**
 354   * @}
 355   */
 356
 357 /** @defgroup CAN_filter_number CAN filter number
 358   * @{
 359   */
 360 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
 361 /**
 362   * @}
 363   */
 364
 365 /** @defgroup CAN_filter_mode CAN filter mode
 366   * @{
 367   */
 368 #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
 369 #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
 370
 371 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
 372                                   ((MODE) == CAN_FILTERMODE_IDLIST))
 373 /**
 374   * @}
 375   */
 376
 377 /** @defgroup CAN_filter_scale CAN filter scale
 378   * @{
 379   */
 380 #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
 381 #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
 382
 383 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
 384                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
 385 /**
 386   * @}
 387   */
 388
 389 /** @defgroup CAN_filter_FIFO CAN filter FIFO
 390   * @{
 391   */
 392 #define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
 393 #define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
 394
 395 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
 396                                   ((FIFO) == CAN_FILTER_FIFO1))
 397
 398 /* Legacy defines */
 399 #define CAN_FilterFIFO0  CAN_FILTER_FIFO0
 400 #define CAN_FilterFIFO1  CAN_FILTER_FIFO1
 401 /**
 402   * @}
 403   */
 404
 405 /** @defgroup CAN_Start_bank_filter_for_slave_CAN CAN Start bank filter for slave CAN
 406   * @{
 407   */
 408 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
 409 /**
 410   * @}
 411   */
 412
 413 /** @defgroup CAN_Tx CAN Tx
 414   * @{
 415   */
 416 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
 417 #define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
 418 #define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
 419 #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
 420 /**
 421   * @}
 422   */
 423
 424 /** @defgroup CAN_identifier_type  CAN identifier type
 425   * @{
 426   */
 427 #define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
 428 #define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
 429 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
 430                                 ((IDTYPE) == CAN_ID_EXT))
 431 /**
 432   * @}
 433   */
 434
 435 /** @defgroup CAN_remote_transmission_request CAN remote transmission request
 436   * @{
 437   */
 438 #define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
 439 #define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
 440 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
 441
 442 /**
 443   * @}
 444   */
 445
 446 /** @defgroup CAN_transmit_constants CAN transmit constants
 447   * @{
 448   */
 449 #define CAN_TXSTATUS_FAILED         ((uint8_t)0x00)  /*!< CAN transmission failed */
 450 #define CAN_TXSTATUS_OK             ((uint8_t)0x01)  /*!< CAN transmission succeeded */
 451 #define CAN_TXSTATUS_PENDING        ((uint8_t)0x02)  /*!< CAN transmission pending */
 452 #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
 453
 454 /**
 455   * @}
 456   */
 457
 458 /** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants
 459   * @{
 460   */
 461 #define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
 462 #define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
 463
 464 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
 465 /**
 466   * @}
 467   */
 468
 469 /** @defgroup CAN_flags CAN flags
 470   * @{
 471   */
 472 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
 473    and CAN_ClearFlag() functions. */
 474 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
 475    CAN_GetFlagStatus() function.  */
 476
 477 /* Transmit Flags */
 478 #define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
 479 #define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
 480 #define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
 481 #define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
 482 #define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
 483 #define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
 484 #define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
 485 #define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
 486 #define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
 487
 488 /* Receive Flags */
 489 #define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
 490 #define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
 491
 492 #define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
 493 #define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
 494
 495 /* Operating Mode Flags */
 496 #define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
 497 #define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
 498 #define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
 499 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
 500          In this case the SLAK bit can be polled.*/
 501
 502 /* Error Flags */
 503 #define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
 504 #define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
 505 #define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
 506 /**
 507   * @}
 508   */
 509
 510
 511 /** @defgroup CAN_interrupts CAN interrupts
 512   * @{
 513   */
 514 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
 515
 516 /* Receive Interrupts */
 517 #define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
 518 #define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
 519 #define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
 520 #define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
 521 #define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
 522 #define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
 523
 524 /* Operating Mode Interrupts */
 525 #define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
 526 #define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
 527
 528 /* Error Interrupts */
 529 #define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
 530 #define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
 531 #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
 532 #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
 533 #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
 534
 535 /* Flags named as Interrupts : kept only for FW compatibility */
 536 #define CAN_IT_RQCP0   CAN_IT_TME
 537 #define CAN_IT_RQCP1   CAN_IT_TME
 538 #define CAN_IT_RQCP2   CAN_IT_TME
 539 /**
 540   * @}
 541   */
 542
 543 /** @defgroup CAN_Timeouts CAN Timeouts
 544 * @{
 545 */
 546
 547 /* Time out for INAK bit */
 548 #define INAK_TIMEOUT      ((uint32_t)0x00FFFFFF)
 549 /* Time out for SLAK bit */
 550 #define SLAK_TIMEOUT      ((uint32_t)0x00FFFFFF)
 551 /**
 552   * @}
 553   */
 554
 555 /** @defgroup CAN_Mailboxes CAN Mailboxes
 556 * @{
 557 */
 558 /* Mailboxes definition */
 559 #define CAN_TXMAILBOX_0   ((uint8_t)0x00)
 560 #define CAN_TXMAILBOX_1   ((uint8_t)0x01)
 561 #define CAN_TXMAILBOX_2   ((uint8_t)0x02)
 562 /**
 563   * @}
 564   */
 565
 566 /**
 567   * @}
 568   */
 569
 570 /* Exported macros -----------------------------------------------------------*/
 571 /** @defgroup CAN_Exported_Macros CAN Exported Macros
 572   * @{
 573   */
 574
 575 /** @brief  Reset CAN handle state
 576   * @param  __HANDLE__: CAN handle.
 577   * @retval None
 578   */
 579 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
 580
 581 /**
 582   * @brief  Enable the specified CAN interrupts.
 583   * @param  __HANDLE__: CAN handle.
 584   * @param  __INTERRUPT__: CAN Interrupt
 585   * @retval None
 586   */
 587 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
 588
 589 /**
 590   * @brief  Disable the specified CAN interrupts.
 591   * @param  __HANDLE__: CAN handle.
 592   * @param  __INTERRUPT__: CAN Interrupt
 593   * @retval None
 594   */
 595 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
 596
 597 /**
 598   * @brief  Return the number of pending received messages.
 599   * @param  __HANDLE__: CAN handle.
 600   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
 601   * @retval The number of pending message.
 602   */
 603 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
 604 ((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
 605
 606 /** @brief  Check whether the specified CAN flag is set or not.
 607   * @param  __HANDLE__: specifies the CAN Handle.
 608   * @param  __FLAG__: specifies the flag to check.
 609   *        This parameter can be one of the following values:
 610   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
 611   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
 612   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
 613   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
 614   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
 615   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
 616   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
 617   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
 618   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
 619   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
 620   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
 621   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
 622   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
 623   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
 624   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
 625   *            @arg CAN_FLAG_WKU: Wake up Flag
 626   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
 627   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
 628   *            @arg CAN_FLAG_EWG: Error Warning Flag
 629   *            @arg CAN_FLAG_EPV: Error Passive Flag
 630   *            @arg CAN_FLAG_BOF: Bus-Off Flag
 631   * @retval The new state of __FLAG__ (TRUE or FALSE).
 632   */
 633 #define CAN_FLAG_MASK  ((uint32_t)0x000000FF)
 634 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
 635 ((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 636  (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 637  (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 638  (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
 639  ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
 640
 641 /** @brief  Clear the specified CAN pending flag.
 642   * @param  __HANDLE__: specifies the CAN Handle.
 643   * @param  __FLAG__: specifies the flag to check.
 644   *        This parameter can be one of the following values:
 645   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
 646   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
 647   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
 648   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
 649   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
 650   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
 651   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
 652   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
 653   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
 654   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
 655   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
 656   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
 657   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
 658   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
 659   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
 660   *            @arg CAN_FLAG_WKU: Wake up Flag
 661   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
 662   *            @arg CAN_FLAG_EWG: Error Warning Flag
 663   *            @arg CAN_FLAG_EPV: Error Passive Flag
 664   *            @arg CAN_FLAG_BOF: Bus-Off Flag
 665   * @retval The new state of __FLAG__ (TRUE or FALSE).
 666   */
 667 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
 668 ((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 669  (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 670  (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 671  (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
 672
 673
 674 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
 675   * @param  __HANDLE__: specifies the CAN Handle.
 676   * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
 677   *          This parameter can be one of the following values:
 678   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
 679   *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
 680   *            @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
 681   * @retval The new state of __IT__ (TRUE or FALSE).
 682   */
 683 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 684
 685 /**
 686   * @brief  Check the transmission status of a CAN Frame.
 687   * @param  __HANDLE__: CAN handle.
 688   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
 689   * @retval The new status of transmission  (TRUE or FALSE).
 690   */
 691 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
 692 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
 693  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
 694  ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
 695
 696
 697
 698 /**
 699   * @brief  Release the specified receive FIFO.
 700   * @param  __HANDLE__: CAN handle.
 701   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
 702   * @retval None
 703   */
 704 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
 705 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
 706
 707 /**
 708   * @brief  Cancel a transmit request.
 709   * @param  __HANDLE__: specifies the CAN Handle.
 710   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
 711   * @retval None
 712   */
 713 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
 714 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
 715  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
 716  ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
 717
 718 /**
 719   * @brief  Enable or disables the DBG Freeze for CAN.
 720   * @param  __HANDLE__: specifies the CAN Handle.
 721   * @param  __NEWSTATE__: new state of the CAN peripheral.
 722   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
 723   *         during debug. Reception FIFOs can still be accessed/controlled normally)
 724   *         or DISABLE (CAN is working during debug).
 725   * @retval None
 726   */
 727 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
 728 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
 729
 730 /**
 731   * @}
 732   */
 733
 734 /* Exported functions --------------------------------------------------------*/
 735 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
 736   * @{
 737   */
 738
 739 /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
 740  *  @brief    Initialization and Configuration functions
 741  * @{
 742  */
 743
 744 /* Initialization and de-initialization functions *****************************/
 745 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
 746 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
 747 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
 748 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
 749 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
 750 /**
 751   * @}
 752   */
 753
 754 /** @addtogroup CAN_Exported_Functions_Group2 I/O operation functions
 755  *  @brief    I/O operation functions
 756  * @{
 757  */
 758
 759 /* IO operation functions *****************************************************/
 760 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
 761 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
 762 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
 763 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
 764 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
 765 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
 766
 767 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
 768
 769 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
 770 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
 771 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
 772 /**
 773   * @}
 774   */
 775
 776 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
 777  *  @brief   CAN Peripheral State functions
 778  * @{
 779  */
 780 /* Peripheral State and Error functions ***************************************/
 781 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
 782 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
 783
 784 /**
 785   * @}
 786   */
 787
 788 /**
 789   * @}
 790   */
 791
 792 /**
 793   * @}
 794   */
 795
 796 /**
 797   * @}
 798   */
 799
 800 #endif /* STM32F072xB || STM32F042x6 || STM32F048xx  || STM32F078xx || STM32F091xC || STM32F098xx */
 801
 802 #ifdef __cplusplus
 803 }
 804 #endif
 805
 806 #endif /* __STM32F0xx_HAL_CAN_H */
 807
 808
 809 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 810