tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f0xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    11-December-2014
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F0xx_HAL_DMA_H
  40 #define __STM32F0xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f0xx_hal_def.h"
  48
  49 /** @addtogroup STM32F0xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup DMA
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup DMA_Exported_Types DMA Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  DMA Configuration Structure definition
  64   */
  65 typedef struct
  66 {
  67   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  68                                            from memory to memory or from peripheral to memory.
  69                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  70
  71   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  72                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  73
  74   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  75                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  76
  77   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  78                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  79
  80   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  81                                            This parameter can be a value of @ref DMA_Memory_data_size */
  82
  83   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  84                                            This parameter can be a value of @ref DMA_mode
  85                                            @note The circular buffer mode cannot be used if the memory-to-memory
  86                                                  data transfer is configured on the selected Channel */
  87
  88   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
  89                                             This parameter can be a value of @ref DMA_Priority_level */
  90
  91 } DMA_InitTypeDef;
  92
  93 /**
  94   * @brief DMA Configuration enumeration values definition
  95   */
  96 typedef enum
  97 {
  98   DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
  99   DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
 100
 101 } DMA_ControlTypeDef;
 102
 103 /**
 104   * @brief  HAL DMA State structures definition
 105   */
 106 typedef enum
 107 {
 108   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
 109   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use   */
 110   HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
 111   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
 112   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
 113   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
 114
 115 }HAL_DMA_StateTypeDef;
 116
 117 /**
 118   * @brief  HAL DMA Error Code structure definition
 119   */
 120 typedef enum
 121 {
 122   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
 123   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
 124
 125 }HAL_DMA_LevelCompleteTypeDef;
 126
 127
 128 /**
 129   * @brief  DMA handle Structure definition
 130   */
 131 typedef struct __DMA_HandleTypeDef
 132 {
 133   DMA_Channel_TypeDef   *Instance;                                                    /*!< Register base address                  */
 134
 135   DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */
 136
 137   HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */
 138
 139   HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 140
 141   void                  *Parent;                                                      /*!< Parent object state                    */
 142
 143   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 144
 145   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 146
 147   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 148
 149   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
 150
 151 } DMA_HandleTypeDef;
 152 /**
 153   * @}
 154   */
 155
 156 /* Exported constants --------------------------------------------------------*/
 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 158   * @{
 159   */
 160
 161 /** @defgroup DMA_Error_Code DMA Error Code
 162   * @{
 163   */
 164 #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
 165 #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
 166 #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
 167 /**
 168   * @}
 169   */
 170
 171 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 172   * @{
 173   */
 174 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
 175 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
 176 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction     */
 177
 178 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 179                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 180                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 181 /**
 182   * @}
 183   */
 184
 185 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
 186   * @{
 187   */
 188 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 189 /**
 190   * @}
 191   */
 192
 193 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 194   * @{
 195   */
 196 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
 197 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
 198
 199 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 200                                             ((STATE) == DMA_PINC_DISABLE))
 201 /**
 202   * @}
 203   */
 204
 205 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 206   * @{
 207   */
 208 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
 209 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
 210
 211 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 212                                         ((STATE) == DMA_MINC_DISABLE))
 213 /**
 214   * @}
 215   */
 216
 217 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 218   * @{
 219   */
 220 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
 221 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
 222 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
 223
 224 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 225                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 226                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 227 /**
 228   * @}
 229   */
 230
 231
 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
 233   * @{
 234   */
 235 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
 236 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
 237 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
 238
 239 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 240                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 241                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 242 /**
 243   * @}
 244   */
 245
 246 /** @defgroup DMA_mode DMA mode
 247   * @{
 248   */
 249 #define DMA_NORMAL         ((uint32_t)0x00000000)      /*!< Normal Mode                  */
 250 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
 251
 252 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 253                            ((MODE) == DMA_CIRCULAR))
 254 /**
 255   * @}
 256   */
 257
 258 /** @defgroup DMA_Priority_level DMA Priority level
 259   * @{
 260   */
 261 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
 262 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
 263 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
 264 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
 265
 266 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 267                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 268                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 269                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 270 /**
 271   * @}
 272   */
 273
 274
 275 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 276   * @{
 277   */
 278
 279 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
 280 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
 281 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
 282
 283 /**
 284   * @}
 285   */
 286
 287 /** @defgroup DMA_flag_definitions DMA flag definitions
 288   * @{
 289   */
 290
 291 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag  */
 292 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
 293 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag     */
 294 #define DMA_FLAG_TE1                      ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag    */
 295 #define DMA_FLAG_GL2                      ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag  */
 296 #define DMA_FLAG_TC2                      ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
 297 #define DMA_FLAG_HT2                      ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag     */
 298 #define DMA_FLAG_TE2                      ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag    */
 299 #define DMA_FLAG_GL3                      ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag  */
 300 #define DMA_FLAG_TC3                      ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
 301 #define DMA_FLAG_HT3                      ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag     */
 302 #define DMA_FLAG_TE3                      ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag    */
 303 #define DMA_FLAG_GL4                      ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag  */
 304 #define DMA_FLAG_TC4                      ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
 305 #define DMA_FLAG_HT4                      ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag     */
 306 #define DMA_FLAG_TE4                      ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag    */
 307 #define DMA_FLAG_GL5                      ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag  */
 308 #define DMA_FLAG_TC5                      ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
 309 #define DMA_FLAG_HT5                      ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag     */
 310 #define DMA_FLAG_TE5                      ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag    */
 311 #define DMA_FLAG_GL6                      ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag  */
 312 #define DMA_FLAG_TC6                      ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
 313 #define DMA_FLAG_HT6                      ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag     */
 314 #define DMA_FLAG_TE6                      ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag    */
 315 #define DMA_FLAG_GL7                      ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag  */
 316 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
 317 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag     */
 318 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag    */
 319
 320
 321 /**
 322   * @}
 323   */
 324
 325 /**
 326   * @}
 327   */
 328
 329 /* Exported macros -----------------------------------------------------------*/
 330 /** @defgroup DMA_Exported_Macros DMA Exported Macros
 331   * @{
 332   */
 333
 334 /** @brief  Reset DMA handle state
 335   * @param  __HANDLE__: DMA handle.
 336   * @retval None
 337   */
 338 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 339
 340 /**
 341   * @brief  Enable the specified DMA Channel.
 342   * @param  __HANDLE__: DMA handle
 343   * @retval None.
 344   */
 345 #define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
 346
 347 /**
 348   * @brief  Disable the specified DMA Channel.
 349   * @param  __HANDLE__: DMA handle
 350   * @retval None.
 351   */
 352 #define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
 353
 354
 355 /* Interrupt & Flag management */
 356
 357 /**
 358   * @brief  Enables the specified DMA Channel interrupts.
 359   * @param  __HANDLE__: DMA handle
 360   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 361   *          This parameter can be any combination of the following values:
 362   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 363   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 364   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 365   * @retval None
 366   */
 367 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
 368
 369 /**
 370   * @brief  Disables the specified DMA Channel interrupts.
 371   * @param  __HANDLE__: DMA handle
 372   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 373   *          This parameter can be any combination of the following values:
 374   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 375   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 376   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 377   * @retval None
 378   */
 379 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
 380
 381 /**
 382   * @brief  Checks whether the specified DMA Channel interrupt has occurred or not.
 383   * @param  __HANDLE__: DMA handle
 384   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 385   *          This parameter can be one of the following values:
 386   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 387   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 388   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 389   * @retval The state of DMA_IT (SET or RESET).
 390   */
 391 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 392
 393 /**
 394   * @}
 395   */
 396
 397 /* Include DMA HAL Extension module */
 398 #include "stm32f0xx_hal_dma_ex.h"
 399
 400 /* Exported functions --------------------------------------------------------*/
 401 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
 402   * @{
 403   */
 404 /** @addtogroup DMA_Exported_Functions_Group1
 405  *  @brief   Initialization and de-initialization functions
 406   * @{
 407   */
 408 /* Initialization and de-initialization functions *****************************/
 409 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 410 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
 411 /**
 412   * @}
 413   */
 414
 415 /** @addtogroup DMA_Exported_Functions_Group2
 416  *  @brief   I/O operation functions
 417   * @{
 418   */
 419 /* IO operation functions *****************************************************/
 420 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 422 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 423 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 424 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 425 /**
 426   * @}
 427   */
 428
 429 /* Peripheral State and Error functions ***************************************/
 430 /** @addtogroup DMA_Exported_Functions_Group3
 431   *  @brief    Peripheral State functions
 432   * @{
 433   */
 434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 435 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 436 /**
 437   * @}
 438   */
 439
 440 /**
 441   * @}
 442   */
 443
 444 /**
 445   * @}
 446   */
 447
 448 /**
 449   * @}
 450   */
 451
 452 #ifdef __cplusplus
 453 }
 454 #endif
 455
 456 #endif /* __STM32F0xx_HAL_DMA_H */
 457
 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 459