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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F1 / stm32f1xx_hal_adc.c
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_adc.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Analog to Digital Convertor (ADC)
9 * peripheral:
10 * + Initialization and de-initialization functions
11 * ++ Initialization and Configuration of ADC
12 * + Operation functions
13 * ++ Start, stop, get result of conversions of regular
14 * group, using 3 possible modes: polling, interruption or DMA.
15 * + Control functions
16 * ++ Channels configuration on regular group
17 * ++ Channels configuration on injected group
18 * ++ Analog Watchdog configuration
19 * + State functions
20 * ++ ADC state machine management
21 * ++ Interrupts and flags management
22 * Other functions (extended functions) are available in file
23 * "stm32f1xx_hal_adc_ex.c".
24 *
25 @verbatim
26 ==============================================================================
27 ##### ADC peripheral features #####
28 ==============================================================================
29 [..]
30 (+) 12-bit resolution
31
32 (+) Interrupt generation at the end of regular conversion, end of injected
33 conversion, and in case of analog watchdog or overrun events.
34
35 (+) Single and continuous conversion modes.
36
37 (+) Scan mode for automatic conversion of channel 0 to channel 'n'.
38
39 (+) Data alignment with in-built data coherency.
40
41 (+) Channel-wise programmable sampling time.
42
43 (+) ADC conversion Regular or Injected groups.
44
45 (+) External trigger (timer or EXTI) with configurable polarity for both
46 regular and injected groups.
47
48 (+) DMA request generation for transfer of conversions data of regular group.
49
50 (+) Multimode Dual mode (available on devices with 2 ADCs or more).
51
52 (+) Configurable DMA data storage in Multimode Dual mode (available on devices
53 with 2 DCs or more).
54
55 (+) Configurable delay between conversions in Dual interleaved mode (available
56 on devices with 2 DCs or more).
57
58 (+) ADC calibration
59
60 (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
61 slower speed.
62
63 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
64 Vdda or to an external voltage reference).
65
66
67 ##### How to use this driver #####
68 ==============================================================================
69 [..]
70
71 *** Configuration of top level parameters related to ADC ***
72 ============================================================
73 [..]
74
75 (#) Enable the ADC interface
76 (++) As prerequisite, ADC clock must be configured at RCC top level.
77 Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
78 to device datasheet).
79 Therefore, ADC clock prescaler must be configured in
80 function of ADC clock source frequency to remain
81 below this maximum frequency.
82 (++) One clock setting is mandatory:
83 ADC clock (core and conversion clock).
84 (+++) Example:
85 Into HAL_ADC_MspInit() (recommended code location) or with
86 other device clock parameters configuration:
87 (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit;
88 (+++) __ADC1_CLK_ENABLE();
89 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
90 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
91 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
92
93 (#) ADC pins configuration
94 (++) Enable the clock for the ADC GPIOs
95 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
96 (++) Configure these ADC pins in analog mode
97 using function HAL_GPIO_Init()
98
99 (#) Optionally, in case of usage of ADC with interruptions:
100 (++) Configure the NVIC for ADC
101 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
102 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
103 into the function of corresponding ADC interruption vector
104 ADCx_IRQHandler().
105
106 (#) Optionally, in case of usage of DMA:
107 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
108 using function HAL_DMA_Init().
109 (++) Configure the NVIC for DMA
110 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
111 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
112 into the function of corresponding DMA interruption vector
113 DMAx_Channelx_IRQHandler().
114
115 *** Configuration of ADC, groups regular/injected, channels parameters ***
116 ==========================================================================
117 [..]
118
119 (#) Configure the ADC parameters (resolution, data alignment, ...)
120 and regular group parameters (conversion trigger, sequencer, ...,
121 of regular group)
122 using function HAL_ADC_Init().
123
124 (#) Configure the channels for regular group parameters (channel number,
125 channel rank into sequencer, ..., into regular group)
126 using function HAL_ADC_ConfigChannel().
127
128 (#) Optionally, configure the injected group parameters (conversion trigger,
129 sequencer, ..., of injected group)
130 and the channels for injected group parameters (channel number,
131 channel rank into sequencer, ..., into injected group)
132 using function HAL_ADCEx_InjectedConfigChannel().
133
134 (#) Optionally, configure the analog watchdog parameters (channels
135 monitored, thresholds, ...)
136 using function HAL_ADC_AnalogWDGConfig().
137
138 (#) Optionally, for devices with several ADC instances: configure the
139 multimode parameters
140 using function HAL_ADCEx_MultiModeConfigChannel().
141
142 *** Execution of ADC conversions ***
143 ====================================
144 [..]
145
146 (#) Optionally, perform an automatic ADC calibration to improve the
147 conversion accuracy
148 using function HAL_ADCEx_Calibration_Start().
149
150 (#) ADC driver can be used among three modes: polling, interruption,
151 transfer by DMA.
152
153 (++) ADC conversion by polling:
154 (+++) Activate the ADC peripheral and start conversions
155 using function HAL_ADC_Start()
156 (+++) Wait for ADC conversion completion
157 using function HAL_ADC_PollForConversion()
158 (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
159 (+++) Retrieve conversion results
160 using function HAL_ADC_GetValue()
161 (or for injected group: HAL_ADCEx_InjectedGetValue() )
162 (+++) Stop conversion and disable the ADC peripheral
163 using function HAL_ADC_Stop()
164
165 (++) ADC conversion by interruption:
166 (+++) Activate the ADC peripheral and start conversions
167 using function HAL_ADC_Start_IT()
168 (+++) Wait for ADC conversion completion by call of function
169 HAL_ADC_ConvCpltCallback()
170 (this function must be implemented in user program)
171 (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
172 (+++) Retrieve conversion results
173 using function HAL_ADC_GetValue()
174 (or for injected group: HAL_ADCEx_InjectedGetValue() )
175 (+++) Stop conversion and disable the ADC peripheral
176 using function HAL_ADC_Stop_IT()
177
178 (++) ADC conversion with transfer by DMA:
179 (+++) Activate the ADC peripheral and start conversions
180 using function HAL_ADC_Start_DMA()
181 (+++) Wait for ADC conversion completion by call of function
182 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
183 (these functions must be implemented in user program)
184 (+++) Conversion results are automatically transferred by DMA into
185 destination variable address.
186 (+++) Stop conversion and disable the ADC peripheral
187 using function HAL_ADC_Stop_DMA()
188
189 (++) For devices with several ADCs: ADC multimode conversion
190 with transfer by DMA:
191 (+++) Activate the ADC peripheral (slave) and start conversions
192 using function HAL_ADC_Start()
193 (+++) Activate the ADC peripheral (master) and start conversions
194 using function HAL_ADCEx_MultiModeStart_DMA()
195 (+++) Wait for ADC conversion completion by call of function
196 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
197 (these functions must be implemented in user program)
198 (+++) Conversion results are automatically transferred by DMA into
199 destination variable address.
200 (+++) Stop conversion and disable the ADC peripheral (master)
201 using function HAL_ADCEx_MultiModeStop_DMA()
202 (+++) Stop conversion and disable the ADC peripheral (slave)
203 using function HAL_ADC_Stop_IT()
204
205 [..]
206
207 (@) Callback functions must be implemented in user program:
208 (+@) HAL_ADC_ErrorCallback()
209 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
210 (+@) HAL_ADC_ConvCpltCallback()
211 (+@) HAL_ADC_ConvHalfCpltCallback
212 (+@) HAL_ADCEx_InjectedConvCpltCallback()
213
214 *** Deinitialization of ADC ***
215 ============================================================
216 [..]
217
218 (#) Disable the ADC interface
219 (++) ADC clock can be hard reset and disabled at RCC top level.
220 (++) Hard reset of ADC peripherals
221 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
222 (++) ADC clock disable
223 using the equivalent macro/functions as configuration step.
224 (+++) Example:
225 Into HAL_ADC_MspDeInit() (recommended code location) or with
226 other device clock parameters configuration:
227 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
228 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
229 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
230
231 (#) ADC pins configuration
232 (++) Disable the clock for the ADC GPIOs
233 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
234
235 (#) Optionally, in case of usage of ADC with interruptions:
236 (++) Disable the NVIC for ADC
237 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
238
239 (#) Optionally, in case of usage of DMA:
240 (++) Deinitialize the DMA
241 using function HAL_DMA_Init().
242 (++) Disable the NVIC for DMA
243 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
244
245 [..]
246
247 @endverbatim
248 ******************************************************************************
249 * @attention
250 *
251 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
252 *
253 * Redistribution and use in source and binary forms, with or without modification,
254 * are permitted provided that the following conditions are met:
255 * 1. Redistributions of source code must retain the above copyright notice,
256 * this list of conditions and the following disclaimer.
257 * 2. Redistributions in binary form must reproduce the above copyright notice,
258 * this list of conditions and the following disclaimer in the documentation
259 * and/or other materials provided with the distribution.
260 * 3. Neither the name of STMicroelectronics nor the names of its contributors
261 * may be used to endorse or promote products derived from this software
262 * without specific prior written permission.
263 *
264 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
265 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
266 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
267 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
268 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
269 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
270 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
271 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
272 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
273 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
274 *
275 ******************************************************************************
276 */
277
278 /* Includes ------------------------------------------------------------------*/
279 #include "stm32f1xx_hal.h"
280
281 /** @addtogroup STM32F1xx_HAL_Driver
282 * @{
283 */
284
285 /** @defgroup ADC ADC
286 * @brief ADC HAL module driver
287 * @{
288 */
289
290 #ifdef HAL_ADC_MODULE_ENABLED
291
292 /* Private typedef -----------------------------------------------------------*/
293 /* Private define ------------------------------------------------------------*/
294 /** @defgroup ADC_Private_Constants ADC Private Constants
295 * @{
296 */
297
298 /* Timeout values for ADC enable and disable settling time. */
299 /* Values defined to be higher than worst cases: low clocks freq, */
300 /* maximum prescaler. */
301 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
302 /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
303 /* Unit: ms */
304 #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
305 #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
306
307 /* Delay for ADC stabilization time. */
308 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
309 /* Unit: us */
310 #define ADC_STAB_DELAY_US ((uint32_t) 1)
311
312 /* Delay for temperature sensor stabilization time. */
313 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
314 /* Unit: us */
315 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
316
317 /**
318 * @}
319 */
320
321 /* Private macro -------------------------------------------------------------*/
322 /* Private variables ---------------------------------------------------------*/
323 /* Private function prototypes -----------------------------------------------*/
324 /** @defgroup ADC_Private_Functions ADC Private Functions
325 * @{
326 */
327 /**
328 * @}
329 */
330
331 /* Exported functions --------------------------------------------------------*/
332
333 /** @defgroup ADC_Exported_Functions ADC Exported Functions
334 * @{
335 */
336
337 /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
338 * @brief Initialization and Configuration functions
339 *
340 @verbatim
341 ===============================================================================
342 ##### Initialization and de-initialization functions #####
343 ===============================================================================
344 [..] This section provides functions allowing to:
345 (+) Initialize and configure the ADC.
346 (+) De-initialize the ADC.
347
348 @endverbatim
349 * @{
350 */
351
352 /**
353 * @brief Initializes the ADC peripheral and regular group according to
354 * parameters specified in structure "ADC_InitTypeDef".
355 * @note As prerequisite, ADC clock must be configured at RCC top level
356 * (clock source APB2).
357 * See commented example code below that can be copied and uncommented
358 * into HAL_ADC_MspInit().
359 * @note Possibility to update parameters on the fly:
360 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
361 * coming from ADC state reset. Following calls to this function can
362 * be used to reconfigure some parameters of ADC_InitTypeDef
363 * structure on the fly, without modifying MSP configuration. If ADC
364 * MSP has to be modified again, HAL_ADC_DeInit() must be called
365 * before HAL_ADC_Init().
366 * The setting of these parameters is conditioned to ADC state.
367 * For parameters constraints, see comments of structure
368 * "ADC_InitTypeDef".
369 * @note This function configures the ADC within 2 scopes: scope of entire
370 * ADC and scope of regular group. For parameters details, see comments
371 * of structure "ADC_InitTypeDef".
372 * @param hadc: ADC handle
373 * @retval HAL status
374 */
375 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
376 {
377 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
378 uint32_t tmp_cr1 = 0;
379 uint32_t tmp_cr2 = 0;
380 uint32_t tmp_sqr1 = 0;
381
382 /* Check ADC handle */
383 if(hadc == NULL)
384 {
385 return HAL_ERROR;
386 }
387
388 /* Check the parameters */
389 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
390 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
391 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
392 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
393 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
394
395 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
396 {
397 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
398 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
399 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
400 }
401
402 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
403 /* at RCC top level. */
404 /* Refer to header of this file for more details on clock enabling */
405 /* procedure. */
406
407 /* Actions performed only if ADC is coming from state reset: */
408 /* - Initialization of ADC MSP */
409 if (hadc->State == HAL_ADC_STATE_RESET)
410 {
411 /* Allocate lock resource and initialize it */
412 hadc-> Lock = HAL_UNLOCKED;
413
414 /* Init the low level hardware */
415 HAL_ADC_MspInit(hadc);
416 }
417
418 /* Stop potential conversion on going, on regular and injected groups */
419 /* Disable ADC peripheral */
420 /* Note: In case of ADC already enabled, precaution to not launch an */
421 /* unwanted conversion while modifying register CR2 by writing 1 to */
422 /* bit ADON. */
423 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
424
425
426 /* Configuration of ADC parameters if previous preliminary actions are */
427 /* correctly completed. */
428 if (tmp_hal_status != HAL_ERROR)
429 {
430 /* Initialize the ADC state */
431 hadc->State = HAL_ADC_STATE_BUSY;
432
433 /* Set ADC parameters */
434
435 /* Configuration of ADC: */
436 /* - data alignment */
437 /* - external trigger to start conversion */
438 /* - external trigger polarity (always set to 1, because needed for all */
439 /* triggers: external trigger of SW start) */
440 /* - continuous conversion mode */
441 /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
442 /* HAL_ADC_Start_xxx functions because if set in this function, */
443 /* a conversion on injected group would start a conversion also on */
444 /* regular group after ADC enabling. */
445 tmp_cr2 |= (hadc->Init.DataAlign |
446 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
447 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
448
449 /* Configuration of ADC: */
450 /* - scan mode */
451 /* - discontinuous mode disable/enable */
452 /* - discontinuous mode number of conversions */
453 tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
454
455 /* Enable discontinuous mode only if continuous mode is disabled */
456 if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
457 (hadc->Init.ContinuousConvMode == DISABLE) )
458 {
459 /* Enable the selected ADC regular discontinuous mode */
460 /* Set the number of channels to be converted in discontinuous mode */
461 tmp_cr1 |= (ADC_CR1_DISCEN |
462 ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
463 }
464
465 /* Update ADC configuration register CR1 with previous settings */
466 MODIFY_REG(hadc->Instance->CR1,
467 ADC_CR1_SCAN |
468 ADC_CR1_DISCEN |
469 ADC_CR1_DISCNUM ,
470 tmp_cr1 );
471
472 /* Update ADC configuration register CR2 with previous settings */
473 MODIFY_REG(hadc->Instance->CR2,
474 ADC_CR2_ALIGN |
475 ADC_CR2_EXTSEL |
476 ADC_CR2_EXTTRIG |
477 ADC_CR2_CONT ,
478 tmp_cr2 );
479
480 /* Configuration of regular group sequencer: */
481 /* - if scan mode is disabled, regular channels sequence length is set to */
482 /* 0x00: 1 channel converted (channel on regular rank 1) */
483 /* Parameter "NbrOfConversion" is discarded. */
484 /* Note: Scan mode is present by hardware on this device and, if */
485 /* disabled, discards automatically nb of conversions. Anyway, nb of */
486 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
487 /* - if scan mode is enabled, regular channels sequence length is set to */
488 /* parameter "NbrOfConversion" */
489 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
490 {
491 tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
492 }
493
494 MODIFY_REG(hadc->Instance->SQR1,
495 ADC_SQR1_L ,
496 tmp_sqr1 );
497
498 /* Check back that ADC registers have effectively been configured to */
499 /* ensure of no potential problem of ADC core IP clocking. */
500 /* Check through register CR2 (excluding bits set in other functions: */
501 /* execution control bits (ADON, JSWSTART, SWSTART), injected group bits */
502 /* (JEXTTRIG and JEXTSEL), channel internal measurement path bit (TSVREFE)*/
503 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON |
504 ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
505 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
506 ADC_CR2_TSVREFE ))
507 == tmp_cr2)
508 {
509 /* Set ADC error code to none */
510 ADC_CLEAR_ERRORCODE(hadc);
511
512 /* Initialize the ADC state */
513 hadc->State = HAL_ADC_STATE_READY;
514 }
515 else
516 {
517 /* Update ADC state machine to error */
518 hadc->State = HAL_ADC_STATE_ERROR;
519
520 /* Set ADC error code to ADC IP internal error */
521 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
522
523 tmp_hal_status = HAL_ERROR;
524 }
525
526 }
527 else
528 {
529 /* Update ADC state machine to error */
530 hadc->State = HAL_ADC_STATE_ERROR;
531
532 tmp_hal_status = HAL_ERROR;
533 }
534
535 /* Return function status */
536 return tmp_hal_status;
537 }
538
539 /**
540 * @brief Deinitialize the ADC peripheral registers to their default reset
541 * values, with deinitialization of the ADC MSP.
542 * If needed, the example code can be copied and uncommented into
543 * function HAL_ADC_MspDeInit().
544 * @param hadc: ADC handle
545 * @retval HAL status
546 */
547 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
548 {
549 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
550
551 /* Check ADC handle */
552 if(hadc == NULL)
553 {
554 return HAL_ERROR;
555 }
556
557 /* Check the parameters */
558 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
559
560 /* Change ADC state */
561 hadc->State = HAL_ADC_STATE_BUSY;
562
563 /* Stop potential conversion on going, on regular and injected groups */
564 /* Disable ADC peripheral */
565 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
566
567
568 /* Configuration of ADC parameters if previous preliminary actions are */
569 /* correctly completed. */
570 if (tmp_hal_status != HAL_ERROR)
571 {
572 /* ========== Reset ADC registers ========== */
573
574
575
576
577 /* Reset register SR */
578 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
579 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
580
581 /* Reset register CR1 */
582 CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
583 ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
584 ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
585 ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
586
587 /* Reset register CR2 */
588 CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
589 ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
590 ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
591 ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
592 ADC_CR2_ADON ));
593
594 /* Reset register SMPR1 */
595 CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 |
596 ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 |
597 ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
598
599 /* Reset register SMPR2 */
600 CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
601 ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
602 ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
603 ADC_SMPR2_SMP0 ));
604
605 /* Reset register JOFR1 */
606 CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
607 /* Reset register JOFR2 */
608 CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
609 /* Reset register JOFR3 */
610 CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
611 /* Reset register JOFR4 */
612 CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
613
614 /* Reset register HTR */
615 CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
616 /* Reset register LTR */
617 CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
618
619 /* Reset register SQR1 */
620 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
621 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
622 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
623
624 /* Reset register SQR1 */
625 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
626 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
627 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
628
629 /* Reset register SQR2 */
630 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
631 ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
632
633 /* Reset register SQR3 */
634 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
635 ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
636
637 /* Reset register JSQR */
638 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
639 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
640 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
641
642 /* Reset register JSQR */
643 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
644 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
645 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
646
647 /* Reset register DR */
648 /* bits in access mode read only, no direct reset applicable*/
649
650 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
651 /* bits in access mode read only, no direct reset applicable*/
652
653 /* ========== Hard reset ADC peripheral ========== */
654 /* Performs a global reset of the entire ADC peripheral: ADC state is */
655 /* forced to a similar state after device power-on. */
656 /* If needed, copy-paste and uncomment the following reset code into */
657 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
658 /* */
659 /* __HAL_RCC_ADC1_FORCE_RESET() */
660 /* __HAL_RCC_ADC1_RELEASE_RESET() */
661
662 /* DeInit the low level hardware */
663 HAL_ADC_MspDeInit(hadc);
664
665 /* Set ADC error code to none */
666 ADC_CLEAR_ERRORCODE(hadc);
667
668 /* Change ADC state */
669 hadc->State = HAL_ADC_STATE_RESET;
670
671 }
672
673 /* Process unlocked */
674 __HAL_UNLOCK(hadc);
675
676 /* Return function status */
677 return tmp_hal_status;
678 }
679
680 /**
681 * @brief Initializes the ADC MSP.
682 * @param hadc: ADC handle
683 * @retval None
684 */
685 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
686 {
687 /* NOTE : This function should not be modified. When the callback is needed,
688 function HAL_ADC_MspInit must be implemented in the user file.
689 */
690 }
691
692 /**
693 * @brief DeInitializes the ADC MSP.
694 * @param hadc: ADC handle
695 * @retval None
696 */
697 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
698 {
699 /* NOTE : This function should not be modified. When the callback is needed,
700 function HAL_ADC_MspDeInit must be implemented in the user file.
701 */
702 }
703
704 /**
705 * @}
706 */
707
708 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
709 * @brief Input and Output operation functions
710 *
711 @verbatim
712 ===============================================================================
713 ##### IO operation functions #####
714 ===============================================================================
715 [..] This section provides functions allowing to:
716 (+) Start conversion of regular group.
717 (+) Stop conversion of regular group.
718 (+) Poll for conversion complete on regular group.
719 (+) Poll for conversion event.
720 (+) Get result of regular channel conversion.
721 (+) Start conversion of regular group and enable interruptions.
722 (+) Stop conversion of regular group and disable interruptions.
723 (+) Handle ADC interrupt request
724 (+) Start conversion of regular group and enable DMA transfer.
725 (+) Stop conversion of regular group and disable ADC DMA transfer.
726 @endverbatim
727 * @{
728 */
729
730 /**
731 * @brief Enables ADC, starts conversion of regular group.
732 * Interruptions enabled in this function: None.
733 * @param hadc: ADC handle
734 * @retval HAL status
735 */
736 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
737 {
738 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
739
740 /* Check the parameters */
741 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
742
743 /* Process locked */
744 __HAL_LOCK(hadc);
745
746 /* Enable the ADC peripheral */
747 tmp_hal_status = ADC_Enable(hadc);
748
749 /* Start conversion if ADC is effectively enabled */
750 if (tmp_hal_status != HAL_ERROR)
751 {
752 /* State machine update: Check if an injected conversion is ongoing */
753 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
754 {
755 /* Change ADC state */
756 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
757 }
758 else
759 {
760 /* Change ADC state */
761 hadc->State = HAL_ADC_STATE_BUSY_REG;
762 }
763
764 /* Process unlocked */
765 /* Unlock before starting ADC conversions: in case of potential */
766 /* interruption, to let the process to ADC IRQ Handler. */
767 __HAL_UNLOCK(hadc);
768
769 /* Set ADC error code to none */
770 ADC_CLEAR_ERRORCODE(hadc);
771
772 /* Clear regular group conversion flag and overrun flag */
773 /* (To ensure of no unknown state from potential previous ADC operations) */
774 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
775
776 /* Enable conversion of regular group. */
777 /* If software start has been selected, conversion starts immediately. */
778 /* If external trigger has been selected, conversion will start at next */
779 /* trigger event. */
780 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
781 /* slave, ADC is enabled only (conversion is not started). If ADC is */
782 /* master, ADC is enabled and conversion is started. */
783 /* Note: Alternate trigger for single conversion could be to force an */
784 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
785 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
786 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
787 {
788 /* Start ADC conversion on regular group with SW start */
789 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
790 }
791 else
792 {
793 /* Start ADC conversion on regular group with external trigger */
794 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
795 }
796 }
797 else
798 {
799 /* Process unlocked */
800 __HAL_UNLOCK(hadc);
801 }
802
803 /* Return function status */
804 return tmp_hal_status;
805 }
806
807 /**
808 * @brief Stop ADC conversion of regular group (and injected channels in
809 * case of auto_injection mode), disable ADC peripheral.
810 * @note: ADC peripheral disable is forcing stop of potential
811 * conversion on injected group. If injected group is under use, it
812 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
813 * @param hadc: ADC handle
814 * @retval HAL status.
815 */
816 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
817 {
818 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
819
820 /* Check the parameters */
821 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
822
823 /* Process locked */
824 __HAL_LOCK(hadc);
825
826 /* Stop potential conversion on going, on regular and injected groups */
827 /* Disable ADC peripheral */
828 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
829
830 /* Check if ADC is effectively disabled */
831 if (tmp_hal_status != HAL_ERROR)
832 {
833 /* Change ADC state */
834 hadc->State = HAL_ADC_STATE_READY;
835 }
836
837 /* Process unlocked */
838 __HAL_UNLOCK(hadc);
839
840 /* Return function status */
841 return tmp_hal_status;
842 }
843
844 /**
845 * @brief Wait for regular group conversion to be completed.
846 * @param hadc: ADC handle
847 * @param Timeout: Timeout value in millisecond.
848 * @retval HAL status
849 */
850 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
851 {
852 uint32_t tickstart = 0;
853
854 /* Variables for polling in case of scan mode enabled and polling for each */
855 /* conversion. */
856 __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
857 uint32_t Conversion_Timeout_CPU_cycles_max = 0;
858
859 /* Check the parameters */
860 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
861
862 /* Get timeout */
863 tickstart = HAL_GetTick();
864
865 /* Polling for end of conversion: differentiation if single/sequence */
866 /* conversion. */
867 /* - If single conversion for regular group (Scan mode disabled or enabled */
868 /* with NbrOfConversion =1), flag EOC is used to determine the */
869 /* conversion completion. */
870 /* - If sequence conversion for regular group, flag EOC is set only a the */
871 /* end of the sequence. To poll for each conversion, the maximum */
872 /* conversion time is calculated from ADC conversion time (selected */
873 /* sampling time + conversion time of 12.5 ADC clock cycles) and */
874 /* APB2/ADC clock prescalers (depending on settings, conversion time */
875 /* range can be from 28 to 32256 CPU cycles). */
876 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
877 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
878 {
879 /* Wait until End of Conversion flag is raised */
880 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
881 {
882 /* Check if timeout is disabled (set to infinite wait) */
883 if(Timeout != HAL_MAX_DELAY)
884 {
885 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
886 {
887 /* Update ADC state machine to timeout */
888 hadc->State = HAL_ADC_STATE_TIMEOUT;
889
890 /* Process unlocked */
891 __HAL_UNLOCK(hadc);
892
893 return HAL_ERROR;
894 }
895 }
896 }
897 }
898 else
899 {
900 /* Poll with maximum conversion time */
901 /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
902 /* and ADC maximum conversion cycles on all channels. */
903 /* - Wait for the expected ADC clock cycles delay */
904 Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
905 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
906 * ADC_CONVCYCLES_MAX_RANGE(hadc) );
907
908 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
909 {
910 /* Check if timeout is disabled (set to infinite wait) */
911 if(Timeout != HAL_MAX_DELAY)
912 {
913 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
914 {
915 /* Update ADC state machine to timeout */
916 hadc->State = HAL_ADC_STATE_TIMEOUT;
917
918 /* Process unlocked */
919 __HAL_UNLOCK(hadc);
920
921 return HAL_ERROR;
922 }
923 }
924 Conversion_Timeout_CPU_cycles ++;
925 }
926 }
927
928 /* Clear regular group conversion flag */
929 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
930
931 /* Update state machine on conversion status if not in error state */
932 if(hadc->State != HAL_ADC_STATE_ERROR)
933 {
934 /* Update ADC state machine */
935 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
936 {
937 /* Check if a conversion is ready on injected group */
938 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
939 {
940 /* Change ADC state */
941 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
942 }
943 else
944 {
945 /* Change ADC state */
946 hadc->State = HAL_ADC_STATE_EOC_REG;
947 }
948 }
949 }
950
951 /* Return ADC state */
952 return HAL_OK;
953 }
954
955 /**
956 * @brief Poll for conversion event.
957 * @param hadc: ADC handle
958 * @param EventType: the ADC event type.
959 * This parameter can be one of the following values:
960 * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
961 * @param Timeout: Timeout value in millisecond.
962 * @retval HAL status
963 */
964 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
965 {
966 uint32_t tickstart = 0;
967
968 /* Check the parameters */
969 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
970 assert_param(IS_ADC_EVENT_TYPE(EventType));
971
972 /* Get start tick count */
973 tickstart = HAL_GetTick();
974
975 /* Check selected event flag */
976 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
977 {
978 /* Check if timeout is disabled (set to infinite wait) */
979 if(Timeout != HAL_MAX_DELAY)
980 {
981 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
982 {
983 /* Update ADC state machine to timeout */
984 hadc->State = HAL_ADC_STATE_TIMEOUT;
985
986 /* Process unlocked */
987 __HAL_UNLOCK(hadc);
988
989 return HAL_ERROR;
990 }
991 }
992 }
993
994 /* Analog watchdog (level out of window) event */
995 /* Change ADC state */
996 hadc->State = HAL_ADC_STATE_AWD;
997
998 /* Clear ADC analog watchdog flag */
999 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1000
1001 /* Return ADC state */
1002 return HAL_OK;
1003 }
1004
1005 /**
1006 * @brief Enables ADC, starts conversion of regular group with interruption.
1007 * Interruptions enabled in this function:
1008 * - EOC (end of conversion of regular group)
1009 * Each of these interruptions has its dedicated callback function.
1010 * @param hadc: ADC handle
1011 * @retval HAL status
1012 */
1013 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1014 {
1015 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1016
1017 /* Check the parameters */
1018 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1019
1020 /* Process locked */
1021 __HAL_LOCK(hadc);
1022
1023 /* Enable the ADC peripheral */
1024 tmp_hal_status = ADC_Enable(hadc);
1025
1026 /* Start conversion if ADC is effectively enabled */
1027 if (tmp_hal_status != HAL_ERROR)
1028 {
1029 /* State machine update: Check if an injected conversion is ongoing */
1030 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
1031 {
1032 /* Change ADC state */
1033 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
1034 }
1035 else
1036 {
1037 /* Change ADC state */
1038 hadc->State = HAL_ADC_STATE_BUSY_REG;
1039 }
1040
1041 /* Process unlocked */
1042 /* Unlock before starting ADC conversions: in case of potential */
1043 /* interruption, to let the process to ADC IRQ Handler. */
1044 __HAL_UNLOCK(hadc);
1045
1046 /* Set ADC error code to none */
1047 ADC_CLEAR_ERRORCODE(hadc);
1048
1049 /* Clear regular group conversion flag and overrun flag */
1050 /* (To ensure of no unknown state from potential previous ADC operations) */
1051 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1052
1053 /* Enable end of conversion interrupt for regular group */
1054 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1055
1056 /* Enable conversion of regular group. */
1057 /* If software start has been selected, conversion starts immediately. */
1058 /* If external trigger has been selected, conversion will start at next */
1059 /* trigger event. */
1060 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
1061 /* slave, ADC is enabled only (conversion is not started). If ADC is */
1062 /* master, ADC is enabled and conversion is started. */
1063 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1064 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
1065 {
1066 /* Start ADC conversion on regular group with SW start */
1067 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
1068 }
1069 else
1070 {
1071 /* Start ADC conversion on regular group with external trigger */
1072 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
1073 }
1074 }
1075 else
1076 {
1077 /* Process unlocked */
1078 __HAL_UNLOCK(hadc);
1079 }
1080
1081 /* Return function status */
1082 return tmp_hal_status;
1083 }
1084
1085 /**
1086 * @brief Stop ADC conversion of regular group (and injected group in
1087 * case of auto_injection mode), disable interrution of
1088 * end-of-conversion, disable ADC peripheral.
1089 * @param hadc: ADC handle
1090 * @retval None
1091 */
1092 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1093 {
1094 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1095
1096 /* Check the parameters */
1097 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1098
1099 /* Process locked */
1100 __HAL_LOCK(hadc);
1101
1102 /* Stop potential conversion on going, on regular and injected groups */
1103 /* Disable ADC peripheral */
1104 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1105
1106 /* Check if ADC is effectively disabled */
1107 if (tmp_hal_status != HAL_ERROR)
1108 {
1109 /* Disable ADC end of conversion interrupt for regular group */
1110 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1111
1112 /* Change ADC state */
1113 hadc->State = HAL_ADC_STATE_READY;
1114 }
1115
1116 /* Process unlocked */
1117 __HAL_UNLOCK(hadc);
1118
1119 /* Return function status */
1120 return tmp_hal_status;
1121 }
1122
1123 /**
1124 * @brief Enables ADC, starts conversion of regular group and transfers result
1125 * through DMA.
1126 * Interruptions enabled in this function:
1127 * - DMA transfer complete
1128 * - DMA half transfer
1129 * Each of these interruptions has its dedicated callback function.
1130 * @note For devices with several ADCs: This function is for single-ADC mode
1131 * only. For multimode, use the dedicated MultimodeStart function.
1132 * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
1133 * on devices) have DMA capability.
1134 * ADC2 converted data can be transferred in dual ADC mode using DMA
1135 * of ADC1 (ADC master in multimode).
1136 * In case of using ADC1 with DMA on a device featuring 2 ADC
1137 * instances: ADC1 conversion register DR contains ADC1 conversion
1138 * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
1139 * conversion result (ADC1 register DR bits 16 to 27). Therefore, to
1140 * have DMA transferring the conversion results of ADC1 only, DMA must
1141 * be configured to transfer size: half word.
1142 * @param hadc: ADC handle
1143 * @param pData: The destination Buffer address.
1144 * @param Length: The length of data to be transferred from ADC peripheral to memory.
1145 * @retval None
1146 */
1147 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
1148 {
1149 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1150
1151 /* Check the parameters */
1152 assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
1153
1154 /* Verification if multimode is disabled (for devices with several ADC) */
1155 /* If multimode is enabled, dedicated function multimode conversion */
1156 /* start DMA must be used. */
1157 if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
1158 {
1159 /* Process locked */
1160 __HAL_LOCK(hadc);
1161
1162 /* Enable the ADC peripheral */
1163 tmp_hal_status = ADC_Enable(hadc);
1164
1165 /* Start conversion if ADC is effectively enabled */
1166 if (tmp_hal_status != HAL_ERROR)
1167 {
1168 /* State machine update: Check if an injected conversion is ongoing */
1169 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
1170 {
1171 /* Change ADC state */
1172 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
1173 }
1174 else
1175 {
1176 /* Change ADC state */
1177 hadc->State = HAL_ADC_STATE_BUSY_REG;
1178 }
1179
1180 /* Process unlocked */
1181 /* Unlock before starting ADC conversions: in case of potential */
1182 /* interruption, to let the process to ADC IRQ Handler. */
1183 __HAL_UNLOCK(hadc);
1184
1185 /* Set ADC error code to none */
1186 ADC_CLEAR_ERRORCODE(hadc);
1187
1188 /* Set the DMA transfer complete callback */
1189 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1190
1191 /* Set the DMA half transfer complete callback */
1192 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1193
1194 /* Set the DMA error callback */
1195 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1196
1197
1198 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1199 /* start (in case of SW start): */
1200
1201 /* Clear regular group conversion flag and overrun flag */
1202 /* (To ensure of no unknown state from potential previous ADC */
1203 /* operations) */
1204 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1205
1206 /* Enable ADC DMA mode */
1207 SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
1208
1209 /* Start the DMA channel */
1210 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1211
1212 /* Enable conversion of regular group. */
1213 /* If software start has been selected, conversion starts immediately. */
1214 /* If external trigger has been selected, conversion will start at next */
1215 /* trigger event. */
1216 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
1217 {
1218 /* Start ADC conversion on regular group with SW start */
1219 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
1220 }
1221 else
1222 {
1223 /* Start ADC conversion on regular group with external trigger */
1224 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
1225 }
1226 }
1227 else
1228 {
1229 /* Process unlocked */
1230 __HAL_UNLOCK(hadc);
1231 }
1232 }
1233 else
1234 {
1235 tmp_hal_status = HAL_ERROR;
1236 }
1237
1238 /* Return function status */
1239 return tmp_hal_status;
1240 }
1241
1242 /**
1243 * @brief Stop ADC conversion of regular group (and injected group in
1244 * case of auto_injection mode), disable ADC DMA transfer, disable
1245 * ADC peripheral.
1246 * @note: ADC peripheral disable is forcing stop of potential
1247 * conversion on injected group. If injected group is under use, it
1248 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1249 * @note For devices with several ADCs: This function is for single-ADC mode
1250 * only. For multimode, use the dedicated MultimodeStop function.
1251 * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
1252 * on devices) have DMA capability.
1253 * @param hadc: ADC handle
1254 * @retval HAL status.
1255 */
1256 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
1257 {
1258 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1259
1260 /* Check the parameters */
1261 assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
1262
1263 /* Process locked */
1264 __HAL_LOCK(hadc);
1265
1266 /* Stop potential conversion on going, on regular and injected groups */
1267 /* Disable ADC peripheral */
1268 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1269
1270 /* Check if ADC is effectively disabled */
1271 if (tmp_hal_status != HAL_ERROR)
1272 {
1273 /* Disable ADC DMA mode */
1274 CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
1275
1276 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1277 /* DMA transfer is on going) */
1278 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1279
1280 /* Check if DMA channel effectively disabled */
1281 if (tmp_hal_status != HAL_ERROR)
1282 {
1283 /* Change ADC state */
1284 hadc->State = HAL_ADC_STATE_READY;
1285 }
1286 else
1287 {
1288 /* Update ADC state machine to error */
1289 hadc->State = HAL_ADC_STATE_ERROR;
1290 }
1291 }
1292
1293 /* Process unlocked */
1294 __HAL_UNLOCK(hadc);
1295
1296 /* Return function status */
1297 return tmp_hal_status;
1298 }
1299
1300 /**
1301 * @brief Get ADC regular group conversion result.
1302 * @note Reading DR register automatically clears EOC (end of conversion of
1303 * regular group) flag.
1304 * @param hadc: ADC handle
1305 * @retval Converted value
1306 */
1307 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
1308 {
1309 /* Check the parameters */
1310 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1311
1312 /* Note: EOC flag is not cleared here by software because automatically */
1313 /* cleared by hardware when reading register DR. */
1314
1315 /* Return ADC converted value */
1316 return hadc->Instance->DR;
1317 }
1318
1319 /**
1320 * @brief Handles ADC interrupt request
1321 * @param hadc: ADC handle
1322 * @retval None
1323 */
1324 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
1325 {
1326 /* Check the parameters */
1327 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1328 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1329 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
1330
1331
1332 /* ========== Check End of Conversion flag for regular group ========== */
1333 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
1334 {
1335 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
1336 {
1337 /* Update state machine on conversion status if not in error state */
1338 if(hadc->State != HAL_ADC_STATE_ERROR)
1339 {
1340 /* Update ADC state machine */
1341 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
1342 {
1343 /* Check if a conversion is ready on injected group */
1344 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
1345 {
1346 /* Change ADC state */
1347 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
1348 }
1349 else
1350 {
1351 /* Change ADC state */
1352 hadc->State = HAL_ADC_STATE_EOC_REG;
1353 }
1354 }
1355 }
1356
1357 /* Disable interruption if no further conversion upcoming regular */
1358 /* external trigger or by continuous mode */
1359 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1360 (hadc->Init.ContinuousConvMode == DISABLE) )
1361 {
1362 /* Disable ADC end of single conversion interrupt */
1363 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1364 }
1365
1366 /* Conversion complete callback */
1367 HAL_ADC_ConvCpltCallback(hadc);
1368
1369 /* Clear regular group conversion flag */
1370 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1371 }
1372 }
1373
1374 /* ========== Check End of Conversion flag for injected group ========== */
1375 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
1376 {
1377 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
1378 {
1379 /* Update state machine on conversion status if not in error state */
1380 if(hadc->State != HAL_ADC_STATE_ERROR)
1381 {
1382 /* Update ADC state machine */
1383 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
1384 {
1385
1386 if(hadc->State == HAL_ADC_STATE_EOC_REG)
1387 {
1388 /* Change ADC state */
1389 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
1390 }
1391 else
1392 {
1393 /* Change ADC state */
1394 hadc->State = HAL_ADC_STATE_EOC_INJ;
1395 }
1396 }
1397 }
1398
1399 /* Disable interruption if no further conversion upcoming injected */
1400 /* external trigger or by automatic injected conversion with regular */
1401 /* group having no further conversion upcoming (same conditions as */
1402 /* regular group interruption disabling above). */
1403 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
1404 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
1405 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1406 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
1407 {
1408 /* Disable ADC end of single conversion interrupt */
1409 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1410 }
1411
1412 /* Conversion complete callback */
1413 HAL_ADCEx_InjectedConvCpltCallback(hadc);
1414
1415 /* Clear injected group conversion flag */
1416 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1417 }
1418 }
1419
1420 /* ========== Check Analog watchdog flags ========== */
1421 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
1422 {
1423 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
1424 {
1425 /* Change ADC state */
1426 hadc->State = HAL_ADC_STATE_AWD;
1427
1428 /* Level out of window callback */
1429 HAL_ADC_LevelOutOfWindowCallback(hadc);
1430
1431 /* Clear the ADCx's Analog watchdog flag */
1432 __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
1433 }
1434 }
1435
1436 }
1437
1438 /**
1439 * @brief Conversion complete callback in non blocking mode
1440 * @param hadc: ADC handle
1441 * @retval None
1442 */
1443 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
1444 {
1445 /* NOTE : This function should not be modified. When the callback is needed,
1446 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
1447 */
1448 }
1449
1450 /**
1451 * @brief Conversion DMA half-transfer callback in non blocking mode
1452 * @param hadc: ADC handle
1453 * @retval None
1454 */
1455 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
1456 {
1457 /* NOTE : This function should not be modified. When the callback is needed,
1458 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
1459 */
1460 }
1461
1462 /**
1463 * @brief Analog watchdog callback in non blocking mode.
1464 * @param hadc: ADC handle
1465 * @retval None
1466 */
1467 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1468 {
1469 /* NOTE : This function should not be modified. When the callback is needed,
1470 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
1471 */
1472 }
1473
1474 /**
1475 * @brief ADC error callback in non blocking mode
1476 * (ADC conversion with interruption or transfer by DMA)
1477 * @param hadc: ADC handle
1478 * @retval None
1479 */
1480 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1481 {
1482 /* NOTE : This function should not be modified. When the callback is needed,
1483 function HAL_ADC_ErrorCallback must be implemented in the user file.
1484 */
1485 }
1486
1487
1488 /**
1489 * @}
1490 */
1491
1492 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1493 * @brief Peripheral Control functions
1494 *
1495 @verbatim
1496 ===============================================================================
1497 ##### Peripheral Control functions #####
1498 ===============================================================================
1499 [..] This section provides functions allowing to:
1500 (+) Configure channels on regular group
1501 (+) Configure the analog watchdog
1502
1503 @endverbatim
1504 * @{
1505 */
1506
1507 /**
1508 * @brief Configures the the selected channel to be linked to the regular
1509 * group.
1510 * @note In case of usage of internal measurement channels:
1511 * Vbat/VrefInt/TempSensor.
1512 * These internal paths can be be disabled using function
1513 * HAL_ADC_DeInit().
1514 * @note Possibility to update parameters on the fly:
1515 * This function initializes channel into regular group, following
1516 * calls to this function can be used to reconfigure some parameters
1517 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
1518 * the ADC.
1519 * The setting of these parameters is conditioned to ADC state.
1520 * For parameters constraints, see comments of structure
1521 * "ADC_ChannelConfTypeDef".
1522 * @param hadc: ADC handle
1523 * @param sConfig: Structure of ADC channel for regular group.
1524 * @retval HAL status
1525 */
1526 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
1527 {
1528 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1529 __IO uint32_t wait_loop_index = 0;
1530
1531 /* Check the parameters */
1532 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1533 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1534 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1535 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1536
1537 /* Process locked */
1538 __HAL_LOCK(hadc);
1539
1540
1541 /* Regular sequence configuration */
1542 /* For Rank 1 to 6 */
1543 if (sConfig->Rank < 7)
1544 {
1545 MODIFY_REG(hadc->Instance->SQR3 ,
1546 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
1547 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
1548 }
1549 /* For Rank 7 to 12 */
1550 else if (sConfig->Rank < 13)
1551 {
1552 MODIFY_REG(hadc->Instance->SQR2 ,
1553 ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
1554 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
1555 }
1556 /* For Rank 13 to 16 */
1557 else
1558 {
1559 MODIFY_REG(hadc->Instance->SQR1 ,
1560 ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
1561 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
1562 }
1563
1564
1565 /* Channel sampling time configuration */
1566 /* For channels 10 to 17 */
1567 if (sConfig->Channel >= ADC_CHANNEL_10)
1568 {
1569 MODIFY_REG(hadc->Instance->SMPR1 ,
1570 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
1571 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
1572 }
1573 else /* For channels 0 to 9 */
1574 {
1575 MODIFY_REG(hadc->Instance->SMPR2 ,
1576 ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
1577 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
1578 }
1579
1580 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
1581 /* and VREFINT measurement path. */
1582 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
1583 (sConfig->Channel == ADC_CHANNEL_VREFINT) )
1584 {
1585 /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
1586 /* measurement channels (VrefInt/TempSensor). If these channels are */
1587 /* intended to be set on other ADC instances, an error is reported. */
1588 if (hadc->Instance == ADC1)
1589 {
1590 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
1591 {
1592 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
1593
1594 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
1595 {
1596 /* Delay for temperature sensor stabilization time */
1597 /* Compute number of CPU cycles to wait for */
1598 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
1599 while(wait_loop_index != 0)
1600 {
1601 wait_loop_index--;
1602 }
1603 }
1604 }
1605 }
1606 else
1607 {
1608 /* Update ADC state machine to error */
1609 hadc->State = HAL_ADC_STATE_ERROR;
1610
1611 tmp_hal_status = HAL_ERROR;
1612 }
1613 }
1614
1615 /* Process unlocked */
1616 __HAL_UNLOCK(hadc);
1617
1618 /* Return function status */
1619 return tmp_hal_status;
1620 }
1621
1622 /**
1623 * @brief Configures the analog watchdog.
1624 * @param hadc: ADC handle
1625 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
1626 * @retval HAL status
1627 */
1628 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
1629 {
1630 /* Check the parameters */
1631 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1632 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
1633 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1634 assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
1635 assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
1636
1637 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
1638 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
1639 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
1640 {
1641 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1642 }
1643
1644 /* Process locked */
1645 __HAL_LOCK(hadc);
1646
1647 /* Analog watchdog configuration */
1648
1649 /* Configure ADC Analog watchdog interrupt */
1650 if(AnalogWDGConfig->ITMode == ENABLE)
1651 {
1652 /* Enable the ADC Analog watchdog interrupt */
1653 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1654 }
1655 else
1656 {
1657 /* Disable the ADC Analog watchdog interrupt */
1658 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1659 }
1660
1661 /* Configuration of analog watchdog: */
1662 /* - Set the analog watchdog enable mode: regular and/or injected groups, */
1663 /* one or all channels. */
1664 /* - Set the Analog watchdog channel (is not used if watchdog */
1665 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
1666 MODIFY_REG(hadc->Instance->CR1 ,
1667 ADC_CR1_AWDSGL |
1668 ADC_CR1_JAWDEN |
1669 ADC_CR1_AWDEN |
1670 ADC_CR1_AWDCH ,
1671 AnalogWDGConfig->WatchdogMode |
1672 AnalogWDGConfig->Channel );
1673
1674 /* Set the high threshold */
1675 WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
1676
1677 /* Set the low threshold */
1678 WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
1679
1680 /* Process unlocked */
1681 __HAL_UNLOCK(hadc);
1682
1683 /* Return function status */
1684 return HAL_OK;
1685 }
1686
1687
1688 /**
1689 * @}
1690 */
1691
1692
1693 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
1694 * @brief Peripheral State functions
1695 *
1696 @verbatim
1697 ===============================================================================
1698 ##### Peripheral State and Errors functions #####
1699 ===============================================================================
1700 [..]
1701 This subsection provides functions to get in run-time the status of the
1702 peripheral.
1703 (+) Check the ADC state
1704 (+) Check the ADC error code
1705
1706 @endverbatim
1707 * @{
1708 */
1709
1710 /**
1711 * @brief return the ADC state
1712 * @param hadc: ADC handle
1713 * @retval HAL state
1714 */
1715 HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
1716 {
1717 /* Return ADC state */
1718 return hadc->State;
1719 }
1720
1721 /**
1722 * @brief Return the ADC error code
1723 * @param hadc: ADC handle
1724 * @retval ADC Error Code
1725 */
1726 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1727 {
1728 return hadc->ErrorCode;
1729 }
1730
1731 /**
1732 * @}
1733 */
1734
1735 /**
1736 * @}
1737 */
1738
1739 /** @defgroup ADC_Private_Functions ADC Private Functions
1740 * @{
1741 */
1742
1743 /**
1744 * @brief Enable the selected ADC.
1745 * @note Prerequisite condition to use this function: ADC must be disabled
1746 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
1747 * @param hadc: ADC handle
1748 * @retval HAL status.
1749 */
1750 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
1751 {
1752 uint32_t tickstart = 0;
1753 __IO uint32_t wait_loop_index = 0;
1754
1755 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
1756 /* enabling phase not yet completed: flag ADC ready not yet set). */
1757 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
1758 /* causes: ADC clock not running, ...). */
1759 if (ADC_IS_ENABLE(hadc) == RESET)
1760 {
1761 /* Enable the Peripheral */
1762 __HAL_ADC_ENABLE(hadc);
1763
1764 /* Delay for ADC stabilization time */
1765 /* Compute number of CPU cycles to wait for */
1766 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
1767 while(wait_loop_index != 0)
1768 {
1769 wait_loop_index--;
1770 }
1771
1772 /* Get timeout */
1773 tickstart = HAL_GetTick();
1774
1775 /* Wait for ADC effectively enabled */
1776 while(ADC_IS_ENABLE(hadc) == RESET)
1777 {
1778 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
1779 {
1780 /* Update ADC state machine to error */
1781 hadc->State = HAL_ADC_STATE_ERROR;
1782
1783 /* Set ADC error code to ADC IP internal error */
1784 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
1785
1786 /* Process unlocked */
1787 __HAL_UNLOCK(hadc);
1788
1789 return HAL_ERROR;
1790 }
1791 }
1792 }
1793
1794 /* Return HAL status */
1795 return HAL_OK;
1796 }
1797
1798 /**
1799 * @brief Stop ADC conversion and disable the selected ADC
1800 * @note Prerequisite condition to use this function: ADC conversions must be
1801 * stopped to disable the ADC.
1802 * @param hadc: ADC handle
1803 * @retval HAL status.
1804 */
1805 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
1806 {
1807 uint32_t tickstart = 0;
1808
1809 /* Verification if ADC is not already disabled */
1810 if (ADC_IS_ENABLE(hadc) != RESET)
1811 {
1812 /* Disable the ADC peripheral */
1813 __HAL_ADC_DISABLE(hadc);
1814
1815 /* Get timeout */
1816 tickstart = HAL_GetTick();
1817
1818 /* Wait for ADC effectively disabled */
1819 while(ADC_IS_ENABLE(hadc) != RESET)
1820 {
1821 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
1822 {
1823 /* Update ADC state machine to error */
1824 hadc->State = HAL_ADC_STATE_ERROR;
1825
1826 /* Set ADC error code to ADC IP internal error */
1827 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
1828
1829 return HAL_ERROR;
1830 }
1831 }
1832 }
1833
1834 /* Return HAL status */
1835 return HAL_OK;
1836 }
1837
1838 /**
1839 * @brief DMA transfer complete callback.
1840 * @param hdma: pointer to DMA handle.
1841 * @retval None
1842 */
1843 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1844 {
1845 /* Retrieve ADC handle corresponding to current DMA handle */
1846 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1847
1848 /* Update state machine on conversion status if not in error state */
1849 if(hadc->State != HAL_ADC_STATE_ERROR)
1850 {
1851 /* Update ADC state machine */
1852 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
1853 {
1854 /* Check if a conversion is ready on injected group */
1855 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
1856 {
1857 /* Change ADC state */
1858 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
1859 }
1860 else
1861 {
1862 /* Change ADC state */
1863 hadc->State = HAL_ADC_STATE_EOC_REG;
1864 }
1865 }
1866
1867 /* Conversion complete callback */
1868 HAL_ADC_ConvCpltCallback(hadc);
1869 }
1870 else
1871 {
1872 /* Call DMA error callback */
1873 hadc->DMA_Handle->XferErrorCallback(hdma);
1874 }
1875 }
1876
1877 /**
1878 * @brief DMA half transfer complete callback.
1879 * @param hdma: pointer to DMA handle.
1880 * @retval None
1881 */
1882 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
1883 {
1884 /* Retrieve ADC handle corresponding to current DMA handle */
1885 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1886
1887 /* Half conversion callback */
1888 HAL_ADC_ConvHalfCpltCallback(hadc);
1889 }
1890
1891 /**
1892 * @brief DMA error callback
1893 * @param hdma: pointer to DMA handle.
1894 * @retval None
1895 */
1896 void ADC_DMAError(DMA_HandleTypeDef *hdma)
1897 {
1898 /* Retrieve ADC handle corresponding to current DMA handle */
1899 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1900
1901 /* Change ADC state */
1902 hadc->State = HAL_ADC_STATE_ERROR;
1903
1904 /* Set ADC error code to DMA error */
1905 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
1906
1907 /* Error callback */
1908 HAL_ADC_ErrorCallback(hadc);
1909 }
1910
1911 /**
1912 * @}
1913 */
1914
1915 #endif /* HAL_ADC_MODULE_ENABLED */
1916 /**
1917 * @}
1918 */
1919
1920 /**
1921 * @}
1922 */
1923
1924 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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