tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_hal_nor.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    15-December-2014
   7   * @brief   Header file of NOR HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F1xx_HAL_NOR_H
  40 #define __STM32F1xx_HAL_NOR_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f1xx_ll_fsmc.h"
  48
  49 /** @addtogroup STM32F1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
  54 /** @addtogroup NOR
  55   * @{
  56   */
  57
  58 /** @addtogroup NOR_Private_Constants
  59   * @{
  60   */
  61
  62 /* NOR device IDs addresses */
  63 #define MC_ADDRESS               ((uint16_t)0x0000)
  64 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
  65 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
  66 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
  67
  68 /* NOR CFI IDs addresses */
  69 #define CFI1_ADDRESS             ((uint16_t)0x10)
  70 #define CFI2_ADDRESS             ((uint16_t)0x11)
  71 #define CFI3_ADDRESS             ((uint16_t)0x12)
  72 #define CFI4_ADDRESS             ((uint16_t)0x13)
  73
  74 /* NOR operation wait timeout */
  75 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
  76
  77 /* NOR memory data width */
  78 #define NOR_MEMORY_8B            ((uint8_t)0x0)
  79 #define NOR_MEMORY_16B           ((uint8_t)0x1)
  80
  81 /* NOR memory device read/write start address */
  82 #define NOR_MEMORY_ADRESS1       FSMC_BANK1_1
  83 #define NOR_MEMORY_ADRESS2       FSMC_BANK1_2
  84 #define NOR_MEMORY_ADRESS3       FSMC_BANK1_3
  85 #define NOR_MEMORY_ADRESS4       FSMC_BANK1_4
  86
  87 /**
  88   * @}
  89   */
  90
  91 /** @addtogroup NOR_Private_Macros
  92   * @{
  93   */
  94
  95 /**
  96   * @brief  NOR memory address shifting.
  97   * @param  __NOR_ADDRESS: NOR base address
  98   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
  99   * @param  __ADDRESS__: NOR memory address
 100   * @retval NOR shifted address value
 101   */
 102 #define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
 103             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
 104               ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
 105               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
 106
 107 /**
 108   * @brief  NOR memory write data to specified address.
 109   * @param  __ADDRESS__: NOR memory address
 110   * @param  __DATA__: Data to write
 111   * @retval None
 112   */
 113 #define __NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
 114
 115 /**
 116   * @}
 117   */
 118
 119 /* Exported typedef ----------------------------------------------------------*/
 120 /** @defgroup NOR_Exported_Types NOR Exported Types
 121   * @{
 122   */
 123
 124 /**
 125   * @brief  HAL SRAM State structures definition
 126   */
 127 typedef enum
 128 {
 129   HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
 130   HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
 131   HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
 132   HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
 133   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
 134 }HAL_NOR_StateTypeDef;
 135
 136 /**
 137   * @brief  FSMC NOR Status typedef
 138   */
 139 typedef enum
 140 {
 141   HAL_NOR_STATUS_SUCCESS = 0,
 142   HAL_NOR_STATUS_ONGOING,
 143   HAL_NOR_STATUS_ERROR,
 144   HAL_NOR_STATUS_TIMEOUT
 145 }HAL_NOR_StatusTypeDef;
 146
 147 /**
 148   * @brief  FSMC NOR ID typedef
 149   */
 150 typedef struct
 151 {
 152   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
 153
 154   uint16_t Device_Code1;
 155
 156   uint16_t Device_Code2;
 157
 158   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
 159                                     These codes can be accessed by performing read operations with specific
 160                                     control signals and addresses set.They can also be accessed by issuing
 161                                     an Auto Select command                                                   */
 162 }NOR_IDTypeDef;
 163
 164 /**
 165   * @brief  FSMC NOR CFI typedef
 166   */
 167 typedef struct
 168 {
 169   /*!< Defines the information stored in the memory's Common flash interface
 170        which contains a description of various electrical and timing parameters,
 171        density information and functions supported by the memory                   */
 172
 173   uint16_t CFI_1;
 174
 175   uint16_t CFI_2;
 176
 177   uint16_t CFI_3;
 178
 179   uint16_t CFI_4;
 180 }NOR_CFITypeDef;
 181
 182 /**
 183   * @brief  NOR handle Structure definition
 184   */
 185 typedef struct
 186 {
 187   FSMC_NORSRAM_TypeDef          *Instance;    /*!< Register base address                        */
 188
 189   FSMC_NORSRAM_EXTENDED_TypeDef *Extended;    /*!< Extended mode register base address          */
 190
 191   FSMC_NORSRAM_InitTypeDef      Init;         /*!< NOR device control configuration parameters  */
 192
 193   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
 194
 195   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
 196
 197 }NOR_HandleTypeDef;
 198
 199 /**
 200   * @}
 201   */
 202
 203 /* Exported constants --------------------------------------------------------*/
 204 /* Exported macro ------------------------------------------------------------*/
 205
 206 /** @defgroup NOR_Exported_macro NOR Exported Macros
 207   * @{
 208   */
 209
 210 /** @brief Reset NOR handle state
 211   * @param  __HANDLE__: NOR handle
 212   * @retval None
 213   */
 214 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
 215
 216 /**
 217   * @}
 218   */
 219
 220 /* Exported functions --------------------------------------------------------*/
 221 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
 222  *  @{
 223  */
 224
 225 /** @addtogroup NOR_Exported_Functions_Group1
 226  *  @{
 227  */
 228
 229 /* Initialization/de-initialization functions  **********************************/
 230 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 231 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
 232 void              HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
 233 void              HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
 234 void              HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
 235
 236 /**
 237   * @}
 238   */
 239
 240 /** @addtogroup NOR_Exported_Functions_Group2
 241  *  @{
 242  */
 243
 244 /* I/O operation functions  ***************************************************/
 245 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
 246 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
 247 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 248 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 249
 250 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 251 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 252
 253 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
 254 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
 255 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
 256
 257 /**
 258   * @}
 259   */
 260
 261 /** @addtogroup NOR_Exported_Functions_Group3
 262  *  @{
 263  */
 264
 265 /* NOR Control functions  *****************************************************/
 266 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
 267 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
 268
 269 /**
 270   * @}
 271   */
 272
 273 /** @addtogroup NOR_Exported_Functions_Group4
 274  *  @{
 275  */
 276
 277 /* NOR State functions ********************************************************/
 278 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
 279 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
 280
 281 /**
 282   * @}
 283   */
 284
 285 /**
 286   * @}
 287   */
 288
 289
 290 /**
 291   * @}
 292   */
 293
 294 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
 295
 296 /**
 297   * @}
 298   */
 299
 300 #ifdef __cplusplus
 301 }
 302 #endif
 303
 304 #endif /* __STM32F1xx_HAL_NOR_H */
 305
 306 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/