tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_hal_rcc.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    15-December-2014
   7   * @brief   Header file of RCC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F1xx_HAL_RCC_H
  40 #define __STM32F1xx_HAL_RCC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f1xx_hal_def.h"
  48
  49 /** @addtogroup STM32F1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup RCC
  54   * @{
  55   */
  56
  57 /** @addtogroup RCC_Private_Constants
  58   * @{
  59   */
  60
  61 #define RCC_DBP_TIMEOUT_VALUE          ((uint32_t)100)
  62 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
  63 #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
  64 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
  65 #define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
  66 #define LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
  67 #define PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
  68 #define LSI_VALUE                  ((uint32_t)40000)  /* 40kHz */
  69
  70 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
  71   * @brief RCC registers bit address in the alias region
  72   * @{
  73   */
  74 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
  75 #define RCC_CR_OFFSET             0x00
  76 #define RCC_CFGR_OFFSET           0x04
  77 #define RCC_CIR_OFFSET            0x08
  78 #define RCC_BDCR_OFFSET           0x20
  79 #define RCC_CSR_OFFSET            0x24
  80 #define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
  81 #define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
  82 #define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
  83 #define RCC_BDCR_OFFSET_BB        (RCC_OFFSET + RCC_BDCR_OFFSET)
  84 #define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
  85
  86 /* --- CR Register ---*/
  87 /* Alias word address of HSION bit */
  88 #define HSION_BITNUMBER           POSITION_VAL(RCC_CR_HSION)
  89 #define RCC_CR_HSION_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
  90 /* Alias word address of HSEON bit */
  91 #define HSEON_BITNUMBER           POSITION_VAL(RCC_CR_HSEON)
  92 #define CR_HSEON_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
  93 /* Alias word address of CSSON bit */
  94 #define CSSON_BITNUMBER           POSITION_VAL(RCC_CR_CSSON)
  95 #define RCC_CR_CSSON_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
  96 /* Alias word address of PLLON bit */
  97 #define PLLON_BITNUMBER           POSITION_VAL(RCC_CR_PLLON)
  98 #define RCC_CR_PLLON_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
  99
 100 /* --- CSR Register ---*/
 101 /* Alias word address of LSION bit */
 102 #define LSION_BITNUMBER           POSITION_VAL(RCC_CSR_LSION)
 103 #define RCC_CSR_LSION_BB              ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
 104
 105 /* --- BDCR Register ---*/
 106 /* Alias word address of LSEON bit */
 107 #define LSEON_BITNUMBER           POSITION_VAL(RCC_BDCR_LSEON)
 108 #define BDCR_LSEON_BB              ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
 109
 110 /* Alias word address of LSEON bit */
 111 #define LSEBYP_BITNUMBER          POSITION_VAL(RCC_BDCR_LSEBYP)
 112 #define BDCR_LSEBYP_BB             ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
 113
 114 /* Alias word address of RTCEN bit */
 115 #define RTCEN_BITNUMBER           POSITION_VAL(RCC_BDCR_RTCEN)
 116 #define RCC_BDCR_RTCEN_BB              ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
 117
 118 /* Alias word address of BDRST bit */
 119 #define BDRST_BITNUMBER          POSITION_VAL(RCC_BDCR_BDRST)
 120 #define RCC_BDCR_BDRST_BB             ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (BDRST_BITNUMBER * 4)))
 121
 122 /* CR register byte 2 (Bits[23:16]) base address */
 123 #define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
 124
 125 /* CIR register byte 1 (Bits[15:8]) base address */
 126 #define RCC_CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
 127
 128 /* CIR register byte 2 (Bits[23:16]) base address */
 129 #define RCC_CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
 130
 131 /* Defines used for Flags */
 132 #define CR_REG_INDEX              ((uint8_t)1)
 133 #define BDCR_REG_INDEX            ((uint8_t)2)
 134 #define CSR_REG_INDEX             ((uint8_t)3)
 135
 136 #define RCC_FLAG_MASK             ((uint8_t)0x1F)
 137
 138 /**
 139   * @}
 140   */
 141
 142 /** @addtogroup RCC_Private_Macros
 143   * @{
 144   */
 145
 146 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
 147   * @{
 148   */
 149 #define __HAL_RCC_SYSCFG_CLK_DISABLE    __HAL_RCC_AFIO_CLK_DISABLE
 150 #define __HAL_RCC_SYSCFG_CLK_ENABLE     __HAL_RCC_AFIO_CLK_ENABLE
 151 #define __HAL_RCC_SYSCFG_FORCE_RESET    __HAL_RCC_AFIO_FORCE_RESET
 152 #define __HAL_RCC_SYSCFG_RELEASE_RESET  __HAL_RCC_AFIO_RELEASE_RESET
 153 /**
 154   * @}
 155   */
 156
 157 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
 158
 159 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
 160
 161 #define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
 162
 163 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
 164                              ((__HSE__) == RCC_HSE_BYPASS))
 165
 166 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
 167                              ((__LSE__) == RCC_LSE_BYPASS))
 168
 169 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
 170                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
 171
 172 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
 173                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
 174                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
 175                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
 176                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
 177
 178 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
 179
 180 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
 181                              ((__PLL__) == RCC_PLL_ON))
 182
 183 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
 184                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
 185                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
 186
 187 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
 188                                ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
 189                                ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
 190                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
 191                                ((__HCLK__) == RCC_SYSCLK_DIV512))
 192
 193 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
 194                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
 195                                ((__PCLK__) == RCC_HCLK_DIV16))
 196
 197 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
 198
 199 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
 200
 201 /**
 202   * @}
 203   */
 204
 205 /* Exported types ------------------------------------------------------------*/
 206
 207 /** @defgroup RCC_Exported_Types RCC Exported Types
 208   * @{
 209   */
 210
 211 /**
 212   * @brief  RCC PLL configuration structure definition
 213   */
 214 typedef struct
 215 {
 216   uint32_t PLLState;     /*!< The new state of the PLL.
 217                               This parameter can be a value of @ref __HAL_RCC_PLL_CONFIG */
 218
 219   uint32_t PLLSource;    /*!< PLLSource: PLL entry clock source.
 220                               This parameter must be a value of @ref RCC_PLL_Clock_Source */
 221
 222   uint32_t PLLMUL;         /*!< PLLMUL: Multiplication factor for PLL VCO input clock
 223                               This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
 224 } RCC_PLLInitTypeDef;
 225
 226 /**
 227   * @brief  RCC System, AHB and APB busses clock configuration structure definition
 228   */
 229 typedef struct
 230 {
 231   uint32_t ClockType;             /*!< The clock to be configured.
 232                                        This parameter can be a value of @ref RCC_System_Clock_Type */
 233
 234   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
 235                                        This parameter can be a value of @ref RCC_System_Clock_Source */
 236
 237   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
 238                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
 239
 240   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
 241                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
 242
 243   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
 244                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
 245
 246 } RCC_ClkInitTypeDef;
 247
 248 /**
 249   * @}
 250   */
 251
 252 /**
 253   * @}
 254   */
 255
 256 /* Exported constants --------------------------------------------------------*/
 257 /** @defgroup RCC_Exported_Constants RCC Exported Constants
 258   * @{
 259   */
 260
 261 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
 262   * @{
 263   */
 264
 265 #define RCC_PLLSOURCE_HSI_DIV2      ((uint32_t)0x00000000)  /*!< HSI clock divided by 2 selected as PLL entry clock source */
 266 #define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC         /*!< HSE clock selected as PLL entry clock source */
 267
 268 /**
 269   * @}
 270   */
 271
 272 /** @defgroup RCC_Oscillator_Type Oscillator Type
 273   * @{
 274   */
 275 #define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
 276 #define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
 277 #define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
 278 #define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
 279 #define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
 280
 281 /**
 282   * @}
 283   */
 284
 285 /** @defgroup __HAL_RCC_HSE_CONFIG HSE Config
 286   * @{
 287   */
 288 #define RCC_HSE_OFF                      ((uint32_t)0x00000000) /*!< HSE clock deactivation */
 289 #define RCC_HSE_ON                       ((uint32_t)0x00000001) /*!< HSE clock activation */
 290 #define RCC_HSE_BYPASS                   ((uint32_t)0x00000005) /*!< External clock source for HSE clock */
 291
 292 /**
 293   * @}
 294   */
 295
 296 /** @defgroup __HAL_RCC_LSE_CONFIG LSE Config
 297   * @{
 298   */
 299 #define RCC_LSE_OFF                      ((uint32_t)0x00000000) /*!< LSE clock deactivation */
 300 #define RCC_LSE_ON                       ((uint32_t)0x00000001) /*!< LSE clock activation */
 301 #define RCC_LSE_BYPASS                   ((uint32_t)0x00000005) /*!< External clock source for LSE clock */
 302
 303 /**
 304   * @}
 305   */
 306
 307 /** @defgroup RCC_HSI_Config HSI Config
 308   * @{
 309   */
 310 #define RCC_HSI_OFF                      ((uint32_t)0x00000000)   /*!< HSI clock deactivation */
 311 #define RCC_HSI_ON                       RCC_CR_HSION             /*!< HSI clock activation */
 312
 313 #define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)         /* Default HSI calibration trimming value */
 314
 315 /**
 316   * @}
 317   */
 318
 319 /** @defgroup RCC_LSI_Config LSI Config
 320   * @{
 321   */
 322 #define RCC_LSI_OFF                      ((uint32_t)0x00000000)   /*!< LSI clock deactivation */
 323 #define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
 324
 325 /**
 326   * @}
 327   */
 328
 329 /** @defgroup __HAL_RCC_PLL_CONFIG PLL Config
 330   * @{
 331   */
 332 #define RCC_PLL_NONE                      ((uint32_t)0x00000000)  /*!< PLL is not configured */
 333 #define RCC_PLL_OFF                       ((uint32_t)0x00000001)  /*!< PLL deactivation */
 334 #define RCC_PLL_ON                        ((uint32_t)0x00000002)  /*!< PLL activation */
 335
 336 /**
 337   * @}
 338   */
 339
 340 /** @defgroup RCC_System_Clock_Type System Clock Type
 341   * @{
 342   */
 343 #define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001) /*!< SYSCLK to configure */
 344 #define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002) /*!< HCLK to configure */
 345 #define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004) /*!< PCLK1 to configure */
 346 #define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008) /*!< PCLK2 to configure */
 347
 348 /**
 349   * @}
 350   */
 351
 352 /** @defgroup RCC_System_Clock_Source System Clock Source
 353   * @{
 354   */
 355 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI      /*!< HSI selected as system clock */
 356 #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE      /*!< HSE selected as system clock */
 357 #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL      /*!< PLL selected as system clock */
 358
 359 /**
 360   * @}
 361   */
 362
 363 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
 364   * @{
 365   */
 366 #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI
 367 #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE
 368 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL
 369
 370 /**
 371   * @}
 372   */
 373
 374 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
 375   * @{
 376   */
 377 #define RCC_SYSCLK_DIV1                  (RCC_CFGR_HPRE_DIV1)   /*!< SYSCLK not divided */
 378 #define RCC_SYSCLK_DIV2                  (RCC_CFGR_HPRE_DIV2)   /*!< SYSCLK divided by 2 */
 379 #define RCC_SYSCLK_DIV4                  (RCC_CFGR_HPRE_DIV4)   /*!< SYSCLK divided by 4 */
 380 #define RCC_SYSCLK_DIV8                  (RCC_CFGR_HPRE_DIV8)   /*!< SYSCLK divided by 8 */
 381 #define RCC_SYSCLK_DIV16                 (RCC_CFGR_HPRE_DIV16)  /*!< SYSCLK divided by 16 */
 382 #define RCC_SYSCLK_DIV64                 (RCC_CFGR_HPRE_DIV64)  /*!< SYSCLK divided by 64 */
 383 #define RCC_SYSCLK_DIV128                (RCC_CFGR_HPRE_DIV128) /*!< SYSCLK divided by 128 */
 384 #define RCC_SYSCLK_DIV256                (RCC_CFGR_HPRE_DIV256) /*!< SYSCLK divided by 256 */
 385 #define RCC_SYSCLK_DIV512                (RCC_CFGR_HPRE_DIV512) /*!< SYSCLK divided by 512 */
 386
 387 /**
 388   * @}
 389   */
 390
 391 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
 392   * @{
 393   */
 394 #define RCC_HCLK_DIV1                    (RCC_CFGR_PPRE1_DIV1)  /*!< HCLK not divided */
 395 #define RCC_HCLK_DIV2                    (RCC_CFGR_PPRE1_DIV2)  /*!< HCLK divided by 2 */
 396 #define RCC_HCLK_DIV4                    (RCC_CFGR_PPRE1_DIV4)  /*!< HCLK divided by 4 */
 397 #define RCC_HCLK_DIV8                    (RCC_CFGR_PPRE1_DIV8)  /*!< HCLK divided by 8 */
 398 #define RCC_HCLK_DIV16                   (RCC_CFGR_PPRE1_DIV16) /*!< HCLK divided by 16 */
 399
 400 /**
 401   * @}
 402   */
 403
 404 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
 405   * @{
 406   */
 407 #define RCC_RTCCLKSOURCE_LSE             (RCC_BDCR_RTCSEL_LSE)  /*!< LSE oscillator clock used as RTC clock */
 408 #define RCC_RTCCLKSOURCE_LSI             (RCC_BDCR_RTCSEL_LSI)  /*!< LSI oscillator clock used as RTC clock */
 409 #define RCC_RTCCLKSOURCE_HSE_DIV128      (RCC_BDCR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 128 used as RTC clock */
 410 /**
 411   * @}
 412   */
 413
 414 /** @defgroup RCC_MCO_Index MCO Index
 415   * @{
 416   */
 417 #define RCC_MCO1                         ((uint32_t)0x00000000)
 418 #define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
 419
 420 /**
 421   * @}
 422   */
 423
 424 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
 425   * @{
 426   */
 427 #define RCC_MCODIV_1                    ((uint32_t)0x00000000)
 428
 429 /**
 430   * @}
 431   */
 432
 433 /** @defgroup RCC_Interrupt Interrupts
 434   * @{
 435   */
 436 #define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
 437 #define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
 438 #define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
 439 #define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
 440 #define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
 441 #define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)    /*!< Clock Security System Interrupt flag */
 442 /**
 443   * @}
 444   */
 445
 446 /** @defgroup RCC_Flag Flags
 447   *        Elements values convention: 0XXYYYYYb
 448   *           - YYYYY  : Flag position in the register
 449   *           - XX  : Register index
 450   *                 - 01: CR register
 451   *                 - 10: BDCR register
 452   *                 - 11: CSR register
 453   * @{
 454   */
 455 /* Flags in the CR register */
 456 #define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
 457 #define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
 458 #define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
 459
 460 /* Flags in the BDCR register */
 461 #define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
 462
 463 /* Flags in the CSR register */
 464 #define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
 465 #define RCC_FLAG_RMV                     ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_RMVF)))     /*!< Remove reset flag */
 466 #define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
 467 #define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
 468 #define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
 469 #define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
 470 #define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
 471 #define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
 472
 473 /**
 474   * @}
 475   */
 476
 477 /**
 478   * @}
 479   */
 480
 481 /* Exported macro ------------------------------------------------------------*/
 482
 483 /** @defgroup RCC_Exported_Macros RCC Exported Macros
 484   * @{
 485   */
 486
 487 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
 488   * @brief  Enable or disable the AHB1 peripheral clock.
 489   * @note   After reset, the peripheral clock (used for registers read/write access)
 490   *         is disabled and the application software has to enable this clock before
 491   *         using it.
 492   * @{
 493   */
 494 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
 495                                         __IO uint32_t tmpreg; \
 496                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
 497                                         /* Delay after an RCC peripheral clock enabling */ \
 498                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
 499                                         UNUSED(tmpreg); \
 500                                       } while(0)
 501
 502 #define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
 503                                         __IO uint32_t tmpreg; \
 504                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
 505                                         /* Delay after an RCC peripheral clock enabling */ \
 506                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
 507                                         UNUSED(tmpreg); \
 508                                       } while(0)
 509
 510 #define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
 511                                         __IO uint32_t tmpreg; \
 512                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
 513                                         /* Delay after an RCC peripheral clock enabling */ \
 514                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
 515                                         UNUSED(tmpreg); \
 516                                       } while(0)
 517
 518 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
 519                                         __IO uint32_t tmpreg; \
 520                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
 521                                         /* Delay after an RCC peripheral clock enabling */ \
 522                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
 523                                         UNUSED(tmpreg); \
 524                                       } while(0)
 525
 526 #define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
 527 #define __HAL_RCC_SRAM_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
 528 #define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
 529 #define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
 530
 531 /**
 532   * @}
 533   */
 534
 535 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
 536   * @brief  Get the enable or disable status of the AHB peripheral clock.
 537   * @note   After reset, the peripheral clock (used for registers read/write access)
 538   *         is disabled and the application software has to enable this clock before
 539   *         using it.
 540   * @{
 541   */
 542
 543 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
 544 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
 545 #define __HAL_RCC_SRAM_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
 546 #define __HAL_RCC_SRAM_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
 547 #define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
 548 #define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
 549 #define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
 550 #define __HAL_RCC_CRC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
 551
 552 /**
 553   * @}
 554   */
 555
 556 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
 557   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
 558   * @note   After reset, the peripheral clock (used for registers read/write access)
 559   *         is disabled and the application software has to enable this clock before
 560   *         using it.
 561   * @{
 562   */
 563 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
 564                                         __IO uint32_t tmpreg; \
 565                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
 566                                         /* Delay after an RCC peripheral clock enabling */ \
 567                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
 568                                         UNUSED(tmpreg); \
 569                                       } while(0)
 570
 571 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
 572                                         __IO uint32_t tmpreg; \
 573                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
 574                                         /* Delay after an RCC peripheral clock enabling */ \
 575                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
 576                                         UNUSED(tmpreg); \
 577                                       } while(0)
 578
 579 #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
 580                                         __IO uint32_t tmpreg; \
 581                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
 582                                         /* Delay after an RCC peripheral clock enabling */ \
 583                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
 584                                         UNUSED(tmpreg); \
 585                                       } while(0)
 586
 587 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
 588                                         __IO uint32_t tmpreg; \
 589                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
 590                                         /* Delay after an RCC peripheral clock enabling */ \
 591                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
 592                                         UNUSED(tmpreg); \
 593                                       } while(0)
 594
 595 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
 596                                         __IO uint32_t tmpreg; \
 597                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
 598                                         /* Delay after an RCC peripheral clock enabling */ \
 599                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
 600                                         UNUSED(tmpreg); \
 601                                       } while(0)
 602
 603 #define __HAL_RCC_BKP_CLK_ENABLE()   do { \
 604                                         __IO uint32_t tmpreg; \
 605                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
 606                                         /* Delay after an RCC peripheral clock enabling */ \
 607                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
 608                                         UNUSED(tmpreg); \
 609                                       } while(0)
 610
 611 #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
 612                                         __IO uint32_t tmpreg; \
 613                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
 614                                         /* Delay after an RCC peripheral clock enabling */ \
 615                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
 616                                         UNUSED(tmpreg); \
 617                                       } while(0)
 618
 619 #define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 620 #define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 621 #define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 622 #define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 623 #define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 624
 625 #define __HAL_RCC_BKP_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
 626 #define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 627
 628 /**
 629   * @}
 630   */
 631
 632 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
 633   * @brief  Get the enable or disable status of the APB1 peripheral clock.
 634   * @note   After reset, the peripheral clock (used for registers read/write access)
 635   *         is disabled and the application software has to enable this clock before
 636   *         using it.
 637   * @{
 638   */
 639
 640 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
 641 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
 642 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
 643 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
 644 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
 645 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
 646 #define __HAL_RCC_USART2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
 647 #define __HAL_RCC_USART2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
 648 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
 649 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
 650 #define __HAL_RCC_BKP_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
 651 #define __HAL_RCC_BKP_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
 652 #define __HAL_RCC_PWR_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
 653 #define __HAL_RCC_PWR_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
 654
 655 /**
 656   * @}
 657   */
 658
 659 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
 660   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 661   * @note   After reset, the peripheral clock (used for registers read/write access)
 662   *         is disabled and the application software has to enable this clock before
 663   *         using it.
 664   * @{
 665   */
 666 #define __HAL_RCC_AFIO_CLK_ENABLE()   do { \
 667                                         __IO uint32_t tmpreg; \
 668                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
 669                                         /* Delay after an RCC peripheral clock enabling */ \
 670                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
 671                                         UNUSED(tmpreg); \
 672                                       } while(0)
 673
 674 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
 675                                         __IO uint32_t tmpreg; \
 676                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
 677                                         /* Delay after an RCC peripheral clock enabling */ \
 678                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
 679                                         UNUSED(tmpreg); \
 680                                       } while(0)
 681
 682 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
 683                                         __IO uint32_t tmpreg; \
 684                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
 685                                         /* Delay after an RCC peripheral clock enabling */ \
 686                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
 687                                         UNUSED(tmpreg); \
 688                                       } while(0)
 689
 690 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
 691                                         __IO uint32_t tmpreg; \
 692                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
 693                                         /* Delay after an RCC peripheral clock enabling */ \
 694                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
 695                                         UNUSED(tmpreg); \
 696                                       } while(0)
 697
 698 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
 699                                         __IO uint32_t tmpreg; \
 700                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
 701                                         /* Delay after an RCC peripheral clock enabling */ \
 702                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
 703                                         UNUSED(tmpreg); \
 704                                       } while(0)
 705
 706 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
 707                                         __IO uint32_t tmpreg; \
 708                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
 709                                         /* Delay after an RCC peripheral clock enabling */ \
 710                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
 711                                         UNUSED(tmpreg); \
 712                                       } while(0)
 713
 714 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
 715                                         __IO uint32_t tmpreg; \
 716                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
 717                                         /* Delay after an RCC peripheral clock enabling */ \
 718                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
 719                                         UNUSED(tmpreg); \
 720                                       } while(0)
 721
 722 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
 723                                         __IO uint32_t tmpreg; \
 724                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
 725                                         /* Delay after an RCC peripheral clock enabling */ \
 726                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
 727                                         UNUSED(tmpreg); \
 728                                       } while(0)
 729
 730 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
 731                                         __IO uint32_t tmpreg; \
 732                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
 733                                         /* Delay after an RCC peripheral clock enabling */ \
 734                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
 735                                         UNUSED(tmpreg); \
 736                                       } while(0)
 737
 738 #define __HAL_RCC_AFIO_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
 739 #define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
 740 #define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
 741 #define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
 742 #define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
 743 #define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 744
 745 #define __HAL_RCC_TIM1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 746 #define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 747 #define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 748
 749 /**
 750   * @}
 751   */
 752
 753 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
 754   * @brief  Get the enable or disable status of the APB2 peripheral clock.
 755   * @note   After reset, the peripheral clock (used for registers read/write access)
 756   *         is disabled and the application software has to enable this clock before
 757   *         using it.
 758   * @{
 759   */
 760
 761 #define __HAL_RCC_AFIO_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
 762 #define __HAL_RCC_AFIO_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
 763 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
 764 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
 765 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
 766 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
 767 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
 768 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
 769 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
 770 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
 771 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
 772 #define __HAL_RCC_ADC1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
 773 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
 774 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
 775 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
 776 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
 777 #define __HAL_RCC_USART1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
 778 #define __HAL_RCC_USART1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
 779
 780 /**
 781   * @}
 782   */
 783
 784 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
 785   * @brief  Force or release APB1 peripheral reset.
 786   * @{
 787   */
 788 #define __HAL_RCC_APB1_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFF)
 789 #define __HAL_RCC_TIM2_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
 790 #define __HAL_RCC_TIM3_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
 791 #define __HAL_RCC_WWDG_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
 792 #define __HAL_RCC_USART2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
 793 #define __HAL_RCC_I2C1_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
 794
 795 #define __HAL_RCC_BKP_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
 796 #define __HAL_RCC_PWR_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
 797
 798 #define __HAL_RCC_APB1_RELEASE_RESET()      (RCC->APB1RSTR = 0x00)
 799 #define __HAL_RCC_TIM2_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
 800 #define __HAL_RCC_TIM3_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
 801 #define __HAL_RCC_WWDG_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
 802 #define __HAL_RCC_USART2_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
 803 #define __HAL_RCC_I2C1_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
 804
 805 #define __HAL_RCC_BKP_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
 806 #define __HAL_RCC_PWR_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
 807
 808 /**
 809   * @}
 810   */
 811
 812 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
 813   * @brief  Force or release APB2 peripheral reset.
 814   * @{
 815   */
 816 #define __HAL_RCC_APB2_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFF)
 817 #define __HAL_RCC_AFIO_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
 818 #define __HAL_RCC_GPIOA_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
 819 #define __HAL_RCC_GPIOB_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
 820 #define __HAL_RCC_GPIOC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
 821 #define __HAL_RCC_GPIOD_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
 822 #define __HAL_RCC_ADC1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
 823
 824 #define __HAL_RCC_TIM1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
 825 #define __HAL_RCC_SPI1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
 826 #define __HAL_RCC_USART1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
 827
 828 #define __HAL_RCC_APB2_RELEASE_RESET()      (RCC->APB2RSTR = 0x00)
 829 #define __HAL_RCC_AFIO_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
 830 #define __HAL_RCC_GPIOA_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
 831 #define __HAL_RCC_GPIOB_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
 832 #define __HAL_RCC_GPIOC_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
 833 #define __HAL_RCC_GPIOD_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
 834 #define __HAL_RCC_ADC1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
 835
 836 #define __HAL_RCC_TIM1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
 837 #define __HAL_RCC_SPI1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
 838 #define __HAL_RCC_USART1_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
 839
 840 /**
 841   * @}
 842   */
 843
 844 /** @defgroup RCC_HSI_Configuration HSI Configuration
 845   * @{
 846   */
 847
 848 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
 849   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
 850   * @note   HSI can not be stopped if it is used as system clock source. In this case,
 851   *         you have to select another source of the system clock then stop the HSI.
 852   * @note   After enabling the HSI, the application software should wait on HSIRDY
 853   *         flag to be set indicating that HSI clock is stable and can be used as
 854   *         system clock source.
 855   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
 856   *         clock cycles.
 857   */
 858 #define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
 859 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
 860
 861 /** @brief  macro to adjust the Internal High Speed oscillator (HSI) calibration value.
 862   * @note   The calibration is used to compensate for the variations in voltage
 863   *         and temperature that influence the frequency of the internal HSI RC.
 864   * @param  _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
 865   *         (default is RCC_HSICALIBRATION_DEFAULT).
 866   *         This parameter must be a number between 0 and 0x1F.
 867   */
 868 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
 869           (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
 870
 871 /**
 872   * @}
 873   */
 874
 875 /** @defgroup RCC_LSI_Configuration  LSI Configuration
 876   * @{
 877   */
 878
 879 /** @brief Macros to enable or disable  the Internal Low Speed oscillator (LSI).
 880   * @note   After enabling the LSI, the application software should wait on
 881   *         LSIRDY flag to be set indicating that LSI clock is stable and can
 882   *         be used to clock the IWDG and/or the RTC.
 883   * @note   LSI can not be disabled if the IWDG is running.
 884   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
 885   *         clock cycles.
 886   */
 887 #define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
 888 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
 889
 890 /**
 891   * @}
 892   */
 893
 894 /** @defgroup RCC_HSE_Configuration HSE Configuration
 895   * @{
 896   */
 897
 898 /**
 899   * @brief  Macro to configure the External High Speed oscillator (HSE).
 900   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
 901   *         software should wait on HSERDY flag to be set indicating that HSE clock
 902   *         is stable and can be used to clock the PLL and/or system clock.
 903   * @note   HSE state can not be changed if it is used directly or through the
 904   *         PLL as system clock. In this case, you have to select another source
 905   *         of the system clock then change the HSE state (ex. disable it).
 906   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
 907   * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
 908   *         was previously enabled you have to enable it again after calling this
 909   *         function.
 910   * @param  __STATE__: specifies the new state of the HSE.
 911   *          This parameter can be one of the following values:
 912   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
 913   *                              6 HSE oscillator clock cycles.
 914   *            @arg RCC_HSE_ON: turn ON the HSE oscillator
 915   *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
 916   */
 917 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
 918                     do {                                                    \
 919                       CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                     \
 920                       if((__STATE__) == RCC_HSE_ON)                         \
 921                       {                                                     \
 922                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
 923                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
 924                       }                                                     \
 925                       else if((__STATE__) == RCC_HSE_BYPASS)                \
 926                       {                                                     \
 927                         (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__)); \
 928                       }                                                     \
 929                       else                                                  \
 930                       {                                                     \
 931                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
 932                       }                                                     \
 933                     } while(0)
 934
 935 /**
 936   * @}
 937   */
 938
 939 /** @defgroup RCC_LSE_Configuration LSE Configuration
 940   * @{
 941   */
 942
 943 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
 944   */
 945 #define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
 946                                        do{ \
 947                                          if ((__LSE_STATE__) == RCC_LSE_OFF) \
 948                                          { \
 949                                            *(__IO uint32_t *) BDCR_LSEON_BB = DISABLE; \
 950                                            *(__IO uint32_t *) BDCR_LSEBYP_BB = DISABLE; \
 951                                          } \
 952                                          else if ((__LSE_STATE__) == RCC_LSE_ON) \
 953                                          { \
 954                                            *(__IO uint32_t *) BDCR_LSEBYP_BB = DISABLE; \
 955                                            *(__IO uint32_t *) BDCR_LSEON_BB = ENABLE; \
 956                                          } \
 957                                          else \
 958                                          { \
 959                                            *(__IO uint32_t *) BDCR_LSEON_BB = DISABLE; \
 960                                            *(__IO uint32_t *) BDCR_LSEBYP_BB = ENABLE; \
 961                                          } \
 962                                        }while(0)
 963
 964
 965 /**
 966   * @}
 967   */
 968
 969 /** @defgroup RCC_PLL_Configuration PLL Configuration
 970   * @{
 971   */
 972
 973 /** @brief Macros to enable the main PLL.
 974   * @note   After enabling the main PLL, the application software should wait on
 975   *         PLLRDY flag to be set indicating that PLL clock is stable and can
 976   *         be used as system clock source.
 977   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
 978   */
 979 #define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
 980
 981 /** @brief Macros to disable the main PLL.
 982   * @note   The main PLL can not be disabled if it is used as system clock source
 983   */
 984 #define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
 985
 986 /** @brief macros to configure the main PLL clock source and multiplication factors.
 987   * @note   This function must be used only when the main PLL is disabled.
 988   *
 989   * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
 990   *          This parameter can be one of the following values:
 991   *            @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL clock entry
 992   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
 993   * @param  __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
 994   *          This parameter can be one of the following values:
 995   *             @arg RCC_PLL_MUL2: PLLVCO = PLL clock entry x 2 (*)
 996   *             @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 (*)
 997   *             @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
 998   *             @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
 999   *             @arg RCC_PLL_MUL6_5: PLLVCO = PLL clock entry x 6.5 (**)
1000   *             @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
1001   *             @arg RCC_PLL_MUL9: PLLVCO = PLL clock entry x 9
1002   *             @arg RCC_PLL_MUL10: PLLVCO = PLL clock entry x 10 (*)
1003   *             @arg RCC_PLL_MUL11: PLLVCO = PLL clock entry x 11 (*)
1004   *             @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 (*)
1005   *             @arg RCC_PLL_MUL13: PLLVCO = PLL clock entry x 13 (*)
1006   *             @arg RCC_PLL_MUL14: PLLVCO = PLL clock entry x 14 (*)
1007   *             @arg RCC_PLL_MUL15: PLLVCO = PLL clock entry x 15 (*)
1008   *             @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 (*)
1009   * @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
1010   * @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
1011   *
1012   */
1013 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
1014           MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
1015 /**
1016   * @}
1017   */
1018
1019 /** @defgroup RCC_Get_Clock_source Get Clock source
1020   * @{
1021   */
1022
1023 /** @brief  Macro to get the clock source used as system clock.
1024   * @retval The clock source used as system clock. The returned value can be one
1025   *         of the following:
1026   *             @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
1027   *             @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
1028   *             @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
1029   */
1030 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
1031
1032 /** @brief  Get oscillator clock selected as PLL input clock
1033   * @retval The clock source used for PLL entry. The returned value can be one
1034   *         of the following:
1035   *             @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL input clock
1036   *             @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
1037   */
1038 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
1039
1040 /**
1041   * @}
1042   */
1043 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
1044   * @{
1045   */
1046
1047 /** @brief Macro to configures the RTC clock (RTCCLK).
1048   * @note   As the RTC clock configuration bits are in the Backup domain and write
1049   *         access is denied to this domain after reset, you have to enable write
1050   *         access using the Power Backup Access macro before to configure
1051   *         the RTC clock source (to be done once after reset).
1052   * @note   Once the RTC clock is configured it can't be changed unless the
1053   *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
1054   *         a Power On Reset (POR).
1055   *
1056   * @param  __RTC_CLKSOURCE__: specifies the RTC clock source.
1057   *          This parameter can be one of the following values:
1058   *             @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
1059   *             @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
1060   *             @arg RCC_RTCCLKSOURCE_HSE_DIV128: HSE divided by 128 selected as RTC clock
1061   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
1062   *         work in STOP and STANDBY modes, and can be used as wakeup source.
1063   *         However, when the HSE clock is used as RTC clock source, the RTC
1064   *         cannot be used in STOP and STANDBY modes.
1065   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
1066   *         RTC clock source).
1067   */
1068 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
1069
1070
1071 /** @brief macros to get the RTC clock source.
1072   */
1073 #define __HAL_RCC_GET_RTC_SOURCE()              READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)
1074
1075 /** @brief Macros to enable the the RTC clock.
1076   * @note  These macros must be used only after the RTC clock source was selected.
1077   */
1078 #define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
1079
1080 /** @brief Macros to disable the the RTC clock.
1081   * @note   These macros must be used only after the RTC clock source was selected.
1082   */
1083 #define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
1084
1085 /** @brief  Macros to force the Backup domain reset.
1086   * @note   This function resets the entire Backup domain.
1087   */
1088 #define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1089
1090 /** @brief  Macros to release the Backup domain reset.
1091   */
1092 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1093
1094
1095 /**
1096   * @}
1097   */
1098
1099 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1100   * @brief macros to manage the specified RCC Flags and interrupts.
1101   * @{
1102   */
1103
1104 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
1105   *        the selected interrupts.).
1106   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
1107   *          This parameter can be any combination of the following values:
1108   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
1109   *            @arg RCC_IT_LSERDY: LSE ready interrupt
1110   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
1111   *            @arg RCC_IT_HSERDY: HSE ready interrupt
1112   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
1113   *            @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
1114   *            @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
1115   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
1116   */
1117 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1118
1119 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
1120   *        the selected interrupts).
1121   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
1122   *          This parameter can be any combination of the following values:
1123   *            @arg RCC_IT_LSIRDY: LSI ready interrupt
1124   *            @arg RCC_IT_LSERDY: LSE ready interrupt
1125   *            @arg RCC_IT_HSIRDY: HSI ready interrupt
1126   *            @arg RCC_IT_HSERDY: HSE ready interrupt
1127   *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
1128   *            @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
1129   *            @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
1130   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
1131   */
1132 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
1133
1134 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
1135   *        bits to clear the selected interrupt pending bits.
1136   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
1137   *          This parameter can be any combination of the following values:
1138   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
1139   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
1140   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
1141   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
1142   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1143   *            @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
1144   *            @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
1145   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
1146   *            @arg RCC_IT_CSS: Clock Security System interrupt
1147   */
1148 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1149
1150 /** @brief Check the RCC's interrupt has occurred or not.
1151   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
1152   *          This parameter can be one of the following values:
1153   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
1154   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
1155   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
1156   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
1157   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1158   *            @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
1159   *            @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
1160   *            @arg RCC_IT_CSS: Clock Security System interrupt
1161   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
1162   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1163   */
1164 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1165
1166 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1167   * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1168   */
1169 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1170
1171 /** @brief  Check RCC flag is set or not.
1172   * @param  __FLAG__: specifies the flag to check.
1173   *          This parameter can be one of the following values:
1174   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
1175   *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
1176   *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
1177   *            @arg RCC_FLAG_PLL2RDY: Main PLL2 clock ready.(*)
1178   *            @arg RCC_FLAG_PLLI2SRDY: Main PLLI2S clock ready.(*)
1179   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
1180   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
1181   *            @arg RCC_FLAG_PINRST: Pin reset.
1182   *            @arg RCC_FLAG_PORRST: POR/PDR reset.
1183   *            @arg RCC_FLAG_SFTRST: Software reset.
1184   *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
1185   *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
1186   *            @arg RCC_FLAG_LPWRRST: Low Power reset.
1187   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
1188   * @retval The new state of __FLAG__ (TRUE or FALSE).
1189   */
1190 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
1191 /**
1192   * @}
1193   */
1194
1195 /**
1196   * @}
1197   */
1198
1199 /* Include RCC HAL Extension module */
1200 #include "stm32f1xx_hal_rcc_ex.h"
1201
1202 /* Exported functions --------------------------------------------------------*/
1203 /** @addtogroup RCC_Exported_Functions
1204   * @{
1205   */
1206
1207 /** @addtogroup RCC_Exported_Functions_Group1
1208   * @{
1209   */
1210
1211 /* Initialization and de-initialization functions  ******************************/
1212 void              HAL_RCC_DeInit(void);
1213 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1214 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
1215
1216 /**
1217   * @}
1218   */
1219
1220 /** @addtogroup RCC_Exported_Functions_Group2
1221   * @{
1222   */
1223
1224 /* Peripheral Control functions  ************************************************/
1225 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1226 void              HAL_RCC_EnableCSS(void);
1227 void              HAL_RCC_DisableCSS(void);
1228 uint32_t          HAL_RCC_GetSysClockFreq(void);
1229 uint32_t          HAL_RCC_GetHCLKFreq(void);
1230 uint32_t          HAL_RCC_GetPCLK1Freq(void);
1231 uint32_t          HAL_RCC_GetPCLK2Freq(void);
1232 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1233 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
1234
1235 /* CSS NMI IRQ handler */
1236 void              HAL_RCC_NMI_IRQHandler(void);
1237
1238 /* User Callbacks in non blocking mode (IT mode) */
1239 void              HAL_RCC_CSSCallback(void);
1240
1241 /**
1242   * @}
1243   */
1244
1245 /**
1246   * @}
1247   */
1248
1249 /**
1250   * @}
1251   */
1252
1253 /**
1254   * @}
1255   */
1256
1257 #ifdef __cplusplus
1258 }
1259 #endif
1260
1261 #endif /* __STM32F1xx_HAL_RCC_H */
1262
1263 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/