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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / stm32f3xx_hal_tim_ex.c
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer Extended peripheral:
10 * + Time Hall Sensor Interface Initialization
11 * + Time Hall Sensor Interface Start
12 * + Time Complementary signal bread and dead time configuration
13 * + Time Master and Slave synchronization configuration
14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
15 * + Time OCRef clear configuration
16 * + Timer remapping capabilities configuration
17 @verbatim
18 ==============================================================================
19 ##### TIMER Extended features #####
20 ==============================================================================
21 [..]
22 The Timer Extended features include:
23 (#) Complementary outputs with programmable dead-time for :
24 (++) Output Compare
25 (++) PWM generation (Edge and Center-aligned Mode)
26 (++) One-pulse mode output
27 (#) Synchronization circuit to control the timer with external signals and to
28 interconnect several timers together.
29 (#) Break input to put the timer output signals in reset state or in a known state.
30 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
31 positioning purposes
32
33 ##### How to use this driver #####
34 ==============================================================================
35 [..]
36 (#) Initialize the TIM low level resources by implementing the following functions
37 depending from feature used :
38 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
39 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
40 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
41 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
42
43 (#) Initialize the TIM low level resources :
44 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
45 (##) TIM pins configuration
46 (+++) Enable the clock for the TIM GPIOs using the following function:
47 __GPIOx_CLK_ENABLE();
48 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
49
50 (#) The external Clock can be configured, if needed (the default clock is the
51 internal clock from the APBx), using the following function:
52 HAL_TIM_ConfigClockSource, the clock configuration should be done before
53 any start function.
54
55 (#) Configure the TIM in the desired functioning mode using one of the
56 initialization function of this driver:
57 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
58 Timer Hall Sensor Interface and the commutation event with the corresponding
59 Interrupt and DMA request if needed (Note that One Timer is used to interface
60 with the Hall sensor Interface and another Timer should be used to use
61 the commutation event).
62
63 (#) Activate the TIM peripheral using one of the start functions:
64 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
65 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
66 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
67 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
68
69
70 @endverbatim
71 ******************************************************************************
72 * @attention
73 *
74 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
75 *
76 * Redistribution and use in source and binary forms, with or without modification,
77 * are permitted provided that the following conditions are met:
78 * 1. Redistributions of source code must retain the above copyright notice,
79 * this list of conditions and the following disclaimer.
80 * 2. Redistributions in binary form must reproduce the above copyright notice,
81 * this list of conditions and the following disclaimer in the documentation
82 * and/or other materials provided with the distribution.
83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
84 * may be used to endorse or promote products derived from this software
85 * without specific prior written permission.
86 *
87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
97 *
98 ******************************************************************************
99 */
100
101 /* Includes ------------------------------------------------------------------*/
102 #include "stm32f3xx_hal.h"
103
104 /** @addtogroup STM32F3xx_HAL_Driver
105 * @{
106 */
107
108 /** @defgroup TIMEx TIM Extended HAL module driver
109 * @brief TIM Extended HAL module driver
110 * @{
111 */
112
113 #ifdef HAL_TIM_MODULE_ENABLED
114
115 /* Private typedef -----------------------------------------------------------*/
116 /* Private define ------------------------------------------------------------*/
117 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
118 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
119 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
120 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
121
122 #define BDTR_BKF_SHIFT (16)
123 #define BDTR_BK2F_SHIFT (20)
124 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
125 /* STM32F302xC || STM32F303xC || STM32F358xx || */
126 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
127 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
128
129 /* Private macro -------------------------------------------------------------*/
130 /* Private variables ---------------------------------------------------------*/
131 /* Private function prototypes -----------------------------------------------*/
132 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
133 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
134 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
135 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
136 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
137 TIM_OC_InitTypeDef *OC_Config);
138
139 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
140 TIM_OC_InitTypeDef *OC_Config);
141 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
142 /* STM32F302xC || STM32F303xC || STM32F358xx || */
143 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
144 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
145
146 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
147
148 /* Private functions ---------------------------------------------------------*/
149 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
150 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
151 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
152 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
153 /**
154 * @brief Timer Ouput Compare 5 configuration
155 * @param TIMx to select the TIM peripheral
156 * @param OC_Config: The ouput configuration structure
157 * @retval None
158 */
159 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
160 TIM_OC_InitTypeDef *OC_Config)
161 {
162 uint32_t tmpccmrx = 0;
163 uint32_t tmpccer = 0;
164 uint32_t tmpcr2 = 0;
165
166 /* Disable the output: Reset the CCxE Bit */
167 TIMx->CCER &= ~TIM_CCER_CC5E;
168
169 /* Get the TIMx CCER register value */
170 tmpccer = TIMx->CCER;
171 /* Get the TIMx CR2 register value */
172 tmpcr2 = TIMx->CR2;
173 /* Get the TIMx CCMR1 register value */
174 tmpccmrx = TIMx->CCMR3;
175
176 /* Reset the Output Compare Mode Bits */
177 tmpccmrx &= ~(TIM_CCMR3_OC5M);
178 /* Select the Output Compare Mode */
179 tmpccmrx |= OC_Config->OCMode;
180
181 /* Reset the Output Polarity level */
182 tmpccer &= ~TIM_CCER_CC5P;
183 /* Set the Output Compare Polarity */
184 tmpccer |= (OC_Config->OCPolarity << 16);
185
186 if(IS_TIM_BREAK_INSTANCE(TIMx))
187 {
188 /* Reset the Output Compare IDLE State */
189 tmpcr2 &= ~TIM_CR2_OIS5;
190 /* Set the Output Idle state */
191 tmpcr2 |= (OC_Config->OCIdleState << 8);
192 }
193 /* Write to TIMx CR2 */
194 TIMx->CR2 = tmpcr2;
195
196 /* Write to TIMx CCMR3 */
197 TIMx->CCMR3 = tmpccmrx;
198
199 /* Set the Capture Compare Register value */
200 TIMx->CCR5 = OC_Config->Pulse;
201
202 /* Write to TIMx CCER */
203 TIMx->CCER = tmpccer;
204 }
205
206 /**
207 * @brief Timer Ouput Compare 6 configuration
208 * @param TIMx to select the TIM peripheral
209 * @param OC_Config: The ouput configuration structure
210 * @retval None
211 */
212 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
213 TIM_OC_InitTypeDef *OC_Config)
214 {
215 uint32_t tmpccmrx = 0;
216 uint32_t tmpccer = 0;
217 uint32_t tmpcr2 = 0;
218
219 /* Disable the output: Reset the CCxE Bit */
220 TIMx->CCER &= ~TIM_CCER_CC6E;
221
222 /* Get the TIMx CCER register value */
223 tmpccer = TIMx->CCER;
224 /* Get the TIMx CR2 register value */
225 tmpcr2 = TIMx->CR2;
226 /* Get the TIMx CCMR1 register value */
227 tmpccmrx = TIMx->CCMR3;
228
229 /* Reset the Output Compare Mode Bits */
230 tmpccmrx &= ~(TIM_CCMR3_OC6M);
231 /* Select the Output Compare Mode */
232 tmpccmrx |= (OC_Config->OCMode << 8);
233
234 /* Reset the Output Polarity level */
235 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
236 /* Set the Output Compare Polarity */
237 tmpccer |= (OC_Config->OCPolarity << 20);
238
239 if(IS_TIM_BREAK_INSTANCE(TIMx))
240 {
241 /* Reset the Output Compare IDLE State */
242 tmpcr2 &= ~TIM_CR2_OIS6;
243 /* Set the Output Idle state */
244 tmpcr2 |= (OC_Config->OCIdleState << 10);
245 }
246
247 /* Write to TIMx CR2 */
248 TIMx->CR2 = tmpcr2;
249
250 /* Write to TIMx CCMR3 */
251 TIMx->CCMR3 = tmpccmrx;
252
253 /* Set the Capture Compare Register value */
254 TIMx->CCR6 = OC_Config->Pulse;
255
256 /* Write to TIMx CCER */
257 TIMx->CCER = tmpccer;
258 }
259 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
260 /* STM32F302xC || STM32F303xC || STM32F358xx || */
261 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
262 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
263
264 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
265 * @{
266 */
267
268 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
269 * @brief Timer Hall Sensor functions
270 *
271 @verbatim
272 ==============================================================================
273 ##### Timer Hall Sensor functions #####
274 ==============================================================================
275 [..]
276 This section provides functions allowing to:
277 (+) Initialize and configure TIM HAL Sensor.
278 (+) De-initialize TIM HAL Sensor.
279 (+) Start the Hall Sensor Interface.
280 (+) Stop the Hall Sensor Interface.
281 (+) Start the Hall Sensor Interface and enable interrupts.
282 (+) Stop the Hall Sensor Interface and disable interrupts.
283 (+) Start the Hall Sensor Interface and enable DMA transfers.
284 (+) Stop the Hall Sensor Interface and disable DMA transfers.
285
286 @endverbatim
287 * @{
288 */
289 /**
290 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
291 * @param htim: TIM Encoder Interface handle
292 * @param sConfig: TIM Hall Sensor configuration structure
293 * @retval HAL status
294 */
295 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
296 {
297 TIM_OC_InitTypeDef OC_Config;
298
299 /* Check the TIM handle allocation */
300 if(htim == HAL_NULL)
301 {
302 return HAL_ERROR;
303 }
304
305 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
306 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
307 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
308 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
309 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
310 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
311
312 /* Set the TIM state */
313 htim->State= HAL_TIM_STATE_BUSY;
314
315 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
316 HAL_TIMEx_HallSensor_MspInit(htim);
317
318 /* Configure the Time base in the Encoder Mode */
319 TIM_Base_SetConfig(htim->Instance, &htim->Init);
320
321 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
322 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
323
324 /* Reset the IC1PSC Bits */
325 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
326 /* Set the IC1PSC value */
327 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
328
329 /* Enable the Hall sensor interface (XOR function of the three inputs) */
330 htim->Instance->CR2 |= TIM_CR2_TI1S;
331
332 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
333 htim->Instance->SMCR &= ~TIM_SMCR_TS;
334 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
335
336 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
337 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
338 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
339
340 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
341 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
342 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
343 OC_Config.OCMode = TIM_OCMODE_PWM2;
344 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
345 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
346 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
347 OC_Config.Pulse = sConfig->Commutation_Delay;
348
349 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
350
351 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
352 register to 101 */
353 htim->Instance->CR2 &= ~TIM_CR2_MMS;
354 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
355
356 /* Initialize the TIM state*/
357 htim->State= HAL_TIM_STATE_READY;
358
359 return HAL_OK;
360 }
361
362 /**
363 * @brief DeInitializes the TIM Hall Sensor interface
364 * @param htim: TIM Hall Sensor handle
365 * @retval HAL status
366 */
367 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
368 {
369 /* Check the parameters */
370 assert_param(IS_TIM_INSTANCE(htim->Instance));
371
372 htim->State = HAL_TIM_STATE_BUSY;
373
374 /* Disable the TIM Peripheral Clock */
375 __HAL_TIM_DISABLE(htim);
376
377 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
378 HAL_TIMEx_HallSensor_MspDeInit(htim);
379
380 /* Change TIM state */
381 htim->State = HAL_TIM_STATE_RESET;
382
383 /* Release Lock */
384 __HAL_UNLOCK(htim);
385
386 return HAL_OK;
387 }
388
389 /**
390 * @brief Initializes the TIM Hall Sensor MSP.
391 * @param htim: TIM handle
392 * @retval None
393 */
394 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
395 {
396 /* NOTE : This function Should not be modified, when the callback is needed,
397 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
398 */
399 }
400
401 /**
402 * @brief DeInitializes TIM Hall Sensor MSP.
403 * @param htim: TIM handle
404 * @retval None
405 */
406 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
407 {
408 /* NOTE : This function Should not be modified, when the callback is needed,
409 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
410 */
411 }
412
413 /**
414 * @brief Starts the TIM Hall Sensor Interface.
415 * @param htim : TIM Hall Sensor handle
416 * @retval HAL status
417 */
418 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
419 {
420 /* Check the parameters */
421 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
422
423 /* Enable the Input Capture channels 1
424 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
425 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
426
427 /* Enable the Peripheral */
428 __HAL_TIM_ENABLE(htim);
429
430 /* Return function status */
431 return HAL_OK;
432 }
433
434 /**
435 * @brief Stops the TIM Hall sensor Interface.
436 * @param htim : TIM Hall Sensor handle
437 * @retval HAL status
438 */
439 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
440 {
441 /* Check the parameters */
442 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
443
444 /* Disable the Input Capture channels 1, 2 and 3
445 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
446 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
447
448 /* Disable the Peripheral */
449 __HAL_TIM_DISABLE(htim);
450
451 /* Return function status */
452 return HAL_OK;
453 }
454
455 /**
456 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
457 * @param htim : TIM Hall Sensor handle
458 * @retval HAL status
459 */
460 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
461 {
462 /* Check the parameters */
463 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
464
465 /* Enable the capture compare Interrupts 1 event */
466 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
467
468 /* Enable the Input Capture channels 1
469 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
470 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
471
472 /* Enable the Peripheral */
473 __HAL_TIM_ENABLE(htim);
474
475 /* Return function status */
476 return HAL_OK;
477 }
478
479 /**
480 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
481 * @param htim : TIM handle
482 * @retval HAL status
483 */
484 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
485 {
486 /* Check the parameters */
487 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
488
489 /* Disable the Input Capture channels 1
490 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
492
493 /* Disable the capture compare Interrupts event */
494 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
495
496 /* Disable the Peripheral */
497 __HAL_TIM_DISABLE(htim);
498
499 /* Return function status */
500 return HAL_OK;
501 }
502
503 /**
504 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
505 * @param htim : TIM Hall Sensor handle
506 * @param pData: The destination Buffer address.
507 * @param Length: The length of data to be transferred from TIM peripheral to memory.
508 * @retval HAL status
509 */
510 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
511 {
512 /* Check the parameters */
513 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
514
515 if((htim->State == HAL_TIM_STATE_BUSY))
516 {
517 return HAL_BUSY;
518 }
519 else if((htim->State == HAL_TIM_STATE_READY))
520 {
521 if(((uint32_t)pData == 0 ) && (Length > 0))
522 {
523 return HAL_ERROR;
524 }
525 else
526 {
527 htim->State = HAL_TIM_STATE_BUSY;
528 }
529 }
530 /* Enable the Input Capture channels 1
531 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
532 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
533
534 /* Set the DMA Input Capture 1 Callback */
535 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
536 /* Set the DMA error callback */
537 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
538
539 /* Enable the DMA channel for Capture 1*/
540 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
541
542 /* Enable the capture compare 1 Interrupt */
543 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
544
545 /* Enable the Peripheral */
546 __HAL_TIM_ENABLE(htim);
547
548 /* Return function status */
549 return HAL_OK;
550 }
551
552 /**
553 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
554 * @param htim : TIM handle
555 * @retval HAL status
556 */
557 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
558 {
559 /* Check the parameters */
560 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
561
562 /* Disable the Input Capture channels 1
563 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
564 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
565
566
567 /* Disable the capture compare Interrupts 1 event */
568 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
569
570 /* Disable the Peripheral */
571 __HAL_TIM_DISABLE(htim);
572
573 /* Return function status */
574 return HAL_OK;
575 }
576
577 /**
578 * @}
579 */
580
581 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
582 * @brief Timer Complementary Output Compare functions
583 *
584 @verbatim
585 ==============================================================================
586 ##### Timer Complementary Output Compare functions #####
587 ==============================================================================
588 [..]
589 This section provides functions allowing to:
590 (+) Start the Complementary Output Compare/PWM.
591 (+) Stop the Complementary Output Compare/PWM.
592 (+) Start the Complementary Output Compare/PWM and enable interrupts.
593 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
594 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
595 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
596
597 @endverbatim
598 * @{
599 */
600
601 /**
602 * @brief Starts the TIM Output Compare signal generation on the complementary
603 * output.
604 * @param htim : TIM Output Compare handle
605 * @param Channel : TIM Channel to be enabled
606 * This parameter can be one of the following values:
607 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
608 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
609 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
610 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
611 * @retval HAL status
612 */
613 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
614 {
615 /* Check the parameters */
616 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
617
618 /* Enable the Capture compare channel N */
619 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
620
621 /* Enable the Main Ouput */
622 __HAL_TIM_MOE_ENABLE(htim);
623
624 /* Enable the Peripheral */
625 __HAL_TIM_ENABLE(htim);
626
627 /* Return function status */
628 return HAL_OK;
629 }
630
631 /**
632 * @brief Stops the TIM Output Compare signal generation on the complementary
633 * output.
634 * @param htim : TIM handle
635 * @param Channel : TIM Channel to be disabled
636 * This parameter can be one of the following values:
637 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
638 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
639 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
640 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
641 * @retval HAL status
642 */
643 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
644 {
645 /* Check the parameters */
646 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
647
648 /* Disable the Capture compare channel N */
649 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
650
651 /* Disable the Main Ouput */
652 __HAL_TIM_MOE_DISABLE(htim);
653
654 /* Disable the Peripheral */
655 __HAL_TIM_DISABLE(htim);
656
657 /* Return function status */
658 return HAL_OK;
659 }
660
661 /**
662 * @brief Starts the TIM Output Compare signal generation in interrupt mode
663 * on the complementary output.
664 * @param htim : TIM OC handle
665 * @param Channel : TIM Channel to be enabled
666 * This parameter can be one of the following values:
667 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
668 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
669 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
670 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
671 * @retval HAL status
672 */
673 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
674 {
675 /* Check the parameters */
676 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
677
678 switch (Channel)
679 {
680 case TIM_CHANNEL_1:
681 {
682 /* Enable the TIM Output Compare interrupt */
683 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
684 }
685 break;
686
687 case TIM_CHANNEL_2:
688 {
689 /* Enable the TIM Output Compare interrupt */
690 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
691 }
692 break;
693
694 case TIM_CHANNEL_3:
695 {
696 /* Enable the TIM Output Compare interrupt */
697 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
698 }
699 break;
700
701 case TIM_CHANNEL_4:
702 {
703 /* Enable the TIM Output Compare interrupt */
704 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
705 }
706 break;
707
708 default:
709 break;
710 }
711
712 /* Enable the TIM Break interrupt */
713 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
714
715 /* Enable the Capture compare channel N */
716 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
717
718 /* Enable the Main Ouput */
719 __HAL_TIM_MOE_ENABLE(htim);
720
721 /* Enable the Peripheral */
722 __HAL_TIM_ENABLE(htim);
723
724 /* Return function status */
725 return HAL_OK;
726 }
727
728 /**
729 * @brief Stops the TIM Output Compare signal generation in interrupt mode
730 * on the complementary output.
731 * @param htim : TIM Output Compare handle
732 * @param Channel : TIM Channel to be disabled
733 * This parameter can be one of the following values:
734 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
735 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
736 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
737 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
738 * @retval HAL status
739 */
740 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
741 {
742 uint32_t tmpccer = 0;
743
744 /* Check the parameters */
745 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
746
747 switch (Channel)
748 {
749 case TIM_CHANNEL_1:
750 {
751 /* Disable the TIM Output Compare interrupt */
752 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
753 }
754 break;
755
756 case TIM_CHANNEL_2:
757 {
758 /* Disable the TIM Output Compare interrupt */
759 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
760 }
761 break;
762
763 case TIM_CHANNEL_3:
764 {
765 /* Disable the TIM Output Compare interrupt */
766 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
767 }
768 break;
769
770 case TIM_CHANNEL_4:
771 {
772 /* Disable the TIM Output Compare interrupt */
773 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
774 }
775 break;
776
777 default:
778 break;
779 }
780
781 /* Disable the Capture compare channel N */
782 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
783
784 /* Disable the TIM Break interrupt (only if no more channel is active) */
785 tmpccer = htim->Instance->CCER;
786 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
787 {
788 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
789 }
790
791 /* Disable the Main Ouput */
792 __HAL_TIM_MOE_DISABLE(htim);
793
794 /* Disable the Peripheral */
795 __HAL_TIM_DISABLE(htim);
796
797 /* Return function status */
798 return HAL_OK;
799 }
800
801 /**
802 * @brief Starts the TIM Output Compare signal generation in DMA mode
803 * on the complementary output.
804 * @param htim : TIM Output Compare handle
805 * @param Channel : TIM Channel to be enabled
806 * This parameter can be one of the following values:
807 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
808 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
809 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
810 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
811 * @param pData: The source Buffer address.
812 * @param Length: The length of data to be transferred from memory to TIM peripheral
813 * @retval HAL status
814 */
815 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
816 {
817 /* Check the parameters */
818 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
819
820 if((htim->State == HAL_TIM_STATE_BUSY))
821 {
822 return HAL_BUSY;
823 }
824 else if((htim->State == HAL_TIM_STATE_READY))
825 {
826 if(((uint32_t)pData == 0 ) && (Length > 0))
827 {
828 return HAL_ERROR;
829 }
830 else
831 {
832 htim->State = HAL_TIM_STATE_BUSY;
833 }
834 }
835 switch (Channel)
836 {
837 case TIM_CHANNEL_1:
838 {
839 /* Set the DMA Period elapsed callback */
840 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
841
842 /* Set the DMA error callback */
843 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
844
845 /* Enable the DMA channel */
846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
847
848 /* Enable the TIM Output Compare DMA request */
849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
850 }
851 break;
852
853 case TIM_CHANNEL_2:
854 {
855 /* Set the DMA Period elapsed callback */
856 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
857
858 /* Set the DMA error callback */
859 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
860
861 /* Enable the DMA channel */
862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
863
864 /* Enable the TIM Output Compare DMA request */
865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
866 }
867 break;
868
869 case TIM_CHANNEL_3:
870 {
871 /* Set the DMA Period elapsed callback */
872 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
873
874 /* Set the DMA error callback */
875 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
876
877 /* Enable the DMA channel */
878 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
879
880 /* Enable the TIM Output Compare DMA request */
881 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
882 }
883 break;
884
885 case TIM_CHANNEL_4:
886 {
887 /* Set the DMA Period elapsed callback */
888 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
889
890 /* Set the DMA error callback */
891 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
892
893 /* Enable the DMA channel */
894 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
895
896 /* Enable the TIM Output Compare DMA request */
897 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
898 }
899 break;
900
901 default:
902 break;
903 }
904
905 /* Enable the Capture compare channel N */
906 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
907
908 /* Enable the Main Ouput */
909 __HAL_TIM_MOE_ENABLE(htim);
910
911 /* Enable the Peripheral */
912 __HAL_TIM_ENABLE(htim);
913
914 /* Return function status */
915 return HAL_OK;
916 }
917
918 /**
919 * @brief Stops the TIM Output Compare signal generation in DMA mode
920 * on the complementary output.
921 * @param htim : TIM Output Compare handle
922 * @param Channel : TIM Channel to be disabled
923 * This parameter can be one of the following values:
924 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
925 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
926 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
927 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
928 * @retval HAL status
929 */
930 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
931 {
932 /* Check the parameters */
933 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
934
935 switch (Channel)
936 {
937 case TIM_CHANNEL_1:
938 {
939 /* Disable the TIM Output Compare DMA request */
940 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
941 }
942 break;
943
944 case TIM_CHANNEL_2:
945 {
946 /* Disable the TIM Output Compare DMA request */
947 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
948 }
949 break;
950
951 case TIM_CHANNEL_3:
952 {
953 /* Disable the TIM Output Compare DMA request */
954 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
955 }
956 break;
957
958 case TIM_CHANNEL_4:
959 {
960 /* Disable the TIM Output Compare interrupt */
961 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
962 }
963 break;
964
965 default:
966 break;
967 }
968
969 /* Disable the Capture compare channel N */
970 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
971
972 /* Disable the Main Ouput */
973 __HAL_TIM_MOE_DISABLE(htim);
974
975 /* Disable the Peripheral */
976 __HAL_TIM_DISABLE(htim);
977
978 /* Change the htim state */
979 htim->State = HAL_TIM_STATE_READY;
980
981 /* Return function status */
982 return HAL_OK;
983 }
984
985 /**
986 * @}
987 */
988
989 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
990 * @brief Timer Complementary PWM functions
991 *
992 @verbatim
993 ==============================================================================
994 ##### Timer Complementary PWM functions #####
995 ==============================================================================
996 [..]
997 This section provides functions allowing to:
998 (+) Start the Complementary PWM.
999 (+) Stop the Complementary PWM.
1000 (+) Start the Complementary PWM and enable interrupts.
1001 (+) Stop the Complementary PWM and disable interrupts.
1002 (+) Start the Complementary PWM and enable DMA transfers.
1003 (+) Stop the Complementary PWM and disable DMA transfers.
1004 (+) Start the Complementary Input Capture measurement.
1005 (+) Stop the Complementary Input Capture.
1006 (+) Start the Complementary Input Capture and enable interrupts.
1007 (+) Stop the Complementary Input Capture and disable interrupts.
1008 (+) Start the Complementary Input Capture and enable DMA transfers.
1009 (+) Stop the Complementary Input Capture and disable DMA transfers.
1010 (+) Start the Complementary One Pulse generation.
1011 (+) Stop the Complementary One Pulse.
1012 (+) Start the Complementary One Pulse and enable interrupts.
1013 (+) Stop the Complementary One Pulse and disable interrupts.
1014
1015 @endverbatim
1016 * @{
1017 */
1018
1019 /**
1020 * @brief Starts the PWM signal generation on the complementary output.
1021 * @param htim : TIM handle
1022 * @param Channel : TIM Channel to be enabled
1023 * This parameter can be one of the following values:
1024 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1025 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1026 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1027 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1028 * @retval HAL status
1029 */
1030 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1031 {
1032 /* Check the parameters */
1033 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1034
1035 /* Enable the complementary PWM output */
1036 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1037
1038 /* Enable the Main Ouput */
1039 __HAL_TIM_MOE_ENABLE(htim);
1040
1041 /* Enable the Peripheral */
1042 __HAL_TIM_ENABLE(htim);
1043
1044 /* Return function status */
1045 return HAL_OK;
1046 }
1047
1048 /**
1049 * @brief Stops the PWM signal generation on the complementary output.
1050 * @param htim : TIM handle
1051 * @param Channel : TIM Channel to be disabled
1052 * This parameter can be one of the following values:
1053 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1054 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1055 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1056 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1057 * @retval HAL status
1058 */
1059 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1060 {
1061 /* Check the parameters */
1062 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1063
1064 /* Disable the complementary PWM output */
1065 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1066
1067 /* Disable the Main Ouput */
1068 __HAL_TIM_MOE_DISABLE(htim);
1069
1070 /* Disable the Peripheral */
1071 __HAL_TIM_DISABLE(htim);
1072
1073 /* Return function status */
1074 return HAL_OK;
1075 }
1076
1077 /**
1078 * @brief Starts the PWM signal generation in interrupt mode on the
1079 * complementary output.
1080 * @param htim : TIM handle
1081 * @param Channel : TIM Channel to be disabled
1082 * This parameter can be one of the following values:
1083 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1084 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1085 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1086 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1087 * @retval HAL status
1088 */
1089 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1090 {
1091 /* Check the parameters */
1092 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1093
1094 switch (Channel)
1095 {
1096 case TIM_CHANNEL_1:
1097 {
1098 /* Enable the TIM Capture/Compare 1 interrupt */
1099 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1100 }
1101 break;
1102
1103 case TIM_CHANNEL_2:
1104 {
1105 /* Enable the TIM Capture/Compare 2 interrupt */
1106 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1107 }
1108 break;
1109
1110 case TIM_CHANNEL_3:
1111 {
1112 /* Enable the TIM Capture/Compare 3 interrupt */
1113 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1114 }
1115 break;
1116
1117 case TIM_CHANNEL_4:
1118 {
1119 /* Enable the TIM Capture/Compare 4 interrupt */
1120 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1121 }
1122 break;
1123
1124 default:
1125 break;
1126 }
1127
1128 /* Enable the TIM Break interrupt */
1129 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1130
1131 /* Enable the complementary PWM output */
1132 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1133
1134 /* Enable the Main Ouput */
1135 __HAL_TIM_MOE_ENABLE(htim);
1136
1137 /* Enable the Peripheral */
1138 __HAL_TIM_ENABLE(htim);
1139
1140 /* Return function status */
1141 return HAL_OK;
1142 }
1143
1144 /**
1145 * @brief Stops the PWM signal generation in interrupt mode on the
1146 * complementary output.
1147 * @param htim : TIM handle
1148 * @param Channel : TIM Channel to be disabled
1149 * This parameter can be one of the following values:
1150 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1151 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1152 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1153 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1154 * @retval HAL status
1155 */
1156 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1157 {
1158 uint32_t tmpccer = 0;
1159
1160 /* Check the parameters */
1161 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1162
1163 switch (Channel)
1164 {
1165 case TIM_CHANNEL_1:
1166 {
1167 /* Disable the TIM Capture/Compare 1 interrupt */
1168 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1169 }
1170 break;
1171
1172 case TIM_CHANNEL_2:
1173 {
1174 /* Disable the TIM Capture/Compare 2 interrupt */
1175 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1176 }
1177 break;
1178
1179 case TIM_CHANNEL_3:
1180 {
1181 /* Disable the TIM Capture/Compare 3 interrupt */
1182 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1183 }
1184 break;
1185
1186 case TIM_CHANNEL_4:
1187 {
1188 /* Disable the TIM Capture/Compare 3 interrupt */
1189 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1190 }
1191 break;
1192
1193 default:
1194 break;
1195 }
1196
1197 /* Disable the complementary PWM output */
1198 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1199
1200 /* Disable the TIM Break interrupt (only if no more channel is active) */
1201 tmpccer = htim->Instance->CCER;
1202 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
1203 {
1204 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1205 }
1206
1207 /* Disable the Main Ouput */
1208 __HAL_TIM_MOE_DISABLE(htim);
1209
1210 /* Disable the Peripheral */
1211 __HAL_TIM_DISABLE(htim);
1212
1213 /* Return function status */
1214 return HAL_OK;
1215 }
1216
1217 /**
1218 * @brief Starts the TIM PWM signal generation in DMA mode on the
1219 * complementary output
1220 * @param htim : TIM handle
1221 * @param Channel : TIM Channel to be enabled
1222 * This parameter can be one of the following values:
1223 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1224 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1225 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1226 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1227 * @param pData: The source Buffer address.
1228 * @param Length: The length of data to be transferred from memory to TIM peripheral
1229 * @retval HAL status
1230 */
1231 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1232 {
1233 /* Check the parameters */
1234 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1235
1236 if((htim->State == HAL_TIM_STATE_BUSY))
1237 {
1238 return HAL_BUSY;
1239 }
1240 else if((htim->State == HAL_TIM_STATE_READY))
1241 {
1242 if(((uint32_t)pData == 0 ) && (Length > 0))
1243 {
1244 return HAL_ERROR;
1245 }
1246 else
1247 {
1248 htim->State = HAL_TIM_STATE_BUSY;
1249 }
1250 }
1251 switch (Channel)
1252 {
1253 case TIM_CHANNEL_1:
1254 {
1255 /* Set the DMA Period elapsed callback */
1256 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1257
1258 /* Set the DMA error callback */
1259 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1260
1261 /* Enable the DMA channel */
1262 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1263
1264 /* Enable the TIM Capture/Compare 1 DMA request */
1265 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1266 }
1267 break;
1268
1269 case TIM_CHANNEL_2:
1270 {
1271 /* Set the DMA Period elapsed callback */
1272 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1273
1274 /* Set the DMA error callback */
1275 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1276
1277 /* Enable the DMA channel */
1278 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1279
1280 /* Enable the TIM Capture/Compare 2 DMA request */
1281 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1282 }
1283 break;
1284
1285 case TIM_CHANNEL_3:
1286 {
1287 /* Set the DMA Period elapsed callback */
1288 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1289
1290 /* Set the DMA error callback */
1291 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1292
1293 /* Enable the DMA channel */
1294 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1295
1296 /* Enable the TIM Capture/Compare 3 DMA request */
1297 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1298 }
1299 break;
1300
1301 case TIM_CHANNEL_4:
1302 {
1303 /* Set the DMA Period elapsed callback */
1304 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1305
1306 /* Set the DMA error callback */
1307 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1308
1309 /* Enable the DMA channel */
1310 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1311
1312 /* Enable the TIM Capture/Compare 4 DMA request */
1313 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1314 }
1315 break;
1316
1317 default:
1318 break;
1319 }
1320
1321 /* Enable the complementary PWM output */
1322 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1323
1324 /* Enable the Main Ouput */
1325 __HAL_TIM_MOE_ENABLE(htim);
1326
1327 /* Enable the Peripheral */
1328 __HAL_TIM_ENABLE(htim);
1329
1330 /* Return function status */
1331 return HAL_OK;
1332 }
1333
1334 /**
1335 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1336 * output
1337 * @param htim : TIM handle
1338 * @param Channel : TIM Channel to be disabled
1339 * This parameter can be one of the following values:
1340 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1341 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1342 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1343 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1344 * @retval HAL status
1345 */
1346 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1347 {
1348 /* Check the parameters */
1349 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1350
1351 switch (Channel)
1352 {
1353 case TIM_CHANNEL_1:
1354 {
1355 /* Disable the TIM Capture/Compare 1 DMA request */
1356 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1357 }
1358 break;
1359
1360 case TIM_CHANNEL_2:
1361 {
1362 /* Disable the TIM Capture/Compare 2 DMA request */
1363 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1364 }
1365 break;
1366
1367 case TIM_CHANNEL_3:
1368 {
1369 /* Disable the TIM Capture/Compare 3 DMA request */
1370 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1371 }
1372 break;
1373
1374 case TIM_CHANNEL_4:
1375 {
1376 /* Disable the TIM Capture/Compare 4 DMA request */
1377 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1378 }
1379 break;
1380
1381 default:
1382 break;
1383 }
1384
1385 /* Disable the complementary PWM output */
1386 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1387
1388 /* Disable the Main Ouput */
1389 __HAL_TIM_MOE_DISABLE(htim);
1390
1391 /* Disable the Peripheral */
1392 __HAL_TIM_DISABLE(htim);
1393
1394 /* Change the htim state */
1395 htim->State = HAL_TIM_STATE_READY;
1396
1397 /* Return function status */
1398 return HAL_OK;
1399 }
1400
1401 /**
1402 * @}
1403 */
1404
1405 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1406 * @brief Timer Complementary One Pulse functions
1407 *
1408 @verbatim
1409 ==============================================================================
1410 ##### Timer Complementary One Pulse functions #####
1411 ==============================================================================
1412 [..]
1413 This section provides functions allowing to:
1414 (+) Start the Complementary One Pulse generation.
1415 (+) Stop the Complementary One Pulse.
1416 (+) Start the Complementary One Pulse and enable interrupts.
1417 (+) Stop the Complementary One Pulse and disable interrupts.
1418
1419 @endverbatim
1420 * @{
1421 */
1422
1423 /**
1424 * @brief Starts the TIM One Pulse signal generation on the complemetary
1425 * output.
1426 * @param htim : TIM One Pulse handle
1427 * @param OutputChannel : TIM Channel to be enabled
1428 * This parameter can be one of the following values:
1429 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1430 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1431 * @retval HAL status
1432 */
1433 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1434 {
1435 /* Check the parameters */
1436 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1437
1438 /* Enable the complementary One Pulse output */
1439 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1440
1441 /* Enable the Main Ouput */
1442 __HAL_TIM_MOE_ENABLE(htim);
1443
1444 /* Return function status */
1445 return HAL_OK;
1446 }
1447
1448 /**
1449 * @brief Stops the TIM One Pulse signal generation on the complementary
1450 * output.
1451 * @param htim : TIM One Pulse handle
1452 * @param OutputChannel : TIM Channel to be disabled
1453 * This parameter can be one of the following values:
1454 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1455 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1456 * @retval HAL status
1457 */
1458 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1459 {
1460
1461 /* Check the parameters */
1462 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1463
1464 /* Disable the complementary One Pulse output */
1465 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1466
1467 /* Disable the Main Ouput */
1468 __HAL_TIM_MOE_DISABLE(htim);
1469
1470 /* Disable the Peripheral */
1471 __HAL_TIM_DISABLE(htim);
1472
1473 /* Return function status */
1474 return HAL_OK;
1475 }
1476
1477 /**
1478 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1479 * complementary channel.
1480 * @param htim : TIM One Pulse handle
1481 * @param OutputChannel : TIM Channel to be enabled
1482 * This parameter can be one of the following values:
1483 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1484 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1485 * @retval HAL status
1486 */
1487 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1488 {
1489 /* Check the parameters */
1490 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1491
1492 /* Enable the TIM Capture/Compare 1 interrupt */
1493 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1494
1495 /* Enable the TIM Capture/Compare 2 interrupt */
1496 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1497
1498 /* Enable the complementary One Pulse output */
1499 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1500
1501 /* Enable the Main Ouput */
1502 __HAL_TIM_MOE_ENABLE(htim);
1503
1504 /* Return function status */
1505 return HAL_OK;
1506 }
1507
1508 /**
1509 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1510 * complementary channel.
1511 * @param htim : TIM One Pulse handle
1512 * @param OutputChannel : TIM Channel to be disabled
1513 * This parameter can be one of the following values:
1514 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1515 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1516 * @retval HAL status
1517 */
1518 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1519 {
1520 /* Check the parameters */
1521 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1522
1523 /* Disable the TIM Capture/Compare 1 interrupt */
1524 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1525
1526 /* Disable the TIM Capture/Compare 2 interrupt */
1527 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1528
1529 /* Disable the complementary One Pulse output */
1530 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1531
1532 /* Disable the Main Ouput */
1533 __HAL_TIM_MOE_DISABLE(htim);
1534
1535 /* Disable the Peripheral */
1536 __HAL_TIM_DISABLE(htim);
1537
1538 /* Return function status */
1539 return HAL_OK;
1540 }
1541
1542
1543
1544 /**
1545 * @}
1546 */
1547 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1548 * @brief Peripheral Control functions
1549 *
1550 @verbatim
1551 ==============================================================================
1552 ##### Peripheral Control functions #####
1553 ==============================================================================
1554 [..]
1555 This section provides functions allowing to:
1556 (+) Configure the commutation event in case of use of the Hall sensor interface.
1557 (+) Configure Output channels for OC and PWM mode.
1558
1559 (+) Configure Complementary channels, break features and dead time.
1560 (+) Configure Master synchronization.
1561 (+) Configure timer remapping capabilities.
1562 (+) Enable or disable channel grouping
1563
1564 @endverbatim
1565 * @{
1566 */
1567 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1568 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1569 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1570 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1571 /**
1572 * @brief Configure the TIM commutation event sequence.
1573 * @note: this function is mandatory to use the commutation event in order to
1574 * update the configuration at each commutation detection on the TRGI input of the Timer,
1575 * the typical use of this feature is with the use of another Timer(interface Timer)
1576 * configured in Hall sensor interface, this interface Timer will generate the
1577 * commutation at its TRGO output (connected to Timer used in this function) each time
1578 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1579 * @param htim: TIM handle
1580 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1581 * This parameter can be one of the following values:
1582 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1583 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1584 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1585 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1586 * @arg TIM_TS_NONE: No trigger is needed
1587 * @param CommutationSource : the Commutation Event source
1588 * This parameter can be one of the following values:
1589 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1590 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1591 * @retval HAL status
1592 */
1593 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1594 {
1595 /* Check the parameters */
1596 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1597 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1598
1599 __HAL_LOCK(htim);
1600
1601 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1602 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1603 {
1604 /* Select the Input trigger */
1605 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1606 htim->Instance->SMCR |= InputTrigger;
1607 }
1608
1609 /* Select the Capture Compare preload feature */
1610 htim->Instance->CR2 |= TIM_CR2_CCPC;
1611 /* Select the Commutation event source */
1612 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1613 htim->Instance->CR2 |= CommutationSource;
1614
1615 __HAL_UNLOCK(htim);
1616
1617 return HAL_OK;
1618 }
1619
1620 /**
1621 * @brief Configure the TIM commutation event sequence with interrupt.
1622 * @note: this function is mandatory to use the commutation event in order to
1623 * update the configuration at each commutation detection on the TRGI input of the Timer,
1624 * the typical use of this feature is with the use of another Timer(interface Timer)
1625 * configured in Hall sensor interface, this interface Timer will generate the
1626 * commutation at its TRGO output (connected to Timer used in this function) each time
1627 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1628 * @param htim: TIM handle
1629 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1630 * This parameter can be one of the following values:
1631 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1632 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1633 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1634 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1635 * @arg TIM_TS_NONE: No trigger is needed
1636 * @param CommutationSource : the Commutation Event source
1637 * This parameter can be one of the following values:
1638 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1639 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1640 * @retval HAL status
1641 */
1642 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1643 {
1644 /* Check the parameters */
1645 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1646 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1647
1648 __HAL_LOCK(htim);
1649
1650 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1651 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1652 {
1653 /* Select the Input trigger */
1654 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1655 htim->Instance->SMCR |= InputTrigger;
1656 }
1657
1658 /* Select the Capture Compare preload feature */
1659 htim->Instance->CR2 |= TIM_CR2_CCPC;
1660 /* Select the Commutation event source */
1661 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1662 htim->Instance->CR2 |= CommutationSource;
1663
1664 /* Enable the Commutation Interrupt Request */
1665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
1666
1667 __HAL_UNLOCK(htim);
1668
1669 return HAL_OK;
1670 }
1671
1672 /**
1673 * @brief Configure the TIM commutation event sequence with DMA.
1674 * @note: this function is mandatory to use the commutation event in order to
1675 * update the configuration at each commutation detection on the TRGI input of the Timer,
1676 * the typical use of this feature is with the use of another Timer(interface Timer)
1677 * configured in Hall sensor interface, this interface Timer will generate the
1678 * commutation at its TRGO output (connected to Timer used in this function) each time
1679 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1680 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
1681 * @param htim: TIM handle
1682 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1683 * This parameter can be one of the following values:
1684 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1685 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1686 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1687 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1688 * @arg TIM_TS_NONE: No trigger is needed
1689 * @param CommutationSource : the Commutation Event source
1690 * This parameter can be one of the following values:
1691 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1692 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1693 * @retval HAL status
1694 */
1695 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
1696 {
1697 /* Check the parameters */
1698 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1699 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1700
1701 __HAL_LOCK(htim);
1702
1703 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1704 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1705 {
1706 /* Select the Input trigger */
1707 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1708 htim->Instance->SMCR |= InputTrigger;
1709 }
1710
1711 /* Select the Capture Compare preload feature */
1712 htim->Instance->CR2 |= TIM_CR2_CCPC;
1713 /* Select the Commutation event source */
1714 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1715 htim->Instance->CR2 |= CommutationSource;
1716
1717 /* Enable the Commutation DMA Request */
1718 /* Set the DMA Commutation Callback */
1719 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
1720 /* Set the DMA error callback */
1721 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
1722
1723 /* Enable the Commutation DMA Request */
1724 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
1725
1726 __HAL_UNLOCK(htim);
1727
1728 return HAL_OK;
1729 }
1730
1731 /**
1732 * @brief Initializes the TIM Output Compare Channels according to the specified
1733 * parameters in the TIM_OC_InitTypeDef.
1734 * @param htim: TIM Output Compare handle
1735 * @param sConfig: TIM Output Compare configuration structure
1736 * @param Channel : TIM Channels to configure
1737 * This parameter can be one of the following values:
1738 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1739 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1740 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1741 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1742 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1743 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1744 * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
1745 * @retval HAL status
1746 */
1747 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
1748 TIM_OC_InitTypeDef* sConfig,
1749 uint32_t Channel)
1750 {
1751 /* Check the parameters */
1752 assert_param(IS_TIM_CHANNELS(Channel));
1753 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
1754 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
1755 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
1756 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
1757 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
1758
1759 /* Check input state */
1760 __HAL_LOCK(htim);
1761
1762 htim->State = HAL_TIM_STATE_BUSY;
1763
1764 switch (Channel)
1765 {
1766 case TIM_CHANNEL_1:
1767 {
1768 /* Check the parameters */
1769 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
1770
1771 /* Configure the TIM Channel 1 in Output Compare */
1772 TIM_OC1_SetConfig(htim->Instance, sConfig);
1773 }
1774 break;
1775
1776 case TIM_CHANNEL_2:
1777 {
1778 /* Check the parameters */
1779 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1780
1781 /* Configure the TIM Channel 2 in Output Compare */
1782 TIM_OC2_SetConfig(htim->Instance, sConfig);
1783 }
1784 break;
1785
1786 case TIM_CHANNEL_3:
1787 {
1788 /* Check the parameters */
1789 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
1790
1791 /* Configure the TIM Channel 3 in Output Compare */
1792 TIM_OC3_SetConfig(htim->Instance, sConfig);
1793 }
1794 break;
1795
1796 case TIM_CHANNEL_4:
1797 {
1798 /* Check the parameters */
1799 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
1800
1801 /* Configure the TIM Channel 4 in Output Compare */
1802 TIM_OC4_SetConfig(htim->Instance, sConfig);
1803 }
1804 break;
1805
1806 case TIM_CHANNEL_5:
1807 {
1808 /* Check the parameters */
1809 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
1810
1811 /* Configure the TIM Channel 5 in Output Compare */
1812 TIM_OC5_SetConfig(htim->Instance, sConfig);
1813 }
1814 break;
1815
1816 case TIM_CHANNEL_6:
1817 {
1818 /* Check the parameters */
1819 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
1820
1821 /* Configure the TIM Channel 6 in Output Compare */
1822 TIM_OC6_SetConfig(htim->Instance, sConfig);
1823 }
1824 break;
1825
1826 default:
1827 break;
1828 }
1829
1830 htim->State = HAL_TIM_STATE_READY;
1831
1832 __HAL_UNLOCK(htim);
1833
1834 return HAL_OK;
1835 }
1836
1837 /**
1838 * @brief Initializes the TIM PWM channels according to the specified
1839 * parameters in the TIM_OC_InitTypeDef.
1840 * @param htim: TIM PWM handle
1841 * @param sConfig: TIM PWM configuration structure
1842 * @param Channel : TIM Channels to be configured
1843 * This parameter can be one of the following values:
1844 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1845 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1846 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1847 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1848 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1849 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1850 * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
1851 * @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 PWM channels can
1852 * be configured
1853 * @retval HAL status
1854 */
1855 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
1856 TIM_OC_InitTypeDef* sConfig,
1857 uint32_t Channel)
1858 {
1859 /* Check the parameters */
1860 assert_param(IS_TIM_CHANNELS(Channel));
1861 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
1862 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
1863 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
1864 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
1865 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
1866 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
1867
1868 /* Check input state */
1869 __HAL_LOCK(htim);
1870
1871 htim->State = HAL_TIM_STATE_BUSY;
1872
1873 switch (Channel)
1874 {
1875 case TIM_CHANNEL_1:
1876 {
1877 /* Check the parameters */
1878 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
1879
1880 /* Configure the Channel 1 in PWM mode */
1881 TIM_OC1_SetConfig(htim->Instance, sConfig);
1882
1883 /* Set the Preload enable bit for channel1 */
1884 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
1885
1886 /* Configure the Output Fast mode */
1887 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
1888 htim->Instance->CCMR1 |= sConfig->OCFastMode;
1889 }
1890 break;
1891
1892 case TIM_CHANNEL_2:
1893 {
1894 /* Check the parameters */
1895 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
1896
1897 /* Configure the Channel 2 in PWM mode */
1898 TIM_OC2_SetConfig(htim->Instance, sConfig);
1899
1900 /* Set the Preload enable bit for channel2 */
1901 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
1902
1903 /* Configure the Output Fast mode */
1904 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
1905 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
1906 }
1907 break;
1908
1909 case TIM_CHANNEL_3:
1910 {
1911 /* Check the parameters */
1912 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
1913
1914 /* Configure the Channel 3 in PWM mode */
1915 TIM_OC3_SetConfig(htim->Instance, sConfig);
1916
1917 /* Set the Preload enable bit for channel3 */
1918 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
1919
1920 /* Configure the Output Fast mode */
1921 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
1922 htim->Instance->CCMR2 |= sConfig->OCFastMode;
1923 }
1924 break;
1925
1926 case TIM_CHANNEL_4:
1927 {
1928 /* Check the parameters */
1929 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
1930
1931 /* Configure the Channel 4 in PWM mode */
1932 TIM_OC4_SetConfig(htim->Instance, sConfig);
1933
1934 /* Set the Preload enable bit for channel4 */
1935 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
1936
1937 /* Configure the Output Fast mode */
1938 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
1939 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
1940 }
1941 break;
1942
1943 case TIM_CHANNEL_5:
1944 {
1945 /* Check the parameters */
1946 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
1947
1948 /* Configure the Channel 5 in PWM mode */
1949 TIM_OC5_SetConfig(htim->Instance, sConfig);
1950
1951 /* Set the Preload enable bit for channel5*/
1952 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
1953
1954 /* Configure the Output Fast mode */
1955 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
1956 htim->Instance->CCMR3 |= sConfig->OCFastMode;
1957 }
1958 break;
1959
1960 case TIM_CHANNEL_6:
1961 {
1962 /* Check the parameters */
1963 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
1964
1965 /* Configure the Channel 5 in PWM mode */
1966 TIM_OC6_SetConfig(htim->Instance, sConfig);
1967
1968 /* Set the Preload enable bit for channel6 */
1969 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
1970
1971 /* Configure the Output Fast mode */
1972 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
1973 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
1974 }
1975 break;
1976
1977 default:
1978 break;
1979 }
1980
1981 htim->State = HAL_TIM_STATE_READY;
1982
1983 __HAL_UNLOCK(htim);
1984
1985 return HAL_OK;
1986 }
1987
1988 /**
1989 * @brief Configures the OCRef clear feature
1990 * @param htim: TIM handle
1991 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
1992 * contains the OCREF clear feature and parameters for the TIM peripheral.
1993 * @param Channel: specifies the TIM Channel
1994 * This parameter can be one of the following values:
1995 * @arg TIM_Channel_1: TIM Channel 1
1996 * @arg TIM_Channel_2: TIM Channel 2
1997 * @arg TIM_Channel_3: TIM Channel 3
1998 * @arg TIM_Channel_4: TIM Channel 4
1999 * @arg TIM_Channel_5: TIM Channel 5
2000 * @arg TIM_Channel_6: TIM Channel 6
2001 * @note For STM32F302xC, STM32F303xC, STM32F358xx and STM32F303x8 up to 6 OC channels can
2002 * be configured
2003 * @retval None
2004 */
2005 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
2006 TIM_ClearInputConfigTypeDef *sClearInputConfig,
2007 uint32_t Channel)
2008 {
2009 uint32_t tmpsmcr = 0;
2010
2011 /* Check the parameters */
2012 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
2013 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
2014
2015 /* Check input state */
2016 __HAL_LOCK(htim);
2017
2018 switch (sClearInputConfig->ClearInputSource)
2019 {
2020 case TIM_CLEARINPUTSOURCE_NONE:
2021 {
2022 /* Clear the OCREF clear selection bit */
2023 tmpsmcr &= ~TIM_SMCR_OCCS;
2024
2025 /* Clear the ETR Bits */
2026 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
2027
2028 /* Set TIMx_SMCR */
2029 htim->Instance->SMCR = tmpsmcr;
2030 }
2031 break;
2032
2033 case TIM_CLEARINPUTSOURCE_OCREFCLR:
2034 {
2035 /* Clear the OCREF clear selection bit */
2036 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
2037 }
2038 break;
2039
2040 case TIM_CLEARINPUTSOURCE_ETR:
2041 {
2042 /* Check the parameters */
2043 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
2044 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
2045 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
2046
2047 TIM_ETR_SetConfig(htim->Instance,
2048 sClearInputConfig->ClearInputPrescaler,
2049 sClearInputConfig->ClearInputPolarity,
2050 sClearInputConfig->ClearInputFilter);
2051
2052 /* Set the OCREF clear selection bit */
2053 htim->Instance->SMCR |= TIM_SMCR_OCCS;
2054 }
2055 break;
2056 }
2057
2058 switch (Channel)
2059 {
2060 case TIM_CHANNEL_1:
2061 {
2062 if(sClearInputConfig->ClearInputState != RESET)
2063 {
2064 /* Enable the Ocref clear feature for Channel 1 */
2065 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
2066 }
2067 else
2068 {
2069 /* Disable the Ocref clear feature for Channel 1 */
2070 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
2071 }
2072 }
2073 break;
2074 case TIM_CHANNEL_2:
2075 {
2076 if(sClearInputConfig->ClearInputState != RESET)
2077 {
2078 /* Enable the Ocref clear feature for Channel 2 */
2079 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
2080 }
2081 else
2082 {
2083 /* Disable the Ocref clear feature for Channel 2 */
2084 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
2085 }
2086 }
2087 break;
2088 case TIM_CHANNEL_3:
2089 {
2090 if(sClearInputConfig->ClearInputState != RESET)
2091 {
2092 /* Enable the Ocref clear feature for Channel 3 */
2093 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
2094 }
2095 else
2096 {
2097 /* Disable the Ocref clear feature for Channel 3 */
2098 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
2099 }
2100 }
2101 break;
2102 case TIM_CHANNEL_4:
2103 {
2104 if(sClearInputConfig->ClearInputState != RESET)
2105 {
2106 /* Enable the Ocref clear feature for Channel 4 */
2107 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
2108 }
2109 else
2110 {
2111 /* Disable the Ocref clear feature for Channel 4 */
2112 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
2113 }
2114 }
2115 break;
2116 case TIM_CHANNEL_5:
2117 {
2118 if(sClearInputConfig->ClearInputState != RESET)
2119 {
2120 /* Enable the Ocref clear feature for Channel 1 */
2121 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
2122 }
2123 else
2124 {
2125 /* Disable the Ocref clear feature for Channel 1 */
2126 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
2127 }
2128 }
2129 break;
2130 case TIM_CHANNEL_6:
2131 {
2132 if(sClearInputConfig->ClearInputState != RESET)
2133 {
2134 /* Enable the Ocref clear feature for Channel 1 */
2135 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
2136 }
2137 else
2138 {
2139 /* Disable the Ocref clear feature for Channel 1 */
2140 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
2141 }
2142 }
2143 break;
2144 default:
2145 break;
2146 }
2147
2148 __HAL_UNLOCK(htim);
2149
2150 return HAL_OK;
2151 }
2152
2153 /**
2154 * @brief Configures the TIM in master mode.
2155 * @param htim: TIM handle.
2156 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
2157 * contains the selected trigger output (TRGO) and the Master/Slave
2158 * mode.
2159 * @retval HAL status
2160 */
2161 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2162 TIM_MasterConfigTypeDef * sMasterConfig)
2163 {
2164 uint32_t tmpcr2;
2165 uint32_t tmpsmcr;
2166
2167 /* Check the parameters */
2168 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
2169 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2170 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2171
2172 /* Check input state */
2173 __HAL_LOCK(htim);
2174
2175 /* Get the TIMx CR2 register value */
2176 tmpcr2 = htim->Instance->CR2;
2177
2178 /* Get the TIMx SMCR register value */
2179 tmpsmcr = htim->Instance->SMCR;
2180
2181 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2182 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2183 {
2184 /* Check the parameters */
2185 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2186
2187 /* Clear the MMS2 bits */
2188 tmpcr2 &= ~TIM_CR2_MMS2;
2189 /* Select the TRGO2 source*/
2190 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2191 }
2192
2193 /* Reset the MMS Bits */
2194 tmpcr2 &= ~TIM_CR2_MMS;
2195 /* Select the TRGO source */
2196 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2197
2198 /* Reset the MSM Bit */
2199 tmpsmcr &= ~TIM_SMCR_MSM;
2200 /* Set master mode */
2201 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2202
2203 /* Update TIMx CR2 */
2204 htim->Instance->CR2 = tmpcr2;
2205
2206 /* Update TIMx SMCR */
2207 htim->Instance->SMCR = tmpsmcr;
2208
2209 __HAL_UNLOCK(htim);
2210
2211 return HAL_OK;
2212 }
2213 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2214 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2215 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2216 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2217
2218 #if defined(STM32F373xC) || defined(STM32F378xx)
2219 /**
2220 * @brief Configures the TIM in master mode.
2221 * @param htim: TIM handle.
2222 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
2223 * contains the selected trigger output (TRGO) and the Master/Slave
2224 * mode.
2225 * @retval HAL status
2226 */
2227 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
2228 {
2229 /* Check the parameters */
2230 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2231 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2232 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2233
2234 __HAL_LOCK(htim);
2235
2236 htim->State = HAL_TIM_STATE_BUSY;
2237
2238 /* Reset the MMS Bits */
2239 htim->Instance->CR2 &= ~TIM_CR2_MMS;
2240 /* Select the TRGO source */
2241 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
2242
2243 /* Reset the MSM Bit */
2244 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
2245 /* Set or Reset the MSM Bit */
2246 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
2247
2248 htim->State = HAL_TIM_STATE_READY;
2249
2250 __HAL_UNLOCK(htim);
2251
2252 return HAL_OK;
2253 }
2254 #endif /* STM32F373xC || STM32F378xx */
2255
2256 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2257 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2258 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2259 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2260 /**
2261 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2262 * and the AOE(automatic output enable).
2263 * @param htim: TIM handle
2264 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2265 * contains the BDTR Register configuration information for the TIM peripheral.
2266 * @note For STM32F302xC, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx and STM32F303x8 two break inputs can be configured.
2267 * @retval HAL status
2268 */
2269 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2270 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
2271 {
2272 uint32_t tmpbdtr = 0;
2273
2274 /* Check the parameters */
2275 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2276 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2277 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2278 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2279 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2280 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2281 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2282 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2283 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2284
2285 /* Check input state */
2286 __HAL_LOCK(htim);
2287
2288 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2289 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2290 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2291 {
2292 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2293 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2294 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2295
2296 /* Clear the BDTR bits */
2297 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
2298 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
2299 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
2300 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
2301
2302 /* Set the BDTR bits */
2303 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
2304 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
2305 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
2306 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
2307 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
2308 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
2309 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
2310 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
2311 tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
2312 tmpbdtr |= sBreakDeadTimeConfig->Break2State;
2313 tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
2314 }
2315 else
2316 {
2317 /* Clear the BDTR bits */
2318 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
2319 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
2320 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
2321
2322 /* Set the BDTR bits */
2323 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
2324 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
2325 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
2326 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
2327 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
2328 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
2329 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
2330 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
2331 }
2332
2333 /* Set TIMx_BDTR */
2334 htim->Instance->BDTR = tmpbdtr;
2335
2336 __HAL_UNLOCK(htim);
2337
2338 return HAL_OK;
2339 }
2340 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2341 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2342 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2343 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2344
2345 #if defined(STM32F373xC) || defined(STM32F378xx)
2346 /**
2347 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2348 * and the AOE(automatic output enable).
2349 * @param htim: TIM handle
2350 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2351 * contains the BDTR Register configuration information for the TIM peripheral.
2352 * @retval HAL status
2353 */
2354 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2355 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2356 {
2357 /* Check the parameters */
2358 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2359 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2360 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2361 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2362 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2363 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2364 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2365 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2366
2367 /* Process Locked */
2368 __HAL_LOCK(htim);
2369
2370 htim->State = HAL_TIM_STATE_BUSY;
2371
2372 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2373 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2374 htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
2375 sBreakDeadTimeConfig->OffStateIDLEMode |
2376 sBreakDeadTimeConfig->LockLevel |
2377 sBreakDeadTimeConfig->DeadTime |
2378 sBreakDeadTimeConfig->BreakState |
2379 sBreakDeadTimeConfig->BreakPolarity |
2380 sBreakDeadTimeConfig->AutomaticOutput;
2381
2382
2383 htim->State = HAL_TIM_STATE_READY;
2384
2385 __HAL_UNLOCK(htim);
2386
2387 return HAL_OK;
2388 }
2389 #endif /* STM32F373xC || STM32F378xx */
2390
2391 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2392 defined(STM32F303xC) || defined(STM32F358xx)
2393 #if defined(STM32F303xE) || defined(STM32F398xx)
2394 /**
2395 * @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
2396 * @param htim: TIM handle.
2397 * @param Remap1: specifies the first TIM remapping source.
2398 * This parameter can be one of the following values:
2399 * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
2400 * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2401 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2402 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2403 * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
2404 * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
2405 * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
2406 * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
2407 * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
2408 * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
2409 * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
2410 * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
2411 * @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
2412 * @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
2413 * @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
2414 * @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
2415 * @param Remap2: specifies the second TIMremapping source (if any).
2416 * This parameter can be one of the following values:
2417 * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
2418 * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
2419 * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
2420 * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
2421 * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
2422 * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
2423 * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
2424 * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
2425 * @arg TIM_TIM16_NONE: Non significant value for TIM16
2426 * @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
2427 * @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
2428 * @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
2429 * @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
2430 * @retval HAL status
2431 */
2432 #else /* STM32F303xC || STM32F358xx */
2433 /**
2434 * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
2435 * @param htim: TIM handle.
2436 * @param Remap1: specifies the first TIM remapping source.
2437 * This parameter can be one of the following values:
2438 * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
2439 * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2440 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2441 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2442 * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
2443 * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
2444 * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
2445 * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
2446 * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
2447 * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
2448 * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
2449 * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
2450 * @param Remap2: specifies the second TIMremapping source (if any).
2451 * This parameter can be one of the following values:
2452 * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
2453 * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
2454 * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
2455 * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
2456 * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
2457 * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
2458 * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
2459 * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
2460 * @retval HAL status
2461 */
2462 #endif /* STM32F303xE || STM32F398xx || */
2463 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
2464 {
2465 __HAL_LOCK(htim);
2466
2467 /* Check parameters */
2468 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2469 assert_param(IS_TIM_REMAP(Remap1));
2470 assert_param(IS_TIM_REMAP2(Remap2));
2471
2472 /* Set the Timer remapping configuration */
2473 htim->Instance->OR = Remap1 | Remap2;
2474
2475 htim->State = HAL_TIM_STATE_READY;
2476
2477 __HAL_UNLOCK(htim);
2478
2479 return HAL_OK;
2480 }
2481 #endif /* STM32F303xE || STM32F398xx || */
2482 /* STM32F303xC || STM32F358xx || */
2483
2484
2485 #if defined(STM32F302xE) || \
2486 defined(STM32F302xC) || \
2487 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2488 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
2489 defined(STM32F373xC) || defined(STM32F378xx)
2490 #if defined(STM32F302xE) || \
2491 defined(STM32F302xC) || \
2492 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2493 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2494 /**
2495 * @brief Configures the TIM1 and TIM16 Remapping input capabilities.
2496 * @param htim: TIM handle.
2497 * @param Remap: specifies the TIM remapping source.
2498 * This parameter can be one of the following values:
2499 * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
2500 * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
2501 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
2502 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
2503 * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
2504 * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
2505 * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
2506 * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
2507 * @retval HAL status
2508 */
2509 #else /* STM32F373xC || STM32F378xx */
2510 /**
2511 * @brief Configures the TIM2 and TIM14 Remapping input capabilities.
2512 * @param htim: TIM handle.
2513 * @param Remap: specifies the TIM remapping source.
2514 * This parameter can be one of the following values:
2515 * STM32F373xC, STM32F378xx:
2516 * @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
2517 * @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
2518 * @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
2519 * @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
2520 * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
2521 * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
2522 * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
2523 * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
2524 * @retval HAL status
2525 */
2526 #endif /* STM32F302xE || */
2527 /* STM32F302xC || */
2528 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2529 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
2530 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2531 {
2532 __HAL_LOCK(htim);
2533
2534 /* Check parameters */
2535 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2536 assert_param(IS_TIM_REMAP(Remap));
2537
2538 /* Set the Timer remapping configuration */
2539 htim->Instance->OR = Remap;
2540
2541 htim->State = HAL_TIM_STATE_READY;
2542
2543 __HAL_UNLOCK(htim);
2544
2545 return HAL_OK;
2546 }
2547 #endif /* STM32F302xE || */
2548 /* STM32F302xC || */
2549 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2550 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
2551 /* STM32F373xC || STM32F378xx */
2552
2553
2554 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2555 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2556 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2557 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2558 /**
2559 * @brief Group channel 5 and channel 1, 2 or 3
2560 * @param htim: TIM handle.
2561 * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
2562 * This parameter can be any combination of the following values:
2563 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2564 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2565 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2566 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2567 * @retval HAL status
2568 */
2569 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
2570 {
2571 /* Check parameters */
2572 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2573 assert_param(IS_TIM_GROUPCH5(OCRef));
2574
2575 /* Process Locked */
2576 __HAL_LOCK(htim);
2577
2578 htim->State = HAL_TIM_STATE_BUSY;
2579
2580 /* Clear GC5Cx bit fields */
2581 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
2582
2583 /* Set GC5Cx bit fields */
2584 htim->Instance->CCR5 |= OCRef;
2585
2586 htim->State = HAL_TIM_STATE_READY;
2587
2588 __HAL_UNLOCK(htim);
2589
2590 return HAL_OK;
2591 }
2592 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2593 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2594 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2595 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2596
2597 /**
2598 * @}
2599 */
2600
2601 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2602 * @brief Extended Callbacks functions
2603 *
2604 @verbatim
2605 ==============================================================================
2606 ##### Extended Callbacks functions #####
2607 ==============================================================================
2608 [..]
2609 This section provides Extended TIM callback functions:
2610 (+) Timer Commutation callback
2611 (+) Timer Break callback
2612
2613 @endverbatim
2614 * @{
2615 */
2616
2617 /**
2618 * @brief Hall commutation changed callback in non blocking mode
2619 * @param htim : TIM handle
2620 * @retval None
2621 */
2622 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
2623 {
2624 /* NOTE : This function Should not be modified, when the callback is needed,
2625 the HAL_TIMEx_CommutationCallback could be implemented in the user file
2626 */
2627 }
2628
2629 /**
2630 * @brief Hall Break detection callback in non blocking mode
2631 * @param htim : TIM handle
2632 * @retval None
2633 */
2634 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
2635 {
2636 /* NOTE : This function Should not be modified, when the callback is needed,
2637 the HAL_TIMEx_BreakCallback could be implemented in the user file
2638 */
2639 }
2640
2641 /**
2642 * @}
2643 */
2644
2645 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
2646 * @brief Extended Peripheral State functions
2647 *
2648 @verbatim
2649 ==============================================================================
2650 ##### Extended Peripheral State functions #####
2651 ==============================================================================
2652 [..]
2653 This subsection permit to get in run-time the status of the peripheral
2654 and the data flow.
2655
2656 @endverbatim
2657 * @{
2658 */
2659
2660 /**
2661 * @brief Return the TIM Hall Sensor interface state
2662 * @param htim: TIM Hall Sensor handle
2663 * @retval HAL state
2664 */
2665 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
2666 {
2667 return htim->State;
2668 }
2669
2670 /**
2671 * @}
2672 */
2673
2674 /**
2675 * @brief TIM DMA Commutation callback.
2676 * @param hdma : pointer to DMA handle.
2677 * @retval None
2678 */
2679 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
2680 {
2681 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2682
2683 htim->State= HAL_TIM_STATE_READY;
2684
2685 HAL_TIMEx_CommutationCallback(htim);
2686 }
2687
2688 /**
2689 * @brief Enables or disables the TIM Capture Compare Channel xN.
2690 * @param TIMx to select the TIM peripheral
2691 * @param Channel: specifies the TIM Channel
2692 * This parameter can be one of the following values:
2693 * @arg TIM_Channel_1: TIM Channel 1
2694 * @arg TIM_Channel_2: TIM Channel 2
2695 * @arg TIM_Channel_3: TIM Channel 3
2696 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
2697 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
2698 * @retval None
2699 */
2700 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
2701 {
2702 uint32_t tmp = 0;
2703
2704 tmp = TIM_CCER_CC1NE << Channel;
2705
2706 /* Reset the CCxNE Bit */
2707 TIMx->CCER &= ~tmp;
2708
2709 /* Set or reset the CCxNE Bit */
2710 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
2711 }
2712
2713 /**
2714 * @}
2715 */
2716
2717 #endif /* HAL_TIM_MODULE_ENABLED */
2718 /**
2719 * @}
2720 */
2721
2722 /**
2723 * @}
2724 */
2725
2726 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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