]> git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.h
git://git.gir.st / tmk_keyboard.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3XX / stm32f30x_hrtim.h
1 /**
2 ******************************************************************************
3 * @file stm32f30x_hrtim.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 27-February-2014
7 * @brief This file contains all the functions prototypes for the HRTIM firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 *
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef __STM32F30x_HRTIM_H
41 #define __STM32F30x_HRTIM_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f30x.h"
49
50 /** @addtogroup STM32F30x_StdPeriph_Driver
51 * @{
52 */
53
54 /** @addtogroup ADC
55 * @{
56 */
57
58 /* Exported types ------------------------------------------------------------*/
59
60 /**
61 * @brief HRTIM Configuration Structure definition - Time base related parameters
62 */
63 typedef struct
64 {
65 uint32_t Period; /*!< Specifies the timer period
66 The period value must be above 3 periods of the fHRTIM clock.
67 Maximum value is = 0xFFDF */
68 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
69 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
70 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
71 This parameter can be any value of @ref HRTIM_PrescalerRatio */
72 uint32_t Mode; /*!< Specifies the counter operating mode
73 This parameter can be any value of @ref HRTIM_Mode */
74 } HRTIM_BaseInitTypeDef;
75 /**
76 * @brief Waveform mode initialization parameters definition
77 */
78 typedef struct {
79 uint32_t HalfModeEnable; /*!< Specifies whether or not half mode is enabled
80 This parameter can be a combination of @ref HRTIM_HalfModeEnable */
81 uint32_t StartOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
82 This parameter can be a combination of @ref HRTIM_StartOnSyncInputEvent */
83 uint32_t ResetOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
84 This parameter can be a combination of @ref HRTIM_ResetOnSyncInputEvent */
85 uint32_t DACSynchro; /*!< Indicates whether or not the a DAC synchronization event is generated
86 This parameter can be any value of @ref HRTIM_DACSynchronization */
87 uint32_t PreloadEnable; /*!< Specifies whether or not register preload is enabled
88 This parameter can be a combination of @ref HRTIM_RegisterPreloadEnable */
89 uint32_t UpdateGating; /*!< Specifies how the update occurs with respect to a burst DMA transaction or
90 update enable inputs (Slave timers only)
91 This parameter can be any value of @ref HRTIM_UpdateGating */
92 uint32_t BurstMode; /*!< Specifies how the timer behaves during a burst mode operation
93 This parameter can be a combination of @ref HRTIM_TimerBurstMode */
94 uint32_t RepetitionUpdate; /*!< Specifies whether or not registers update is triggered by the repetition event
95 This parameter can be a combination of @ref HRTIM_TimerRepetitionUpdate */
96 } HRTIM_TimerInitTypeDef;
97
98 /**
99 * @brief Basic output compare mode configuration definition
100 */
101 typedef struct {
102 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
103 This parameter can be a combination of @ref HRTIM_BasicOCMode */
104 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
105 The compare value must be above or equal to 3 periods of the fHRTIM clock */
106 uint32_t Polarity; /*!< Specifies the output polarity
107 This parameter can be any value of @ref HRTIM_Output_Polarity */
108 uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
109 This parameter can be any value of @ref HRTIM_OutputIDLEState */
110 } HRTIM_BasicOCChannelCfgTypeDef;
111
112 /**
113 * @brief Basic PWM output mode configuration definition
114 */
115 typedef struct {
116 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
117 The compare value must be above or equal to 3 periods of the fHRTIM clock */
118 uint32_t Polarity; /*!< Specifies the output polarity
119 This parameter can be any value of @ref HRTIM_OutputPolarity */
120 uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
121 This parameter can be any value of @ref HRTIM_OutputIDLEState */
122 } HRTIM_BasicPWMChannelCfgTypeDef;
123
124 /**
125 * @brief Basic capture mode configuration definition
126 */
127 typedef struct {
128 uint32_t CaptureUnit; /*!< Specifies the external event Channel
129 This parameter can be any 'EEVx' value of @ref HRTIM_CaptureUnit */
130 uint32_t Event; /*!< Specifies the external event triggering the capture
131 This parameter can be any 'EEVx' value of @ref HRTIM_ExternalEventChannels */
132 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
133 This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
134 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
135 This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
136 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
137 This parameter can be a value of @ref HRTIM_ExternalEventFilter */
138 } HRTIM_BasicCaptureChannelCfgTypeDef;
139
140 /**
141 * @brief Basic One Pulse mode configuration definition
142 */
143 typedef struct {
144 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
145 The compare value must be above or equal to 3 periods of the fHRTIM clock */
146 uint32_t OutputPolarity; /*!< Specifies the output polarity
147 This parameter can be any value of @ref HRTIM_Output_Polarity */
148 uint32_t OutputIdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
149 This parameter can be any value of @ref HRTIM_Output_IDLE_State */
150 uint32_t Event; /*!< Specifies the external event triggering the pulse generation
151 This parameter can be any 'EEVx' value of @ref HRTIM_Capture_Unit_Trigger */
152 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
153 This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
154 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
155 This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
156 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
157 This parameter can be a value of @ref HRTIM_ExternalEventFilter */
158 } HRTIM_BasicOnePulseChannelCfgTypeDef;
159
160 /**
161 * @brief Timer configuration definition
162 */
163 typedef struct {
164 uint32_t PushPull; /*!< Specifies whether or not the push-pull mode is enabled
165 This parameter can be a value of @ref HRTIM_TimerPushPullMode */
166 uint32_t FaultEnable; /*!< Specifies which fault channels are enabled for the timer
167 This parameter can be a combination of @ref HRTIM_TimerFaultEnabling */
168 uint32_t FaultLock; /*!< Specifies whether or not fault enabling status is write protected
169 This parameter can be a value of @ref HRTIM_TimerFaultLock */
170 uint32_t DeadTimeInsertion; /*!< Specifies whether or not dead time insertion is enabled for the timer
171 This parameter can be a value of @ref HRTIM_TimerDeadtimeInsertion */
172 uint32_t DelayedProtectionMode; /*!< Specifies the delayed protection mode
173 This parameter can be a value of @ref HRTIM_TimerDelayedProtectionMode */
174 uint32_t UpdateTrigger; /*!< Specifies source(s) triggering the timer registers update
175 This parameter can be a combination of @ref HRTIM_TimerUpdateTrigger */
176 uint32_t ResetTrigger; /*!< Specifies source(s) triggering the timer counter reset
177 This parameter can be a combination of @ref HRTIM_TimerResetTrigger */
178 uint32_t ResetUpdate; /*!< Specifies whether or not registers update is triggered when the timer counter is reset
179 This parameter can be a combination of @ref HRTIM_TimerResetUpdate */
180 } HRTIM_TimerCfgTypeDef;
181
182 /**
183 * @brief Compare unit configuration definition
184 */
185 typedef struct {
186 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
187 the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
188 the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
189 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
190 This parameter can be a value of @ref HRTIM_CompareUnitAutoDelayedMode */
191 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
192 CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
193 } HRTIM_CompareCfgTypeDef;
194
195 /**
196 * @brief Capture unit configuration definition
197 */
198 typedef struct {
199 uint32_t Trigger; /*!< Specifies source(s) triggering the capture
200 This parameter can be a combination of @ref HRTIM_CaptureUnitTrigger */
201 } HRTIM_CaptureCfgTypeDef;
202
203 /**
204 * @brief Output configuration definition
205 */
206 typedef struct {
207 uint32_t Polarity; /*!< Specifies the output polarity
208 This parameter can be any value of @ref HRTIM_Output_Polarity */
209 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
210 This parameter can be any value of @ref HRTIM_OutputSetSource */
211 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
212 This parameter can be any value of @ref HRTIM_OutputResetSource */
213 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
214 This parameter can be any value of @ref HRTIM_OutputIdleMode */
215 uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
216 This parameter can be any value of @ref HRTIM_OutputIDLEState */
217 uint32_t FaultState; /*!< Specifies whether the output level is active or inactive when in FAULT state
218 This parameter can be any value of @ref HRTIM_OutputFAULTState */
219 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
220 This parameter can be any value of @ref HRTIM_OutputChopperModeEnable */
221 uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
222 during a burst mode operation
223 This parameters can be any value of @ref HRTIM_OutputBurstModeEntryDelayed */
224 } HRTIM_OutputCfgTypeDef;
225
226 /**
227 * @brief External event filtering in timing units configuration definition
228 */
229 typedef struct {
230 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit
231 This parameter can be a value of @ref HRTIM_TimerExternalEventFilter */
232 uint32_t Latch; /*!< Specifies whether or not the signal is latched
233 This parameter can be a value of @ref HRTIM_TimerExternalEventLatch */
234 } HRTIM_TimerEventFilteringCfgTypeDef;
235
236 /**
237 * @brief Dead time feature configuration definition
238 */
239 typedef struct {
240 uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler
241 This parameter can be a number between 0x0 and = 0x7 */
242 uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge
243 This parameter can be a number between 0x0 and 0xFF */
244 uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge
245 This parameter can be a value of @ref HRTIM_DeadtimeRisingSign */
246 uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
247 This parameter can be a value of @ref HRTIM_DeadtimeRisingLock */
248 uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected
249 This parameter can be a value of @ref HRTIM_DeadtimeRisingSignLock */
250 uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge
251 This parameter can be a number between 0x0 and 0xFF */
252 uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge
253 This parameter can be a value of @ref HRTIM_DeadtimeFallingSign */
254 uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
255 This parameter can be a value of @ref HRTIM_DeadtimeFallingLock */
256 uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected
257 This parameter can be a value of @ref HRTIM_DeadtimeFallingSignLock */
258 } HRTIM_DeadTimeCfgTypeDef;
259
260 /**
261 * @brief Chopper mode configuration definition
262 */
263 typedef struct {
264 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
265 This parameter can be a value between 0 and 0xF */
266 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
267 This parameter can be a value between 0 and 0x7 */
268 uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
269 This parameter can be a value between 0 and 0xF */
270 } HRTIM_ChopperModeCfgTypeDef;
271
272 /**
273 * @brief Master synchronization configuration definition
274 */
275 typedef struct {
276 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
277 This parameter can be a value of @ref HRTIM_SynchronizationInputSource */
278 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
279 This parameter can be a value of @ref HRTIM_SynchronizationOutputSource */
280 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization outputs
281 This parameter can be a value of @ref HRTIM_SynchronizationOutputPolarity */
282 } HRTIM_SynchroCfgTypeDef;
283
284 /**
285 * @brief External event channel configuration definition
286 */
287 typedef struct {
288 uint32_t Source; /*!< Identifies the source of the external event
289 This parameter can be a value of @ref HRTIM_ExternalEventSources */
290 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
291 This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
292 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event
293 This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
294 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
295 This parameter can be a value of @ref HRTIM_ExternalEventFilter */
296 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event
297 This parameter can be a value of @ref HRTIM_ExternalEventFastMode */
298 } HRTIM_EventCfgTypeDef;
299
300 /**
301 * @brief Fault channel configuration definition
302 */
303 typedef struct {
304 uint32_t Source; /*!< Identifies the source of the fault
305 This parameter can be a value of @ref HRTIM_FaultSources */
306 uint32_t Polarity; /*!< Specifies the polarity of the fault event
307 This parameter can be a value of @ref HRTIM_FaultPolarity */
308 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
309 This parameter can be a value of @ref HRTIM_FaultFilter */
310 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected
311 This parameter can be a value of @ref HRTIM_FaultLock */
312 } HRTIM_FaultCfgTypeDef;
313
314 /**
315 * @brief Burst mode configuration definition
316 */
317 typedef struct {
318 uint32_t Mode; /*!< Specifies the burst mode operating mode
319 This parameter can be a value of @ref HRTIM_BurstModeOperatingMode */
320 uint32_t ClockSource; /*!< Specifies the burst mode clock source
321 This parameter can be a value of @ref HRTIM_BurstModeClockSource */
322 uint32_t Prescaler; /*!< Specifies the burst mode prescaler
323 This parameter can be a value of @ref HRTIM_BurstModePrescaler */
324 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
325 This parameter can be a combination of @ref HRTIM_BurstModeRegisterPreloadEnable */
326 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation
327 This parameter can be a combination of @ref HRTIM_BurstModeTrigger */
328 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state
329 This parameter can be a number between 0x0 and 0xFFFF */
330 uint32_t Period; /*!< Specifies burst mode repetition period
331 This parameter can be a number between 0x1 and 0xFFFF */
332 } HRTIM_BurstModeCfgTypeDef;
333
334 /**
335 * @brief ADC trigger configuration definition
336 */
337 typedef struct {
338 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source
339 This parameter can be a combination of @ref HRTIM_ADCTriggerUpdateSource */
340 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion
341 This parameter can be a combination of @ref HRTIM_ADCTriggerEvent */
342 } HRTIM_ADCTriggerCfgTypeDef;
343
344
345 /* Exported constants --------------------------------------------------------*/
346 /** @defgroup HRTIM_Exported_Constants
347 * @{
348 */
349
350 /** @defgroup HRTIM_TimerIndex
351 * @{
352 * @brief Constants defining the timer indexes
353 */
354 #define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index associated to timer A */
355 #define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index associated to timer B */
356 #define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index associated to timer C */
357 #define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index associated to timer D */
358 #define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index associated to timer E */
359 #define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index associated to master timer */
360 #define HRTIM_COMMONINDEX (uint32_t)0x6 /*!< Index associated to Common space */
361
362 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
363 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
364 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
365 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
366 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
367 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
368 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
369
370 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
371 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
372 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
373 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
374 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
375 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
376 /**
377 * @}
378 */
379
380 /** @defgroup HRTIM_TimerIdentifier
381 * @{
382 * @brief Constants defining timer identifiers
383 */
384 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
385 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
386 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
387 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
388 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
389 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
390
391 #define IS_HRTIM_TIMERID(TIMERID)\
392 (((TIMERID) == HRTIM_TIMERID_MASTER) || \
393 ((TIMERID) == HRTIM_TIMERID_TIMER_A) || \
394 ((TIMERID) == HRTIM_TIMERID_TIMER_B) || \
395 ((TIMERID) == HRTIM_TIMERID_TIMER_C) || \
396 ((TIMERID) == HRTIM_TIMERID_TIMER_D) || \
397 ((TIMERID) == HRTIM_TIMERID_TIMER_E))
398 /**
399 * @}
400 */
401
402 /** @defgroup HRTIM_CompareUnit
403 * @{
404 * @brief Constants defining compare unit identifiers
405 */
406 #define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */
407 #define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */
408 #define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */
409 #define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */
410
411 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
412 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
413 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
414 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
415 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
416 /**
417 * @}
418 */
419
420 /** @defgroup HRTIM_CaptureUnit
421 * @{
422 * @brief Constants defining capture unit identifiers
423 */
424 #define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */
425 #define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */
426
427 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
428 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
429 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
430 /**
431 * @}
432 */
433
434 /** @defgroup HRTIM_TimerOutput
435 * @{
436 * @brief Constants defining timer output identifiers
437 */
438 #define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Ouput 1 identifier */
439 #define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Ouput 2 identifier */
440 #define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Ouput 1 identifier */
441 #define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Ouput 2 identifier */
442 #define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Ouput 1 identifier */
443 #define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Ouput 2 identifier */
444 #define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Ouput 1 identifier */
445 #define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Ouput 2 identifier */
446 #define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Ouput 1 identifier */
447 #define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Ouput 2 identifier */
448
449 #define IS_HRTIM_OUTPUT(OUTPUT)\
450 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
451 ((OUTPUT) == HRTIM_OUTPUT_TA2) || \
452 ((OUTPUT) == HRTIM_OUTPUT_TB1) || \
453 ((OUTPUT) == HRTIM_OUTPUT_TB2) || \
454 ((OUTPUT) == HRTIM_OUTPUT_TC1) || \
455 ((OUTPUT) == HRTIM_OUTPUT_TC2) || \
456 ((OUTPUT) == HRTIM_OUTPUT_TD1) || \
457 ((OUTPUT) == HRTIM_OUTPUT_TD2) || \
458 ((OUTPUT) == HRTIM_OUTPUT_TE1) || \
459 ((OUTPUT) == HRTIM_OUTPUT_TE2))
460
461 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
462 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
463 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
464 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
465 || \
466 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
467 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
468 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
469 || \
470 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
471 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
472 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
473 || \
474 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
475 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
476 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
477 || \
478 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
479 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
480 ((OUTPUT) == HRTIM_OUTPUT_TE2))))
481 /**
482 * @}
483 */
484
485 /** @defgroup HRTIM_ADCTrigger
486 * @{
487 * @brief Constants defining ADC triggers identifiers
488 */
489 #define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */
490 #define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 1 identifier */
491 #define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 1 identifier */
492 #define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 1 identifier */
493
494 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
495 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
496 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
497 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
498 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
499 /**
500 * @}
501 */
502
503 /** @defgroup HRTIM_ExternalEventChannels
504 * @{
505 * @brief Constants defining external event channel identifiers
506 */
507 #define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */
508 #define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */
509 #define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */
510 #define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */
511 #define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */
512 #define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */
513 #define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */
514 #define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */
515 #define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */
516 #define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */
517 #define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */
518
519 #define IS_HRTIM_EVENT(EVENT)\
520 (((EVENT) == HRTIM_EVENT_1) || \
521 ((EVENT) == HRTIM_EVENT_2) || \
522 ((EVENT) == HRTIM_EVENT_3) || \
523 ((EVENT) == HRTIM_EVENT_4) || \
524 ((EVENT) == HRTIM_EVENT_5) || \
525 ((EVENT) == HRTIM_EVENT_6) || \
526 ((EVENT) == HRTIM_EVENT_7) || \
527 ((EVENT) == HRTIM_EVENT_8) || \
528 ((EVENT) == HRTIM_EVENT_9) || \
529 ((EVENT) == HRTIM_EVENT_10))
530 /**
531 * @}
532 */
533
534 /** @defgroup HRTIM_FaultChannel
535 * @{
536 * @brief Constants defining fault channel identifiers
537 */
538 #define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */
539 #define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */
540 #define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */
541 #define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */
542 #define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */
543
544 #define IS_HRTIM_FAULT(FAULT)\
545 (((FAULT) == HRTIM_FAULT_1) || \
546 ((FAULT) == HRTIM_FAULT_2) || \
547 ((FAULT) == HRTIM_FAULT_3) || \
548 ((FAULT) == HRTIM_FAULT_4) || \
549 ((FAULT) == HRTIM_FAULT_5))
550 /**
551 * @}
552 */
553
554
555 /** @defgroup HRTIM_PrescalerRatio
556 * @{
557 * @brief Constants defining timer high-resolution clock prescaler ratio.
558 */
559 #define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
560 #define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
561 #define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
562 #define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
563 #define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
564 #define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
565 #define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
566 #define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
567
568 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
569 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
570 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
571 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
572 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
573 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
574 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
575 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
576 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
577 /**
578 * @}
579 */
580
581 /** @defgroup HRTIM_Mode
582 * @{
583 * @brief Constants defining timer counter operating mode.
584 */
585 #define HRTIM_MODE_CONTINOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */
586 #define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */
587 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */
588
589 #define IS_HRTIM_MODE(MODE)\
590 (((MODE) == HRTIM_MODE_CONTINOUS) || \
591 ((MODE) == HRTIM_MODE_SINGLESHOT) || \
592 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
593
594 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
595 (((MODE) == HRTIM_MODE_SINGLESHOT) || \
596 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
597
598 /**
599 * @}
600 */
601
602 /** @defgroup HRTIM_HalfModeEnable
603 * @{
604 * @brief Constants defining half mode enabling status.
605 */
606 #define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */
607 #define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */
608
609 #define IS_HRTIM_HALFMODE(HALFMODE)\
610 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
611 ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
612 /**
613 * @}
614 */
615
616 /** @defgroup HRTIM_StartOnSyncInputEvent
617 * @{
618 * @brief Constants defining the timer behavior following the synchronization event
619 */
620 #define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
621 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
622
623 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
624 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
625 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
626 /**
627 * @}
628 */
629
630 /** @defgroup HRTIM_ResetOnSyncInputEvent
631 * @{
632 * @brief Constants defining the timer behavior following the synchronization event
633 */
634 #define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
635 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
636
637 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
638 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
639 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
640 /**
641 * @}
642 */
643
644 /** @defgroup HRTIM_DACSynchronization
645 * @{
646 * @brief Constants defining on which output the DAC synchronization event is sent
647 */
648 #define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */
649 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
650 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
651 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
652
653 #define IS_HRTIM_DACSYNC(DACSYNC)\
654 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
655 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
656 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
657 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
658 /**
659 * @}
660 */
661
662 /** @defgroup HRTIM_RegisterPreloadEnable
663 * @{
664 * @brief Constants defining whether a write access into a preloadable
665 * register is done into the active or the preload register.
666 */
667 #define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */
668 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
669
670 #define IS_HRTIM_PRELOAD(PRELOAD)\
671 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
672 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
673 /**
674 * @}
675 */
676
677 /** @defgroup HRTIM_UpdateGating
678 * @{
679 * @brief Constants defining how the update occurs relatively to the burst DMA
680 * transaction and the external update request on update enable inputs 1 to 3.
681 */
682 #define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */
683 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
684 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
685 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
686 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
687 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
688 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
689 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
690 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
691
692 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
693 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
694 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
695 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
696
697 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
698 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
699 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
700 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
701 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
702 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
703 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
704 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
705 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
706 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
707 /**
708 * @}
709 */
710
711 /** @defgroup HRTIM_TimerBurstMode
712 * @{
713 * @brief Constants defining how the timer behaves during a burst
714 mode operation.
715 */
716 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
717 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
718
719 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
720 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
721 ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
722 /**
723 * @}
724 */
725
726 /** @defgroup HRTIM_TimerRepetitionUpdate
727 * @{
728 * @brief Constants defining whether registers are updated when the timer
729 * repetition period is completed (either due to roll-over or
730 * reset events)
731 */
732 #define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */
733 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
734
735 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
736 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
737 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
738 /**
739 * @}
740 */
741
742
743 /** @defgroup HRTIM_TimerPushPullMode
744 * @{
745 * @brief Constants defining whether or not the push-pull mode is enabled for
746 * a timer.
747 */
748 #define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */
749 #define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
750
751 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
752 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
753 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
754 /**
755 * @}
756 */
757
758 /** @defgroup HRTIM_TimerFaultEnabling
759 * @{
760 * @brief Constants defining whether a faut channel is enabled for a timer
761 */
762 #define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */
763 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
764 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
765 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
766 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
767 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
768
769 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
770
771 /**
772 * @}
773 */
774
775 /** @defgroup HRTIM_TimerFaultLock
776 * @{
777 * @brief Constants defining whether or not fault enabling bits are write
778 * protected for a timer
779 */
780 #define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */
781 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTCLK) /*!< Timer fault enabling bits are read only */
782
783 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
784 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
785 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
786 /**
787 * @}
788 */
789
790 /** @defgroup HRTIM_TimerDeadtimeInsertion
791 * @{
792 * @brief Constants defining whether or not fault the dead time insertion
793 * feature is enabled for a timer
794 */
795 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */
796 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */
797
798 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION)\
799 (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
800 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
801 /**
802 * @}
803 */
804
805 /** @defgroup HRTIM_TimerDelayedProtectionMode
806 * @{
807 * @brief Constants defining all possible delayed protection modes
808 * for a timer. Also define the source and outputs on which the delayed
809 * protection schemes are applied
810 */
811 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
812 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 6 or 8 */
813 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 6 or 8 */
814 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output 2 delayed Idle on external Event 6 or 8 */
815 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 6 or 8 */
816 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 7 or 9 */
817 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 7 or 9 */
818 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output2 delayed Idle on external Event 7 or 9 */
819 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 7 or 9 */
820
821 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION)\
822 (((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) || \
823 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) || \
824 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) || \
825 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) || \
826 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) || \
827 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) || \
828 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) || \
829 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79) || \
830 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79))
831 /**
832 * @}
833 */
834
835 /** @defgroup HRTIM_TimerUpdateTrigger
836 * @{
837 * @brief Constants defining whether the registers update is done synchronously
838 * with any other timer or master update
839 */
840 #define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */
841 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
842 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
843 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
844 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
845 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
846 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
847
848 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
849 /**
850 * @}
851 */
852
853 /** @defgroup HRTIM_TimerResetTrigger
854 * @{
855 * @brief Constants defining the events that can be selected to trigger the reset
856 * of the timer counter
857 */
858 #define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */
859 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
860 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
861 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
862 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
863 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
864 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
865 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
866 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
867 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */
868 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */
869 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */
870 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */
871 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */
872 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */
873 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */
874 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */
875 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */
876 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */
877 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
878 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
879 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
880 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
881 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
882 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
883 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
884 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
885 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
886 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
887 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
888 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
889
890 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
891
892 /**
893 * @}
894 */
895
896 /** @defgroup HRTIM_TimerResetUpdate
897 * @{
898 * @brief Constants defining whether the register are updated upon Timerx
899 * counter reset or rollover to 0 after reaching the period value
900 * in continuous mode
901 */
902 #define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / rollover disabled */
903 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / rollover enabled */
904
905 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
906 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
907 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
908 /**
909 * @}
910 */
911
912 /** @defgroup HRTIM_CompareUnitAutoDelayedMode
913 * @{
914 * @brief Constants defining whether the compare register is behaving in
915 * regular mode (compare match issued as soon as counter equal compare),
916 * or in auto-delayed mode
917 */
918 #define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */
919 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occured */
920 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
921 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
922
923 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
924 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
925 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
926 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
927 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
928
929 /* Auto delayed mode is only available for compare units 2 and 4 */
930 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
931 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) && \
932 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
933 || \
934 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
935 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
936 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
937 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
938 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
939 || \
940 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) && \
941 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
942 || \
943 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
944 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
945 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
946 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
947 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
948 /**
949 * @}
950 */
951
952 /** @defgroup HRTIM_BasicOCMode
953 * @{
954 * @brief Constants defining the behavior of the output signal when the timer
955 operates in basic output compare mode
956 */
957 #define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /*!< Output toggles when the timer counter reaches the compare value */
958 #define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /*!< Output forced to active level when the timer counter reaches the compare value */
959 #define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /*!< Output forced to inactive level when the timer counter reaches the compare value */
960
961 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
962 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
963 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
964 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
965 /**
966 * @}
967 */
968
969 /** @defgroup HRTIM_OutputPolarity
970 * @{
971 * @brief Constants defining the polarity of a timer output
972 */
973 #define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< Output is active HIGH */
974 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
975
976 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
977 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
978 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
979 /**
980 * @}
981 */
982
983 /** @defgroup HRTIM_OutputSetSource
984 * @{
985 * @brief Constants defining the events that can be selected to configure the
986 * set crossbar of a timer output
987 */
988 #define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */
989 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
990 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
991 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
992 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
993 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
994 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
995 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
996 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
997 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
998 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
999 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
1000 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1001 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1002 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1003 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1004 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1005 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1006 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1007 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1008 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1009 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
1010 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
1011 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
1012 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
1013 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
1014 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
1015 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
1016 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
1017 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
1018 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
1019 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
1020
1021 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
1022 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
1023 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
1024 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
1025 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
1026 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
1027 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
1028 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
1029 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
1030 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
1031 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
1032 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
1033 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
1034 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
1035 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
1036 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
1037 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
1038 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
1039 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
1040 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
1041 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
1042 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
1043 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
1044 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
1045 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
1046 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
1047 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
1048 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
1049 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
1050 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
1051 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
1052 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
1053 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
1054 /**
1055 * @}
1056 */
1057
1058 /** @defgroup HRTIM_OutputResetSource
1059 * @{
1060 * @brief Constants defining the events that can be selected to configure the
1061 * set crossbar of a timer output
1062 */
1063 #define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */
1064 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1065 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
1066 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
1067 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
1068 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
1069 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
1070 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
1071 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
1072 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
1073 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
1074 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
1075 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1076 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1077 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1078 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1079 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1080 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1081 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1082 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1083 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1084 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
1085 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
1086 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
1087 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
1088 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
1089 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
1090 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
1091 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
1092 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
1093 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
1094 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
1095
1096 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
1097 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
1098 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
1099 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
1100 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
1101 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
1102 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
1103 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
1104 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
1105 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
1106 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
1107 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
1108 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
1109 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
1110 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
1111 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
1112 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
1113 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
1114 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
1115 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
1116 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
1117 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
1118 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
1119 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
1120 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
1121 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
1122 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
1123 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
1124 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
1125 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
1126 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
1127 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
1128 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
1129 /**
1130 * @}
1131 */
1132
1133 /** @defgroup HRTIM_OutputIdleMode
1134 * @{
1135 * @brief Constants defining whether or not the timer output transition to its
1136 IDLE state when burst mode is entered
1137 */
1138 #define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */
1139 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1140
1141 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
1142 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
1143 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
1144 /**
1145 * @}
1146 */
1147
1148 /** @defgroup HRTIM_OutputIDLEState
1149 * @{
1150 * @brief Constants defining the IDLE state of a timer output
1151 */
1152 #define HRTIM_OUTPUTIDLESTATE_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */
1153 #define HRTIM_OUTPUTIDLESTATE_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1154
1155 #define IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE)\
1156 (((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_INACTIVE) || \
1157 ((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_ACTIVE))
1158 /**
1159 * @}
1160 */
1161
1162 /** @defgroup HRTIM_OutputFAULTState
1163 * @{
1164 * @brief Constants defining the FAULT state of a timer output
1165 */
1166 #define HRTIM_OUTPUTFAULTSTATE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
1167 #define HRTIM_OUTPUTFAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1168 #define HRTIM_OUTPUTFAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1169 #define HRTIM_OUTPUTFAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1170
1171 #define IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE)\
1172 (((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_NONE) || \
1173 ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_ACTIVE) || \
1174 ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_INACTIVE) || \
1175 ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_HIGHZ))
1176 /**
1177 * @}
1178 */
1179
1180 /** @defgroup HRTIM_OutputChopperModeEnable
1181 * @{
1182 * @brief Constants defining whether or not chopper mode is enabled for a timer
1183 output
1184 */
1185 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
1186 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output at active level when in FAULT state */
1187
1188 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
1189 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
1190 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup HRTIM_OutputBurstModeEntryDelayed
1196 * @{
1197 * @brief Constants defining the idle mode entry is delayed by forcing a
1198 deadtime insertion before switching the outputs to their idle state
1199 */
1200 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */
1201 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1202
1203 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
1204 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
1205 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
1206 /**
1207 * @}
1208 */
1209
1210 /** @defgroup HRTIM_CaptureUnitTrigger
1211 * @{
1212 * @brief Constants defining the events that can be selected to trigger the
1213 * capture of the timing unit counter
1214 */
1215 #define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */
1216 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
1217 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
1218 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
1219 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
1220 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
1221 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
1222 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
1223 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
1224 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
1225 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
1226 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
1227 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
1228 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
1229 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TA1CMP1) /*!< Timer A Compare 1 triggers Capture */
1230 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TA1CMP2) /*!< Timer A Compare 2 triggers Capture */
1231 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
1232 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
1233 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TB1CMP1) /*!< Timer B Compare 1 triggers Capture */
1234 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TB1CMP2) /*!< Timer B Compare 2 triggers Capture */
1235 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
1236 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
1237 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TC1CMP1) /*!< Timer C Compare 1 triggers Capture */
1238 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TC1CMP2) /*!< Timer C Compare 2 triggers Capture */
1239 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
1240 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
1241 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TD1CMP1) /*!< Timer D Compare 1 triggers Capture */
1242 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TD1CMP2) /*!< Timer D Compare 2 triggers Capture */
1243 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
1244 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
1245 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TE1CMP1) /*!< Timer E Compare 1 triggers Capture */
1246 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TE1CMP2) /*!< Timer E Compare 2 triggers Capture */
1247
1248 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
1249 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
1250 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
1251 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
1252 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
1253 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
1254 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
1255 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
1256 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
1257 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
1258 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
1259 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
1260 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
1261 || \
1262 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
1263 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
1264 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
1265 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
1266 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2))) \
1267 || \
1268 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
1269 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
1270 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
1271 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
1272 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2))) \
1273 || \
1274 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
1275 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
1276 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
1277 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
1278 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2))) \
1279 || \
1280 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
1281 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
1282 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
1283 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
1284 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \
1285 || \
1286 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
1287 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
1288 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
1289 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
1290 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup HRTIM_TimerExternalEventFilter
1296 * @{
1297 * @brief Constants defining the event filtering applied to external events
1298 * by a timer
1299 */
1300 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
1301 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
1302 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
1303 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
1304 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
1305 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1306 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1307 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1308 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1309 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1310 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1311 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1312 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1313 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
1314 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
1315 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
1316
1317 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
1318 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
1319 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
1320 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
1321 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
1322 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
1323 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
1324 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
1325 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
1326 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
1327 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
1328 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
1329 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
1330 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
1331 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
1332 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
1333 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
1334 /**
1335 * @}
1336 */
1337
1338 /** @defgroup HRTIM_TimerExternalEventLatch
1339 * @{
1340 * @brief Constants defining whether or not the external event is
1341 * memorized (latched) and generated as soon as the blanking period
1342 * is completed or the window ends
1343 */
1344 #define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */
1345 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event 1 is latched and delayed till the end of the blanking or windowing period */ /*!< Blanking from counter reset/roll-over to Compare 1 */
1346
1347 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
1348 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
1349 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
1350 /**
1351 * @}
1352 */
1353
1354 /** @defgroup HRTIM_DeadtimeRisingSign
1355 * @{
1356 * @brief Constants defining whether the deadtime is positive or negative
1357 * (overlapping signal) on rising edge
1358 */
1359 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */
1360 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
1361
1362 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
1363 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
1364 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup HRTIM_DeadtimeRisingLock
1370 * @{
1371 * @brief Constants defining whether or not the deadtime (rising sign and
1372 * value) is write protected
1373 */
1374 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writable */
1375 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
1376
1377 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
1378 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
1379 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
1380 /**
1381 * @}
1382 */
1383
1384 /** @defgroup HRTIM_DeadtimeRisingSignLock
1385 * @{
1386 * @brief Constants defining whether or not the deadtime rising sign is write
1387 * protected
1388 */
1389 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writable */
1390 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
1391
1392 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
1393 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
1394 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
1395 /**
1396 * @}
1397 */
1398
1399 /** @defgroup HRTIM_DeadtimeFallingSign
1400 * @{
1401 * @brief Constants defining whether the deadtime is positive or negative
1402 * (overlapping signal) on falling edge
1403 */
1404 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */
1405 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1406
1407 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
1408 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
1409 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
1410 /**
1411 * @}
1412 */
1413
1414 /** @defgroup HRTIM_DeadtimeFallingLock
1415 * @{
1416 * @brief Constants defining whether or not the deadtime (falling sign and
1417 * value) is write protected
1418 */
1419 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writable */
1420 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
1421
1422 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
1423 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
1424 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
1425 /**
1426 * @}
1427 */
1428
1429 /** @defgroup HRTIM_DeadtimeFallingSignLock
1430 * @{
1431 * @brief Constants defining whether or not the deadtime falling sign is write
1432 * protected
1433 */
1434 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writable */
1435 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
1436
1437 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
1438 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
1439 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
1440 /**
1441 * @}
1442 */
1443
1444 /** @defgroup HRTIM_SynchronizationInputSource
1445 * @{
1446 * @brief Constants defining defining the synchronization input source
1447 */
1448 #define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
1449 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
1450 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
1451
1452 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
1453 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
1454 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
1455 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
1456 /**
1457 * @}
1458 */
1459
1460 /** @defgroup HRTIM_SynchronizationOutputSource
1461 * @{
1462 * @brief Constants defining the source and event to be sent on the
1463 * synchronization outputs
1464 */
1465 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event */
1466 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event*/
1467 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events */
1468 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event */
1469
1470 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
1471 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
1472 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
1473 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
1474 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
1475 /**
1476 * @}
1477 */
1478
1479 /** @defgroup HRTIM_SynchronizationOutputPolarity
1480 * @{
1481 * @brief Constants defining the routing and conditioning of the synchronization output event
1482 */
1483 #define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */
1484 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
1485 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
1486
1487 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
1488 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
1489 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
1490 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
1491 /**
1492 * @}
1493 */
1494
1495 /** @defgroup HRTIM_ExternalEventSources
1496 * @{
1497 * @brief Constants defining available sources associated to external events
1498 */
1499 #define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */
1500 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */
1501 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */
1502 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */
1503
1504 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
1505 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
1506 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
1507 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
1508 ((EVENTSRC) == HRTIM_EVENTSRC_4))
1509 /**
1510 * @}
1511 */
1512
1513 /** @defgroup HRTIM_ExternalEventPolarity
1514 * @{
1515 * @brief Constants defining the polarity of an external event
1516 */
1517 #define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */
1518 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1519
1520 #define IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY)\
1521 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
1522 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))
1523 /**
1524 * @}
1525 */
1526
1527 /** @defgroup HRTIM_ExternalEventSensitivity
1528 * @{
1529 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
1530 * of an external event
1531 */
1532 #define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */
1533 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1534 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1535 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1536
1537 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
1538 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
1539 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
1540 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
1541 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
1542 /**
1543 * @}
1544 */
1545
1546 /** @defgroup HRTIM_ExternalEventFastMode
1547 * @{
1548 * @brief Constants defining whether or not an external event is programmed in
1549 fast mode
1550 */
1551 #define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1552 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1553
1554 #define IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE)\
1555 (((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
1556 ((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))
1557
1558 #define IS_HRTIM_FASTMODE_AVAILABLE(EVENT)\
1559 (((EVENT) == HRTIM_EVENT_1) || \
1560 ((EVENT) == HRTIM_EVENT_2) || \
1561 ((EVENT) == HRTIM_EVENT_3) || \
1562 ((EVENT) == HRTIM_EVENT_4) || \
1563 ((EVENT) == HRTIM_EVENT_5))
1564 /**
1565 * @}
1566 */
1567
1568 /** @defgroup HRTIM_ExternalEventFilter
1569 * @{
1570 * @brief Constants defining the frequency used to sample an external event 6
1571 * input and the length (N) of the digital filter applied
1572 */
1573 #define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
1574 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1575 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1576 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1577 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */
1578 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */
1579 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */
1580 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */
1581 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */
1582 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */
1583 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */
1584 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */
1585 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */
1586 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */
1587 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */
1588 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */
1589
1590 #define IS_HRTIM_EVENTFILTER(EVENTFILTER)\
1591 (((EVENTFILTER) == HRTIM_EVENTFILTER_NONE) || \
1592 ((EVENTFILTER) == HRTIM_EVENTFILTER_1) || \
1593 ((EVENTFILTER) == HRTIM_EVENTFILTER_2) || \
1594 ((EVENTFILTER) == HRTIM_EVENTFILTER_3) || \
1595 ((EVENTFILTER) == HRTIM_EVENTFILTER_4) || \
1596 ((EVENTFILTER) == HRTIM_EVENTFILTER_5) || \
1597 ((EVENTFILTER) == HRTIM_EVENTFILTER_6) || \
1598 ((EVENTFILTER) == HRTIM_EVENTFILTER_7) || \
1599 ((EVENTFILTER) == HRTIM_EVENTFILTER_8) || \
1600 ((EVENTFILTER) == HRTIM_EVENTFILTER_9) || \
1601 ((EVENTFILTER) == HRTIM_EVENTFILTER_10) || \
1602 ((EVENTFILTER) == HRTIM_EVENTFILTER_11) || \
1603 ((EVENTFILTER) == HRTIM_EVENTFILTER_12) || \
1604 ((EVENTFILTER) == HRTIM_EVENTFILTER_13) || \
1605 ((EVENTFILTER) == HRTIM_EVENTFILTER_14) || \
1606 ((EVENTFILTER) == HRTIM_EVENTFILTER_15))
1607 /**
1608 * @}
1609 */
1610
1611 /** @defgroup HRTIM_ ExternalEventPrescaler
1612 * @{
1613 * @brief Constants defining division ratio between the timer clock frequency
1614 * fHRTIM) and the external event signal sampling clock (fEEVS)
1615 * used by the digital filters
1616 */
1617 #define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */
1618 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */
1619 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */
1620 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */
1621
1622 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
1623 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
1624 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
1625 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
1626 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
1627 /**
1628 * @}
1629 */
1630
1631 /** @defgroup HRTIM_FaultSources
1632 * @{
1633 * @brief Constants defining whether a faults is be triggered by any external
1634 * or internal fault source
1635 */
1636 #define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */
1637 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1638
1639
1640 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
1641 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
1642 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
1643 /**
1644 * @}
1645 */
1646
1647 /** @defgroup HRTIM_FaultPolarity
1648 * @{
1649 * @brief Constants defining the polarity of a fault event
1650 */
1651 #define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */
1652 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1653
1654 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
1655 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
1656 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
1657 /**
1658 * @}
1659 */
1660
1661 /** @defgroup HRTIM_FaultFilter
1662 * @{
1663 * @ brief Constants defining the frequency used to sample the fault input and
1664 * the length (N) of the digital filter applied
1665 */
1666 #define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
1667 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1668 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1669 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1670 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1671 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1672 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1673 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1674 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1675 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1676 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1677 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1678 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1679 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1680 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1681 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1682
1683 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
1684 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
1685 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
1686 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
1687 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
1688 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
1689 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
1690 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
1691 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
1692 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
1693 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
1694 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
1695 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
1696 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
1697 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
1698 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
1699 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
1700 /**
1701 * @}
1702 */
1703
1704 /** @defgroup HRTIM_FaultLock
1705 * @{
1706 * @brief Constants defining whether or not the fault programming bits are
1707 write protected
1708 */
1709 #define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */
1710 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
1711
1712 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
1713 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
1714 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
1715 /**
1716 * @}
1717 */
1718
1719 /** @defgroup HRTIM_ExternalFaultPrescaler
1720 * @{
1721 * @brief Constants defining the division ratio between the timer clock
1722 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
1723 * by the digital filters.
1724 */
1725 #define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */
1726 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */
1727 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */
1728 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */
1729
1730 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
1731 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
1732 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
1733 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
1734 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
1735 /**
1736 * @}
1737 */
1738
1739 /** @defgroup HRTIM_BurstModeOperatingmode
1740 * @{
1741 * @brief Constants defining if the burst mode is entered once or if it is
1742 * continuously operating
1743 */
1744 #define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */
1745 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1746
1747 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
1748 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
1749 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
1750 /**
1751 * @}
1752 */
1753
1754 /** @defgroup HRTIM_BurstModeClockSource
1755 * @{
1756 * @brief Constants defining the clock source for the burst mode counter
1757 */
1758 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1759 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1760 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1761 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1762 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1763 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1764 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1765 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1766 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3 (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1767 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4 (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock */
1768 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1769
1770 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
1771 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
1772 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
1773 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
1774 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
1775 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
1776 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
1777 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1) || \
1778 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2) || \
1779 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3) || \
1780 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4) || \
1781 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
1782 /**
1783 * @}
1784 */
1785
1786 /** @defgroup HRTIM_BurstModePrescaler
1787 * @{
1788 * @brief Constants defining the prescaling ratio of the fHRTIM clock
1789 * for the burst mode controller
1790 */
1791 #define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */
1792 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2 */
1793 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/4 */
1794 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8 */
1795 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/16 */
1796 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32 */
1797 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/64 */
1798 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/128 */
1799 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPSC_3) /*!< fBRST = fHRTIM/256 */
1800 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/512 */
1801 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/1024 */
1802 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2048*/
1803 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/4096 */
1804 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8192 */
1805 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/16384 */
1806 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32768 */
1807
1808 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
1809 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
1810 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
1811 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
1812 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
1813 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
1814 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
1815 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
1816 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
1817 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
1818 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
1819 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
1820 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
1821 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
1822 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
1823 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
1824 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
1825 /**
1826 * @}
1827 */
1828
1829 /** @defgroup HRTIM_BurstModeRegisterPreloadEnable
1830 * @{
1831 * @brief Constants defining whether or not burst mode registers preload
1832 mechanism is enabled, i.e. a write access into a preloadable register
1833 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
1834 */
1835 #define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */
1836 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
1837
1838 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
1839 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
1840 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
1841 /**
1842 * @}
1843 */
1844
1845 /** @defgroup HRTIM_BurstModeTrigger
1846 * @{
1847 * @brief Constants defining the events that can be used tor trig the burst
1848 * mode operation
1849 */
1850 #define HRTIM_BURSTMODETRIGGER_SOFTWARE (uint32_t)0x00000000 /*!< Software trigger */
1851 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
1852 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
1853 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */
1854 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */
1855 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */
1856 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */
1857 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
1858 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
1859 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
1860 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
1861 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
1862 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
1863 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
1864 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
1865 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
1866 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
1867 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
1868 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
1869 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
1870 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
1871 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
1872 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
1873 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
1874 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
1875 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
1876 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
1877 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
1878 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
1879 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 */
1880 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 */
1881 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
1882
1883 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
1884 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
1885 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
1886 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
1887 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
1888 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
1889 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
1890 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
1891 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
1892 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
1893 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
1894 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
1895 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
1896 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
1897 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
1898 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
1899 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
1900 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
1901 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
1902 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
1903 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
1904 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
1905 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
1906 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
1907 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
1908 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
1909 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
1910 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
1911 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
1912 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
1913 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
1914 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
1915 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
1916 /**
1917 * @}
1918 */
1919
1920 /** @defgroup HRTIM_ADCTriggerUpdateSource
1921 * @{
1922 * @brief constants defining the source triggering the update of the
1923 HRTIM_ADCxR register (transfer from preload to active register).
1924 */
1925 #define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */
1926 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
1927 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
1928 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
1929 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
1930 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
1931
1932 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
1933 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
1934 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
1935 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
1936 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
1937 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
1938 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
1939 /**
1940 * @}
1941 */
1942
1943 /** @defgroup HRTIM_ADCTriggerEvent
1944 * @{
1945 * @brief constants defining the events triggering ADC conversion.
1946 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
1947 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
1948 */
1949 #define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
1950 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */
1951 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */
1952 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */
1953 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */
1954 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
1955 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */
1956 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */
1957 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */
1958 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */
1959 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */
1960 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */
1961 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */
1962 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */
1963 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
1964 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
1965 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */
1966 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */
1967 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */
1968 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
1969 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
1970 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */
1971 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */
1972 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */
1973 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
1974 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */
1975 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */
1976 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */
1977 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
1978 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */
1979 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */
1980 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */
1981 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
1982
1983 #define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
1984 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */
1985 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */
1986 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */
1987 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */
1988 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
1989 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */
1990 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */
1991 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */
1992 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */
1993 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */
1994 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */
1995 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */
1996 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */
1997 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
1998 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */
1999 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */
2000 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */
2001 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
2002 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */
2003 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */
2004 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */
2005 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
2006 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
2007 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */
2008 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */
2009 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */
2010 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
2011 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
2012 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */
2013 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */
2014 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */
2015 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
2016
2017 /**
2018 * @}
2019 */
2020
2021 /** @defgroup HRTIM_DLLCalibrationRate
2022 * @{
2023 * @brief Constants defining the DLL calibration periods (in micro seconds)
2024 */
2025
2026 #define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /*!< 1048576 * tHRTIM (7.3 ms) */
2027 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */
2028 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< 131072 * tHRTIM (910 µs) */
2029 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */
2030
2031 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
2032 (((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
2033 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
2034 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
2035 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
2036 /**
2037 * @}
2038 */
2039
2040 /** @defgroup HRTIM_BurstDMARegistersUpdate
2041 * @{
2042 * @brief Constants defining the registers that can be written during a burst
2043 * DMA operation
2044 */
2045 #define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */
2046 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
2047 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
2048 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
2049 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
2050 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
2051 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
2052 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
2053 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
2054 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
2055 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
2056 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
2057 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
2058 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
2059 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
2060 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
2061 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
2062 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
2063 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
2064 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
2065 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
2066 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
2067
2068 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
2069 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
2070 || \
2071 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2072 || \
2073 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2074 || \
2075 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2076 || \
2077 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2078 || \
2079 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
2080 /**
2081 * @}
2082 */
2083
2084 /** @defgroup HRTIM_BursttModeControl
2085 * @{
2086 * @brief Constants used to enable or disable the burst mode controller
2087 */
2088 #define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */
2089 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
2090
2091 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
2092 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
2093 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
2094 /**
2095 * @}
2096 */
2097
2098 /** @defgroup HRTIM_FaultModeControl
2099 * @{
2100 * @brief Constants used to enable or disable the Fault mode
2101 */
2102 #define HRTIM_FAULT_DISABLED (uint32_t)0x00000000 /*!< Fault mode disabled */
2103 #define HRTIM_FAULT_ENABLED (HRTIM_FLTINR1_FLT1E) /*!< Fault mode enabled */
2104
2105 #define IS_HRTIM_FAULTCTL(FAULTCTL)\
2106 (((FAULTCTL) == HRTIM_FAULT_DISABLED) || \
2107 ((FAULTCTL) == HRTIM_FAULT_ENABLED))
2108 /**
2109 * @}
2110 */
2111
2112 /** @defgroup HRTIM_SoftwareTimerUpdate
2113 * @{
2114 * @brief Constants used to force timer registers update
2115 */
2116 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
2117 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
2118 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
2119 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
2120 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
2121 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
2122
2123 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
2124 /**
2125 * @}
2126 */
2127
2128 /** @defgroup HRTIM_SoftwareTimerReset
2129 * @{
2130 * @brief Constants used to force timer counter reset
2131 */
2132 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
2133 #define HRTIM_TIMERRESET_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
2134 #define HRTIM_TIMERRESET_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
2135 #define HRTIM_TIMERRESET_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
2136 #define HRTIM_TIMERRESET_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
2137 #define HRTIM_TIMERRESET_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
2138
2139 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
2140 /**
2141 * @}
2142 */
2143
2144 /** @defgroup HRTIM_OutputLevel
2145 * @{
2146 * @brief Constants defining the level of a timer output
2147 */
2148 #define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /*!< Forces the output to its active state */
2149 #define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /*!< Forces the output to its inactive state */
2150
2151 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
2152 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
2153 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
2154 /**
2155 * @}
2156 */
2157
2158 /** @defgroup HRTIM_OutputState
2159 * @{
2160 * @brief Constants defining the state of a timer output
2161 */
2162 #define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
2163 inactive level as programmed in the crossbar unit */
2164 #define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
2165 outputs are disabled by software or during a burst mode operation */
2166 #define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
2167 FAULTx inputs */
2168 /**
2169 * @}
2170 */
2171
2172 /** @defgroup HRTIM_BurstModeStatus
2173 * @{
2174 * @brief Constants defining the operating state of the burst mode controller
2175 */
2176 #define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */
2177 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
2178 /**
2179 * @}
2180 */
2181
2182 /** @defgroup HRTIM_CurrentPushPullStatus
2183 * @{
2184 * @brief Constants defining on which output the signal is currently applied
2185 * in push-pull mode
2186 */
2187 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */
2188 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
2189 /**
2190 * @}
2191 */
2192
2193 /** @defgroup HRTIM_IdlePushPullStatus
2194 * @{
2195 * @brief Constants defining on which output the signal was applied, in
2196 * push-pull mode balanced fault mode or delayed idle mode, when the
2197 * protection was triggered
2198 */
2199 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
2200 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
2201 /**
2202 * @}
2203 */
2204
2205 /** @defgroup HRTIM_CommonInterrupt
2206 * @{
2207 */
2208 #define HRTIM_IT_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
2209 #define HRTIM_IT_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
2210 #define HRTIM_IT_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
2211 #define HRTIM_IT_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
2212 #define HRTIM_IT_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
2213 #define HRTIM_IT_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
2214 #define HRTIM_IT_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
2215 #define HRTIM_IT_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
2216
2217 #define IS_HRTIM_IT(IT)\
2218 (((IT) == HRTIM_ISR_FLT1) || \
2219 ((IT) == HRTIM_ISR_FLT2) || \
2220 ((IT) == HRTIM_ISR_FLT3) || \
2221 ((IT) == HRTIM_ISR_FLT4) || \
2222 ((IT) == HRTIM_ISR_FLT5) || \
2223 ((IT) == HRTIM_ISR_SYSFLT) || \
2224 ((IT) == HRTIM_ISR_DLLRDY) || \
2225 ((IT) == HRTIM_ISR_BMPER))
2226 /**
2227 * @}
2228 */
2229
2230 /** @defgroup HRTIM_MasterInterrupt
2231 * @{
2232 */
2233 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt flag */
2234 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt flag */
2235 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt flag */
2236 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt flag */
2237 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt flag */
2238 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt flag */
2239 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt flag */
2240
2241 #define IS_HRTIM_MASTER_IT(IT)\
2242 (((IT) == HRTIM_MDIER_MCMP1IE) || \
2243 ((IT) == HRTIM_MDIER_MCMP2IE) || \
2244 ((IT) == HRTIM_MDIER_MCMP3IE) || \
2245 ((IT) == HRTIM_MDIER_MCMP4IE) || \
2246 ((IT) == HRTIM_MDIER_MREPIE) || \
2247 ((IT) == HRTIM_MDIER_SYNCIE) || \
2248 ((IT) == HRTIM_MDIER_MUPDIE))
2249
2250 /** @defgroup HRTIM_MasterFlag
2251 * @{
2252 */
2253 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
2254 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
2255 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
2256 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
2257 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
2258 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
2259 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
2260
2261 #define IS_HRTIM_MASTER_FLAG(FLAG)\
2262 (((FLAG) == HRTIM_MISR_MCMP1) || \
2263 ((FLAG) == HRTIM_MISR_MCMP2) || \
2264 ((FLAG) == HRTIM_MISR_MCMP3) || \
2265 ((FLAG) == HRTIM_MISR_MCMP4) || \
2266 ((FLAG) == HRTIM_MISR_MREP) || \
2267 ((FLAG) == HRTIM_MISR_SYNC) || \
2268 ((FLAG) == HRTIM_MISR_MUPD))
2269 /**
2270 * @}
2271 */
2272
2273 /** @defgroup HRTIM_TimingUnitInterrupt
2274 * @{
2275 */
2276 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt flag */
2277 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt flag */
2278 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt flag */
2279 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt flag */
2280 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt flag */
2281 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt flag */
2282 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt flag */
2283 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt flag */
2284 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt flag */
2285 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt flag */
2286 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt flag */
2287 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt flag */
2288 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */
2289 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRT1IE /*!< Timer delay protection interrupt flag */
2290
2291 #define IS_HRTIM_TIM_IT(IT)\
2292 (((IT) == HRTIM_TIMDIER_CMP1IE) || \
2293 ((IT) == HRTIM_TIMDIER_CMP2IE) || \
2294 ((IT) == HRTIM_TIMDIER_CMP3IE) || \
2295 ((IT) == HRTIM_TIMDIER_CMP4IE) || \
2296 ((IT) == HRTIM_TIMDIER_REPIE) || \
2297 ((IT) == HRTIM_TIMDIER_UPDIE) || \
2298 ((IT) == HRTIM_TIMDIER_CPT1IE) || \
2299 ((IT) == HRTIM_TIMDIER_CPT2IE) || \
2300 ((IT) == HRTIM_TIMDIER_SET1IE) || \
2301 ((IT) == HRTIM_TIMDIER_RST1IE) || \
2302 ((IT) == HRTIM_TIMDIER_SET2IE) || \
2303 ((IT) == HRTIM_TIMDIER_RST2IE) || \
2304 ((IT) == HRTIM_TIMDIER_RSTIE) || \
2305 ((IT) == HRTIM_TIMDIER_DLYPRTIE))
2306
2307 /**
2308 * @}
2309 */
2310
2311 /** @defgroup HRTIM_TimingUnitFlag
2312 * @{
2313 */
2314 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
2315 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
2316 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
2317 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
2318 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
2319 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
2320 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
2321 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
2322 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
2323 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
2324 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
2325 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
2326 #define HRTIM_TIM_FLAG_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */
2327 #define HRTIM_TIM_FLAG_DLYPRT1 HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
2328
2329 #define IS_HRTIM_TIM_FLAG(FLAG)\
2330 (((FLAG) == HRTIM_TIM_FLAG_CMP1) || \
2331 ((FLAG) == HRTIM_TIM_FLAG_CMP2) || \
2332 ((FLAG) == HRTIM_TIM_FLAG_CMP3) || \
2333 ((FLAG) == HRTIM_TIM_FLAG_CMP4) || \
2334 ((FLAG) == HRTIM_TIM_FLAG_REP) || \
2335 ((FLAG) == HRTIM_TIM_FLAG_UPD) || \
2336 ((FLAG) == HRTIM_TIM_FLAG_CPT1) || \
2337 ((FLAG) == HRTIM_TIM_FLAG_CPT2) || \
2338 ((FLAG) == HRTIM_TIM_FLAG_SET1) || \
2339 ((FLAG) == HRTIM_TIM_FLAG_RST1) || \
2340 ((FLAG) == HRTIM_TIM_FLAG_SET2) || \
2341 ((FLAG) == HRTIM_TIM_FLAG_RST2) || \
2342 ((FLAG) == HRTIM_TIM_FLAG_RST) || \
2343 ((FLAG) == HRTIM_TIM_FLAG_DLYPRT1))
2344
2345 /**
2346 * @}
2347 */
2348
2349 /** @defgroup HRTIM_MasterDMARequest
2350 * @{
2351 */
2352 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request flag */
2353 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request flag */
2354 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request flag */
2355 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request flag */
2356 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request flag */
2357 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request flag */
2358 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request flag */
2359
2360 #define IS_HRTIM_MASTER_DMA(DMA)\
2361 (((DMA) == HRTIM_MDIER_MCMP1DE) || \
2362 ((DMA) == HRTIM_MDIER_MCMP2DE) || \
2363 ((DMA) == HRTIM_MDIER_MCMP3DE) || \
2364 ((DMA) == HRTIM_MDIER_MCMP4DE) || \
2365 ((DMA) == HRTIM_MDIER_MREPDE) || \
2366 ((DMA) == HRTIM_MDIER_SYNCDE) || \
2367 ((DMA) == HRTIM_MDIER_MUPDDE))
2368 /**
2369 * @}
2370 */
2371
2372 /** @defgroup HRTIM_TimingUnitDMARequest
2373 * @{
2374 */
2375 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 interrupt flag */
2376 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 interrupt flag */
2377 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 interrupt flag */
2378 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 interrupt flag */
2379 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition interrupt flag */
2380 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update interrupt flag */
2381 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 interrupt flag */
2382 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 interrupt flag */
2383 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set interrupt flag */
2384 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset interrupt flag */
2385 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set interrupt flag */
2386 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset interrupt flag */
2387 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset interrupt flag */
2388 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection interrupt flag */
2389
2390 #define IS_HRTIM_TIM_DMA(DMA)\
2391 (((DMA) == HRTIM_TIMDIER_CMP1DE) || \
2392 ((DMA) == HRTIM_TIMDIER_CMP2DE) || \
2393 ((DMA) == HRTIM_TIMDIER_CMP3DE) || \
2394 ((DMA) == HRTIM_TIMDIER_CMP4DE) || \
2395 ((DMA) == HRTIM_TIMDIER_REPDE) || \
2396 ((DMA) == HRTIM_TIMDIER_UPDDE) || \
2397 ((DMA) == HRTIM_TIMDIER_CPT1DE) || \
2398 ((DMA) == HRTIM_TIMDIER_CPT2DE) || \
2399 ((DMA) == HRTIM_TIMDIER_SET1DE) || \
2400 ((DMA) == HRTIM_TIMDIER_RST1DE) || \
2401 ((DMA) == HRTIM_TIMDIER_SET2DE) || \
2402 ((DMA) == HRTIM_TIMDIER_RST2DE) || \
2403 ((DMA) == HRTIM_TIMDIER_RSTDE) || \
2404 ((DMA) == HRTIM_TIMDIER_DLYPRTDE))
2405
2406 /**
2407 * @}
2408 */
2409
2410 /**
2411 * @}
2412 */
2413
2414 /** @defgroup HRTIM_Instancedefinition
2415 * @{
2416 */
2417 #define IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1)
2418 /**
2419 * @}
2420 */
2421
2422 /**
2423 * @}
2424 */
2425
2426 /* Exported macro ------------------------------------------------------------*/
2427
2428
2429 /** @brief Enables or disables the timer counter(s)
2430 * @param __HANDLE__: specifies the HRTIM Handle.
2431 * @param __TIMERS__: timersto enable/disable
2432 * This parameter can be any combinations of the following values:
2433 * @arg HRTIM_TIMERID_MASTER: Master timer identifier
2434 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
2435 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
2436 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
2437 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
2438 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
2439 * @retval None
2440 */
2441 #define __HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->HRTIM_MASTER.MCR |= (__TIMERS__))
2442
2443 /* The counter of a timing unit is disabled only if all the timer outputs */
2444 /* are disabled and no capture is configured */
2445 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
2446 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
2447 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
2448 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
2449 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
2450 #define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
2451 do {\
2452 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
2453 {\
2454 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_MASTER);\
2455 }\
2456 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
2457 {\
2458 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TAOEN_MASK) == RESET)\
2459 {\
2460 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_A);\
2461 }\
2462 }\
2463 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
2464 {\
2465 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TBOEN_MASK) == RESET)\
2466 {\
2467 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_B);\
2468 }\
2469 }\
2470 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
2471 {\
2472 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TCOEN_MASK) == RESET)\
2473 {\
2474 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_C);\
2475 }\
2476 }\
2477 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
2478 {\
2479 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TDOEN_MASK) == RESET)\
2480 {\
2481 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_D);\
2482 }\
2483 }\
2484 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
2485 {\
2486 if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TEOEN_MASK) == RESET)\
2487 {\
2488 ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_E);\
2489 }\
2490 }\
2491 } while(0)
2492
2493 /* Exported functions --------------------------------------------------------*/
2494
2495 /* Simple time base related functions *****************************************/
2496 void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2497
2498 void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
2499
2500 void HRTIM_SimpleBaseStart(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
2501 void HRTIM_SimpleBaseStop(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
2502
2503 /* Simple output compare related functions ************************************/
2504 void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2505
2506 void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *hrtim,
2507 uint32_t TimerIdx,
2508 uint32_t OCChannel,
2509 HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg);
2510
2511 void HRTIM_SimpleOCStart(HRTIM_TypeDef *hrtim,
2512 uint32_t TimerIdx,
2513 uint32_t OCChannel);
2514 void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
2515 uint32_t TimerIdx,
2516 uint32_t OCChannel);
2517 /* Simple PWM output related functions ****************************************/
2518 void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2519
2520 void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *hrtim,
2521 uint32_t TimerIdx,
2522 uint32_t PWMChannel,
2523 HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg);
2524
2525 void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
2526 uint32_t TimerIdx,
2527 uint32_t PWMChannel);
2528 void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
2529 uint32_t TimerIdx,
2530 uint32_t PWMChannel);
2531 /* Simple capture related functions *******************************************/
2532 void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2533
2534 void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *hrtim,
2535 uint32_t TimerIdx,
2536 uint32_t CaptureChannel,
2537 HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg);
2538
2539 void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
2540 uint32_t TimerIdx,
2541 uint32_t CaptureChannel);
2542 void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
2543 uint32_t TimerIdx,
2544 uint32_t CaptureChannel);
2545 /* SImple one pulse related functions *****************************************/
2546 void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2547
2548 void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *hrtim,
2549 uint32_t TimerIdx,
2550 uint32_t OnePulseChannel,
2551 HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg);
2552
2553 void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
2554 uint32_t TimerIdx,
2555 uint32_t OnePulseChannel);
2556 void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIM_,
2557 uint32_t TimerIdx,
2558 uint32_t OnePulseChannel);
2559 /* Waveform related functions *************************************************/
2560 void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
2561 uint32_t TimerIdx,
2562 HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
2563 HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct);
2564
2565 void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *hrtim,
2566 uint32_t TimerIdx,
2567 HRTIM_TimerCfgTypeDef * HRTIM_TimerCfgStruct);
2568
2569 void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *hrtim,
2570 uint32_t TimerIdx,
2571 uint32_t CompareUnit,
2572 HRTIM_CompareCfgTypeDef* pCompareCfg);
2573
2574 void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
2575 uint32_t CompareUnit,
2576 uint32_t Compare);
2577 void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *hrtim,
2578 uint32_t TimerIdx,
2579 uint32_t CaptureUnit,
2580 HRTIM_CaptureCfgTypeDef* pCaptureCfg);
2581
2582 void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *hrtim,
2583 uint32_t TimerIdx,
2584 uint32_t Output,
2585 HRTIM_OutputCfgTypeDef * pOutputCfg);
2586
2587 void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *hrtim,
2588 uint32_t TimerIdx,
2589 uint32_t Event,
2590 HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
2591
2592 void HRTIM_DeadTimeConfig(HRTIM_TypeDef *hrtim,
2593 uint32_t TimerIdx,
2594 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
2595
2596 void HRTIM_ChopperModeConfig(HRTIM_TypeDef *hrtim,
2597 uint32_t TimerIdx,
2598 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
2599
2600 void HRTIM_BurstDMAConfig(HRTIM_TypeDef *hrtim,
2601 uint32_t TimerIdx,
2602 uint32_t RegistersToUpdate);
2603
2604 void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx,
2605 HRTIM_SynchroCfgTypeDef * pSynchroCfg);
2606
2607 void HRTIM_BurstModeConfig(HRTIM_TypeDef *hrtim,
2608 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
2609
2610 void HRTIM_EventConfig(HRTIM_TypeDef *hrtim,
2611 uint32_t Event,
2612 HRTIM_EventCfgTypeDef* pEventCfg);
2613
2614 void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *hrtim,
2615 uint32_t Prescaler);
2616
2617 void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim,
2618 HRTIM_FaultCfgTypeDef* pFaultCfg,
2619 uint32_t Fault);
2620
2621 void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *hrtim,
2622 uint32_t Prescaler);
2623 void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable);
2624
2625 void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *hrtim,
2626 uint32_t ADCTrigger,
2627 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
2628
2629 void HRTIM_WaveformCounterStart(HRTIM_TypeDef *hrtim,
2630 uint32_t TimersToStart);
2631
2632 void HRTIM_WaveformCounterStop(HRTIM_TypeDef *hrtim,
2633 uint32_t TimersToStop);
2634
2635 void HRTIM_WaveformOutputStart(HRTIM_TypeDef *hrtim,
2636 uint32_t OuputsToStart);
2637 void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIM_,
2638 uint32_t OuputsToStop);
2639
2640 void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *hrtim,
2641 uint32_t CalibrationRate);
2642
2643 /* Interrupt/flags and DMA management */
2644 void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState);
2645 void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState);
2646
2647 void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
2648 void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
2649
2650 void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
2651 void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
2652
2653 FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
2654 FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
2655
2656 ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
2657 ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
2658
2659
2660 void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState);
2661
2662 void HRTIM_BurstModeCtl(HRTIM_TypeDef *hrtim,
2663 uint32_t Enable);
2664
2665 void HRTIM_SoftwareCapture(HRTIM_TypeDef *hrtim,
2666 uint32_t TimerIdx,
2667 uint32_t CaptureUnit);
2668
2669 void HRTIM_SoftwareUpdate(HRTIM_TypeDef *hrtim,
2670 uint32_t TimersToUpdate);
2671
2672 void HRTIM_SoftwareReset(HRTIM_TypeDef *hrtim,
2673 uint32_t TimersToReset);
2674
2675
2676 uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *hrtim,
2677 uint32_t TimerIdx,
2678 uint32_t CaptureUnit);
2679
2680 void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_,
2681 uint32_t TimerIdx,
2682 uint32_t Output,
2683 HRTIM_OutputCfgTypeDef * pOutputCfg);
2684
2685 void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *hrtim,
2686 uint32_t TimerIdx,
2687 uint32_t Output,
2688 uint32_t OutputLevel);
2689
2690 uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *hrtim,
2691 uint32_t TimerIdx,
2692 uint32_t Output);
2693
2694 uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * hhrtim,
2695 uint32_t TimerIdx,
2696 uint32_t Output);
2697
2698 uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *hrtim,
2699 uint32_t TimerIdx,
2700 uint32_t Output);
2701
2702 uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *hrtim);
2703
2704 uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *hrtim,
2705 uint32_t TimerIdx);
2706
2707 uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *hrtim,
2708 uint32_t TimerIdx);
2709 /**
2710 * @}
2711 */
2712
2713 /**
2714 * @}
2715 */
2716
2717 #ifdef __cplusplus
2718 }
2719 #endif
2720
2721 #endif /* __STM32F30x_HRTIM_H */
2722
2723 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
Imprint / Impressum