tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_pwr.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f30x_pwr.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    27-February-2014
   7   * @brief   This file provides firmware functions to manage the following
   8   *          functionalities of the Power Controller (PWR) peripheral:
   9   *           + Backup Domain Access
  10   *           + PVD configuration
  11   *           + WakeUp pins configuration
  12   *           + Low Power modes configuration
  13   *           + Flags management
  14   *
  15   ******************************************************************************
  16   * @attention
  17   *
  18   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  19   *
  20   * Redistribution and use in source and binary forms, with or without modification,
  21   * are permitted provided that the following conditions are met:
  22   *   1. Redistributions of source code must retain the above copyright notice,
  23   *      this list of conditions and the following disclaimer.
  24   *   2. Redistributions in binary form must reproduce the above copyright notice,
  25   *      this list of conditions and the following disclaimer in the documentation
  26   *      and/or other materials provided with the distribution.
  27   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  28   *      may be used to endorse or promote products derived from this software
  29   *      without specific prior written permission.
  30   *
  31   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  32   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  33   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  35   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  36   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  37   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  38   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  39   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  40   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41   *
  42   ******************************************************************************
  43   */
  44
  45 /* Includes ------------------------------------------------------------------*/
  46 #include "stm32f30x_pwr.h"
  47 #include "stm32f30x_rcc.h"
  48
  49 /** @addtogroup STM32F30x_StdPeriph_Driver
  50   * @{
  51   */
  52
  53 /** @defgroup PWR
  54   * @brief PWR driver modules
  55   * @{
  56   */
  57
  58 /* Private typedef -----------------------------------------------------------*/
  59 /* Private define ------------------------------------------------------------*/
  60 /* --------- PWR registers bit address in the alias region ---------- */
  61 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
  62
  63 /* --- CR Register ---*/
  64
  65 /* Alias word address of DBP bit */
  66 #define CR_OFFSET                (PWR_OFFSET + 0x00)
  67 #define DBP_BitNumber            0x08
  68 #define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
  69
  70 /* Alias word address of PVDE bit */
  71 #define PVDE_BitNumber           0x04
  72 #define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
  73
  74 /* ------------------ PWR registers bit mask ------------------------ */
  75
  76 /* CR register bit mask */
  77 #define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
  78 #define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
  79
  80 /* Private macro -------------------------------------------------------------*/
  81 /* Private variables ---------------------------------------------------------*/
  82 /* Private function prototypes -----------------------------------------------*/
  83 /* Private functions ---------------------------------------------------------*/
  84
  85 /** @defgroup PWR_Private_Functions
  86   * @{
  87   */
  88
  89 /** @defgroup PWR_Group1 Backup Domain Access function
  90  *  @brief   Backup Domain Access function
  91  *
  92 @verbatim
  93   ==============================================================================
  94                    ##### Backup Domain Access function #####
  95   ==============================================================================
  96
  97     [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
  98          and RTC backup registers) are protected against possible stray write accesses.
  99     [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
 100
 101 @endverbatim
 102   * @{
 103   */
 104
 105 /**
 106   * @brief  Deinitializes the PWR peripheral registers to their default reset values.
 107   * @param  None
 108   * @retval None
 109   */
 110 void PWR_DeInit(void)
 111 {
 112   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
 113   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
 114 }
 115
 116 /**
 117   * @brief  Enables or disables access to the RTC and backup registers.
 118   * @note   If the HSE divided by 32 is used as the RTC clock, the
 119   *         Backup Domain Access should be kept enabled.
 120   * @param  NewState: new state of the access to the RTC and backup registers.
 121   *         This parameter can be: ENABLE or DISABLE.
 122   * @retval None
 123   */
 124 void PWR_BackupAccessCmd(FunctionalState NewState)
 125 {
 126   /* Check the parameters */
 127   assert_param(IS_FUNCTIONAL_STATE(NewState));
 128   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
 129 }
 130
 131 /**
 132   * @}
 133   */
 134
 135 /** @defgroup PWR_Group2 PVD configuration functions
 136  *  @brief   PVD configuration functions
 137  *
 138 @verbatim
 139  ===============================================================================
 140                     ##### PVD configuration functions #####
 141   ==============================================================================
 142   [..]
 143   (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
 144       selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
 145   (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
 146       PVD threshold. This event is internally connected to the EXTI line16
 147       and can generate an interrupt if enabled through the EXTI registers.
 148   (+) The PVD is stopped in Standby mode.
 149
 150 @endverbatim
 151   * @{
 152   */
 153
 154 /**
 155   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
 156   * @param  PWR_PVDLevel: specifies the PVD detection level
 157   *         This parameter can be one of the following values:
 158   *             @arg PWR_PVDLevel_0: PVD detection level set to 2.18V
 159   *             @arg PWR_PVDLevel_1: PVD detection level set to 2.28V
 160   *             @arg PWR_PVDLevel_2: PVD detection level set to 2.38V
 161   *             @arg PWR_PVDLevel_3: PVD detection level set to 2.48V
 162   *             @arg PWR_PVDLevel_4: PVD detection level set to 2.58V
 163   *             @arg PWR_PVDLevel_5: PVD detection level set to 2.68V
 164   *             @arg PWR_PVDLevel_6: PVD detection level set to 2.78V
 165   *             @arg PWR_PVDLevel_7: PVD detection level set to 2.88V
 166   * @retval None
 167   */
 168 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
 169 {
 170   uint32_t tmpreg = 0;
 171
 172   /* Check the parameters */
 173   assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
 174
 175   tmpreg = PWR->CR;
 176
 177   /* Clear PLS[7:5] bits */
 178   tmpreg &= CR_PLS_MASK;
 179
 180   /* Set PLS[7:5] bits according to PWR_PVDLevel value */
 181   tmpreg |= PWR_PVDLevel;
 182
 183   /* Store the new value */
 184   PWR->CR = tmpreg;
 185 }
 186
 187 /**
 188   * @brief  Enables or disables the Power Voltage Detector(PVD).
 189   * @param  NewState: new state of the PVD.
 190   *         This parameter can be: ENABLE or DISABLE.
 191   * @retval None
 192   */
 193 void PWR_PVDCmd(FunctionalState NewState)
 194 {
 195   /* Check the parameters */
 196   assert_param(IS_FUNCTIONAL_STATE(NewState));
 197   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
 198 }
 199
 200 /**
 201   * @}
 202   */
 203
 204 /** @defgroup PWR_Group3 WakeUp pins configuration functions
 205  *  @brief   WakeUp pins configuration functions
 206  *
 207 @verbatim
 208  ===============================================================================
 209               ##### WakeUp pins configuration functions #####
 210  ===============================================================================
 211     [..]
 212     (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
 213         forced in input pull down configuration and are active on rising edges.
 214     (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
 215         WakeUp Pin 3 on PE.06.
 216
 217 @endverbatim
 218   * @{
 219   */
 220
 221 /**
 222   * @brief  Enables or disables the WakeUp Pin functionality.
 223   * @param  PWR_WakeUpPin: specifies the WakeUpPin.
 224   *         This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
 225   * @param  NewState: new state of the WakeUp Pin functionality.
 226   *         This parameter can be: ENABLE or DISABLE.
 227   * @retval None
 228   */
 229 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
 230 {
 231   /* Check the parameters */
 232   assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
 233   assert_param(IS_FUNCTIONAL_STATE(NewState));
 234
 235   if (NewState != DISABLE)
 236   {
 237     /* Enable the EWUPx pin */
 238     PWR->CSR |= PWR_WakeUpPin;
 239   }
 240   else
 241   {
 242     /* Disable the EWUPx pin */
 243     PWR->CSR &= ~PWR_WakeUpPin;
 244   }
 245 }
 246
 247 /**
 248   * @}
 249   */
 250
 251
 252 /** @defgroup PWR_Group4 Low Power modes configuration functions
 253  *  @brief   Low Power modes configuration functions
 254  *
 255 @verbatim
 256  ===============================================================================
 257               ##### Low Power modes configuration functions #####
 258   ==============================================================================
 259
 260     [..] The devices feature three low-power modes:
 261     (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
 262     (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
 263     (+) Standby mode: VCORE domain powered off
 264
 265   *** Sleep mode ***
 266   ==================
 267   [..]
 268     (+) Entry:
 269         (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
 270     (+) Exit:
 271         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
 272              controller (NVIC) can wake up the device from Sleep mode.
 273
 274   *** Stop mode ***
 275   =================
 276   [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
 277        and the HSE RC oscillators are disabled. Internal SRAM and register
 278        contents are preserved.
 279        The voltage regulator can be configured either in normal or low-power mode.
 280
 281     (+) Entry:
 282         (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
 283              function with regulator in LowPower or with Regulator ON.
 284     (+) Exit:
 285         (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
 286              or any internal IPs (I2C or UASRT) wakeup event.
 287
 288   *** Standby mode ***
 289   ====================
 290   [..] The Standby mode allows to achieve the lowest power consumption. It is based
 291        on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
 292        The VCORE domain is consequently powered off. The PLL, the HSI, and the HSE
 293        oscillator are also switched off. SRAM and register
 294        contents are lost except for the Backup domain (RTC registers, RTC backup
 295        registers and Standby circuitry).
 296
 297   [..] The voltage regulator is OFF.
 298
 299     (+) Entry:
 300         (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
 301     (+) Exit:
 302         (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
 303              tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
 304
 305   *** Auto-wakeup (AWU) from low-power mode ***
 306   =============================================
 307   [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
 308        event, a time-stamp event, or a comparator event, without depending on an
 309        external interrupt (Auto-wakeup mode).
 310
 311     (+) RTC auto-wakeup (AWU) from the Stop mode
 312         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
 313              (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
 314                    or Event modes) using the EXTI_Init() function.
 315              (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
 316              (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
 317                    and RTC_AlarmCmd() functions.
 318         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
 319              is necessary to:
 320              (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
 321                    or Event modes) using the EXTI_Init() function.
 322              (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
 323                    function.
 324              (+++) Configure the RTC to detect the tamper or time stamp event using the
 325                    RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
 326                    functions.
 327
 328     (+) RTC auto-wakeup (AWU) from the Standby mode
 329         (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
 330              (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
 331              (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
 332                    and RTC_AlarmCmd() functions.
 333         (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
 334              is necessary to:
 335              (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
 336                    function.
 337              (+++) Configure the RTC to detect the tamper or time stamp event using the
 338                    RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
 339                    functions.
 340
 341     (+) Comparator auto-wakeup (AWU) from the Stop mode
 342         (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
 343              (+++) Configure the correspondant comparator EXTI Line to be sensitive to
 344                    the selected edges (falling, rising or falling and rising)
 345                    (Interrupt or Event modes) using the EXTI_Init() function.
 346              (+++) Configure the comparator to generate the event.
 347
 348 @endverbatim
 349   * @{
 350   */
 351
 352 /**
 353   * @brief  Enters Sleep mode.
 354   * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
 355   * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
 356   *         This parameter can be one of the following values:
 357   *             @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
 358   *             @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
 359   * @retval None
 360   */
 361 void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
 362 {
 363   /* Check the parameters */
 364   assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
 365
 366   /* Clear SLEEPDEEP bit of Cortex System Control Register */
 367   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 368
 369   /* Select SLEEP mode entry -------------------------------------------------*/
 370   if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
 371   {
 372     /* Request Wait For Interrupt */
 373     __WFI();
 374   }
 375   else
 376   {
 377     /* Request Wait For Event */
 378     __WFE();
 379   }
 380 }
 381
 382 /**
 383   * @brief  Enters STOP mode.
 384   * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
 385   * @note   When exiting Stop mode by issuing an interrupt or a wakeup event,
 386   *         the HSI RC oscillator is selected as system clock.
 387   * @note   When the voltage regulator operates in low power mode, an additional
 388   *         startup delay is incurred when waking up from Stop mode.
 389   *         By keeping the internal regulator ON during Stop mode, the consumption
 390   *         is higher although the startup time is reduced.
 391   * @param  PWR_Regulator: specifies the regulator state in STOP mode.
 392   *         This parameter can be one of the following values:
 393   *             @arg PWR_Regulator_ON: STOP mode with regulator ON
 394   *             @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
 395   * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
 396   *         This parameter can be one of the following values:
 397   *             @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
 398   *             @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
 399   * @retval None
 400   */
 401 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 402 {
 403   uint32_t tmpreg = 0;
 404
 405   /* Check the parameters */
 406   assert_param(IS_PWR_REGULATOR(PWR_Regulator));
 407   assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
 408
 409   /* Select the regulator state in STOP mode ---------------------------------*/
 410   tmpreg = PWR->CR;
 411   /* Clear PDDS and LPDSR bits */
 412   tmpreg &= CR_DS_MASK;
 413
 414   /* Set LPDSR bit according to PWR_Regulator value */
 415   tmpreg |= PWR_Regulator;
 416
 417   /* Store the new value */
 418   PWR->CR = tmpreg;
 419
 420   /* Set SLEEPDEEP bit of Cortex System Control Register */
 421   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 422
 423   /* Select STOP mode entry --------------------------------------------------*/
 424   if(PWR_STOPEntry == PWR_STOPEntry_WFI)
 425   {
 426     /* Request Wait For Interrupt */
 427     __WFI();
 428   }
 429   else
 430   {
 431     /* Request Wait For Event */
 432     __WFE();
 433   }
 434   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 435   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 436 }
 437
 438 /**
 439   * @brief  Enters STANDBY mode.
 440   * @note   In Standby mode, all I/O pins are high impedance except for:
 441   * @note     Reset pad (still available)
 442   * @note     RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
 443   *           time-stamp, RTC Alarm out, or RTC clock calibration out.
 444   * @note     WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
 445   * @param  None
 446   * @retval None
 447   */
 448 void PWR_EnterSTANDBYMode(void)
 449 {
 450   /* Clear Wakeup flag */
 451   PWR->CR |= PWR_CR_CWUF;
 452
 453   /* Select STANDBY mode */
 454   PWR->CR |= PWR_CR_PDDS;
 455
 456   /* Set SLEEPDEEP bit of Cortex System Control Register */
 457   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 458
 459 /* This option is used to ensure that store operations are completed */
 460 #if defined ( __CC_ARM   )
 461   __force_stores();
 462 #endif
 463   /* Request Wait For Interrupt */
 464   __WFI();
 465 }
 466
 467 /**
 468   * @}
 469   */
 470
 471 /** @defgroup PWR_Group5 Flags management functions
 472  *  @brief   Flags management functions
 473  *
 474 @verbatim
 475  ===============================================================================
 476                     ##### Flags management functions #####
 477  ===============================================================================
 478
 479 @endverbatim
 480   * @{
 481   */
 482
 483 /**
 484   * @brief  Checks whether the specified PWR flag is set or not.
 485   * @param  PWR_FLAG: specifies the flag to check.
 486   *   This parameter can be one of the following values:
 487   *     @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
 488   *       was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B),
 489   *       RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
 490   *     @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
 491   *                       resumed from StandBy mode.
 492   *     @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
 493   *       by the PWR_PVDCmd() function.
 494   *     @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This
 495   *       flag indicates the state of the internal voltage reference, VREFINT.
 496   * @retval The new state of PWR_FLAG (SET or RESET).
 497   */
 498 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
 499 {
 500   FlagStatus bitstatus = RESET;
 501   /* Check the parameters */
 502   assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
 503
 504   if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
 505   {
 506     bitstatus = SET;
 507   }
 508   else
 509   {
 510     bitstatus = RESET;
 511   }
 512   /* Return the flag status */
 513   return bitstatus;
 514 }
 515
 516 /**
 517   * @brief  Clears the PWR's pending flags.
 518   * @param  PWR_FLAG: specifies the flag to clear.
 519   *   This parameter can be one of the following values:
 520   *     @arg PWR_FLAG_WU: Wake Up flag
 521   *     @arg PWR_FLAG_SB: StandBy flag
 522   * @retval None
 523   */
 524 void PWR_ClearFlag(uint32_t PWR_FLAG)
 525 {
 526   /* Check the parameters */
 527   assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
 528
 529   PWR->CR |=  PWR_FLAG << 2;
 530 }
 531
 532 /**
 533   * @}
 534   */
 535
 536 /**
 537   * @}
 538   */
 539
 540 /**
 541   * @}
 542   */
 543
 544 /**
 545   * @}
 546   */
 547
 548 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/