tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f30x.c
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    05-March-2014
   7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8   *          This file contains the system clock configuration for STM32F30x devices,
   9   *          and is generated by the clock configuration tool
  10   *          stm32f30x_Clock_Configuration_V1.0.0.xls
  11   *
  12   * 1.  This file provides two functions and one global variable to be called from
  13   *     user application:
  14   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  15   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  16   *                      depending on the configuration made in the clock xls tool.
  17   *                      This function is called at startup just after reset and
  18   *                      before branch to main program. This call is made inside
  19   *                      the "startup_stm32f30x.s" file.
  20   *
  21   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  22   *                                  by the user application to setup the SysTick
  23   *                                  timer or configure other parameters.
  24   *
  25   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  26   *                                 be called whenever the core clock is changed
  27   *                                 during program execution.
  28   *
  29   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  30   *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
  31   *    configure the system clock before to branch to main program.
  32   *
  33   * 3. If the system clock source selected by user fails to startup, the SystemInit()
  34   *    function will do nothing and HSI still used as system clock source. User can
  35   *    add some code to deal with this issue inside the SetSysClock() function.
  36   *
  37   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
  38   *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
  39   *    through PLL, and you are using different crystal you have to adapt the HSE
  40   *    value to your own configuration.
  41   *
  42   * 5. This file configures the system clock as follows:
  43   *-----------------------------------------------------------------------------
  44   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  45   *                                    | (external 8 MHz clock) | (internal 8 MHz)
  46   *                                    | 2- PLL_HSE_XTAL        |
  47   *                                    | (external 8 MHz xtal)  |
  48   *-----------------------------------------------------------------------------
  49   * SYSCLK(MHz)                        | 72                     | 64
  50   *-----------------------------------------------------------------------------
  51   * AHBCLK (MHz)                       | 72                     | 64
  52   *-----------------------------------------------------------------------------
  53   * APB1CLK (MHz)                      | 36                     | 32
  54   *-----------------------------------------------------------------------------
  55   * APB2CLK (MHz)                      | 72                     | 64
  56   *-----------------------------------------------------------------------------
  57   * USB capable (48 MHz precise clock) | YES                    | NO
  58   *-----------------------------------------------------------------------------
  59   ******************************************************************************
  60   * @attention
  61   *
  62   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  63   *
  64   * Redistribution and use in source and binary forms, with or without modification,
  65   * are permitted provided that the following conditions are met:
  66   *   1. Redistributions of source code must retain the above copyright notice,
  67   *      this list of conditions and the following disclaimer.
  68   *   2. Redistributions in binary form must reproduce the above copyright notice,
  69   *      this list of conditions and the following disclaimer in the documentation
  70   *      and/or other materials provided with the distribution.
  71   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  72   *      may be used to endorse or promote products derived from this software
  73   *      without specific prior written permission.
  74   *
  75   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  76   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  77   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  78   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  79   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  80   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  81   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  82   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  83   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  84   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  85   *
  86   ******************************************************************************
  87   */
  88
  89 /** @addtogroup CMSIS
  90   * @{
  91   */
  92
  93 /** @addtogroup stm32f30x_system
  94   * @{
  95   */
  96
  97 /** @addtogroup STM32F30x_System_Private_Includes
  98   * @{
  99   */
 100
 101 #include "stm32f30x.h"
 102
 103 /**
 104   * @}
 105   */
 106
 107 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
 108   * @{
 109   */
 110
 111 /**
 112   * @}
 113   */
 114
 115 /** @addtogroup STM32F30x_System_Private_Defines
 116   * @{
 117   */
 118
 119 /*!< Uncomment the following line if you need to relocate your vector Table in
 120      Internal SRAM. */
 121 /* #define VECT_TAB_SRAM */
 122 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
 123                                   This value must be a multiple of 0x200. */
 124 /**
 125   * @}
 126   */
 127
 128 /** @addtogroup STM32F30x_System_Private_Macros
 129   * @{
 130   */
 131
 132 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 133 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 134 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 135
 136 /**
 137   * @}
 138   */
 139
 140 /** @addtogroup STM32F30x_System_Private_Variables
 141   * @{
 142   */
 143
 144 uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
 145
 146 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 147
 148 /**
 149   * @}
 150   */
 151
 152 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
 153   * @{
 154   */
 155
 156 void SetSysClock(void);
 157
 158 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 159 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 160 #endif
 161
 162 uint8_t SetSysClock_PLL_HSI(void);
 163
 164 /**
 165   * @}
 166   */
 167
 168 /** @addtogroup STM32F30x_System_Private_Functions
 169   * @{
 170   */
 171
 172 /**
 173   * @brief  Setup the microcontroller system
 174   *         Initialize the Embedded Flash Interface, the PLL and update the
 175   *         SystemFrequency variable.
 176   * @param  None
 177   * @retval None
 178   */
 179 void SystemInit(void)
 180 {
 181   /* FPU settings ------------------------------------------------------------*/
 182   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 183     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 184   #endif
 185
 186   /* Reset the RCC clock configuration to the default reset state ------------*/
 187   /* Set HSION bit */
 188   RCC->CR |= (uint32_t)0x00000001;
 189
 190   /* Reset CFGR register */
 191   RCC->CFGR &= 0xF87FC00C;
 192
 193   /* Reset HSEON, CSSON and PLLON bits */
 194   RCC->CR &= (uint32_t)0xFEF6FFFF;
 195
 196   /* Reset HSEBYP bit */
 197   RCC->CR &= (uint32_t)0xFFFBFFFF;
 198
 199   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
 200   RCC->CFGR &= (uint32_t)0xFF80FFFF;
 201
 202   /* Reset PREDIV1[3:0] bits */
 203   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 204
 205   /* Reset USARTSW[1:0], I2CSW and TIMs bits */
 206   RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
 207
 208   /* Disable all interrupts */
 209   RCC->CIR = 0x00000000;
 210
 211   /* Configure the System clock source, PLL Multiplier and Divider factors,
 212      AHB/APBx prescalers and Flash settings */
 213   SetSysClock();
 214
 215   /* Configure the Vector Table location add offset address ------------------*/
 216 #ifdef VECT_TAB_SRAM
 217   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 218 #else
 219   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 220 #endif
 221 }
 222
 223 /**
 224    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 225   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 226   *         be used by the user application to setup the SysTick timer or configure
 227   *         other parameters.
 228   *
 229   * @note   Each time the core clock (HCLK) changes, this function must be called
 230   *         to update SystemCoreClock variable value. Otherwise, any configuration
 231   *         based on this variable will be incorrect.
 232   *
 233   * @note   - The system frequency computed by this function is not the real
 234   *           frequency in the chip. It is calculated based on the predefined
 235   *           constant and the selected clock source:
 236   *
 237   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 238   *
 239   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 240   *
 241   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 242   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 243   *
 244   *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
 245   *             8 MHz) but the real value may vary depending on the variations
 246   *             in voltage and temperature.
 247   *
 248   *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
 249   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 250   *              frequency of the crystal used. Otherwise, this function may
 251   *              have wrong result.
 252   *
 253   *         - The result of this function could be not correct when using fractional
 254   *           value for HSE crystal.
 255   *
 256   * @param  None
 257   * @retval None
 258   */
 259 void SystemCoreClockUpdate (void)
 260 {
 261   uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
 262
 263   /* Get SYSCLK source -------------------------------------------------------*/
 264   tmp = RCC->CFGR & RCC_CFGR_SWS;
 265
 266   switch (tmp)
 267   {
 268     case 0x00:  /* HSI used as system clock */
 269       SystemCoreClock = HSI_VALUE;
 270       break;
 271     case 0x04:  /* HSE used as system clock */
 272       SystemCoreClock = HSE_VALUE;
 273       break;
 274     case 0x08:  /* PLL used as system clock */
 275       /* Get PLL clock source and multiplication factor ----------------------*/
 276       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 277       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 278       pllmull = ( pllmull >> 18) + 2;
 279
 280       if (pllsource == 0x00)
 281       {
 282         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 283         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 284       }
 285       else
 286       {
 287         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 288         /* HSE oscillator clock selected as PREDIV1 clock entry */
 289         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
 290       }
 291       break;
 292     default: /* HSI used as system clock */
 293       SystemCoreClock = HSI_VALUE;
 294       break;
 295   }
 296   /* Compute HCLK clock frequency ----------------*/
 297   /* Get HCLK prescaler */
 298   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 299   /* HCLK clock frequency */
 300   SystemCoreClock >>= tmp;
 301 }
 302
 303 /**
 304   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 305   *               AHB/APBx prescalers and Flash settings
 306   * @note   This function should be called only once the RCC clock configuration
 307   *         is reset to the default reset state (done in SystemInit() function).
 308   * @param  None
 309   * @retval None
 310   */
 311 void SetSysClock(void)
 312 {
 313   /* 1- Try to start with HSE and external clock */
 314 #if USE_PLL_HSE_EXTC != 0
 315   if (SetSysClock_PLL_HSE(1) == 0)
 316 #endif
 317   {
 318     /* 2- If fail try to start with HSE and external xtal */
 319     #if USE_PLL_HSE_XTAL != 0
 320     if (SetSysClock_PLL_HSE(0) == 0)
 321     #endif
 322     {
 323       /* 3- If fail start with HSI clock */
 324       if (SetSysClock_PLL_HSI() == 0)
 325       {
 326         while(1)
 327         {
 328           // [TODO] Put something here to tell the user that a problem occured...
 329         }
 330       }
 331     }
 332   }
 333
 334   /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
 335   /*
 336   // Enable GPIOA clock
 337   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
 338   // Configure MCO pin (PA8)
 339   GPIO_InitTypeDef GPIO_InitStructure;
 340   GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_8;
 341   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
 342   GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;
 343   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
 344   GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
 345   GPIO_Init(GPIOA, &GPIO_InitStructure);
 346   // Select the clock to output
 347   RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
 348   */
 349 }
 350
 351 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 352 /******************************************************************************/
 353 /*            PLL (clocked by HSE) used as System clock source                */
 354 /******************************************************************************/
 355 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 356 {
 357   __IO uint32_t StartUpCounter = 0;
 358   __IO uint32_t HSEStatus = 0;
 359
 360   /* Bypass HSE: can be done only if HSE is OFF */
 361   RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
 362   if (bypass != 0)
 363   {
 364     RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
 365   }
 366   else
 367   {
 368     RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
 369   }
 370
 371   /* Enable HSE */
 372   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 373
 374   /* Wait till HSE is ready */
 375   do
 376   {
 377     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 378     StartUpCounter++;
 379   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 380
 381   /* Check if HSE has started correctly */
 382   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 383   {
 384     /* Enable prefetch buffer and set flash latency
 385        0WS for 0  < SYSCLK <= 24 MHz
 386        1WS for 24 < SYSCLK <= 48 MHz
 387        2WS for 48 < SYSCLK <= 72 MHz */
 388     FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
 389
 390     /* Warning: values are obtained with external xtal or clock = 8 MHz */
 391     /* SYSCLK = 72 MHz (8 MHz * 9) */
 392     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 393     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9
 394                           | RCC_CFGR_HPRE_DIV1    /* HCLK   = 72 MHz */
 395                           | RCC_CFGR_PPRE2_DIV1   /* PCLK2  = 72 MHz */
 396                           | RCC_CFGR_PPRE1_DIV2); /* PCLK1  = 36 MHz */
 397                                                   /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */
 398
 399     /* Enable PLL */
 400     RCC->CR |= RCC_CR_PLLON;
 401
 402     /* Wait till PLL is ready */
 403     while((RCC->CR & RCC_CR_PLLRDY) == 0)
 404     {
 405     }
 406
 407     /* Select PLL as system clock source */
 408     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 409     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
 410
 411     /* Wait till PLL is used as system clock source */
 412     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
 413     {
 414     }
 415
 416     return 1; // OK
 417   }
 418   else
 419   {
 420     return 0; // FAIL
 421   }
 422 }
 423 #endif
 424
 425 /******************************************************************************/
 426 /*            PLL (clocked by HSI) used as System clock source                */
 427 /******************************************************************************/
 428 uint8_t SetSysClock_PLL_HSI(void)
 429 {
 430   /* At this stage the HSI is already enabled and used as System clock source */
 431
 432   /* Enable prefetch buffer and set flash latency
 433      0WS for 0  < SYSCLK <= 24 MHz
 434      1WS for 24 < SYSCLK <= 48 MHz
 435      2WS for 48 < SYSCLK <= 72 MHz */
 436   FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
 437
 438   /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */
 439   RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 440   RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16
 441                         | RCC_CFGR_HPRE_DIV1    /* HCLK   = 64 MHz */
 442                         | RCC_CFGR_PPRE2_DIV1   /* PCLK2  = 64 MHz */
 443                         | RCC_CFGR_PPRE1_DIV2); /* PCLK1  = 32 MHz */
 444                                                 /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */
 445
 446   /* Enable PLL */
 447   RCC->CR |= RCC_CR_PLLON;
 448
 449   /* Wait till PLL is ready */
 450   while((RCC->CR & RCC_CR_PLLRDY) == 0)
 451   {
 452   }
 453
 454   /* Select PLL as system clock source */
 455   RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 456   RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
 457
 458   /* Wait till PLL is used as system clock source */
 459   while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
 460   {
 461   }
 462
 463   return 1; // OK
 464 }
 465
 466 /**
 467   * @}
 468   */
 469
 470 /**
 471   * @}
 472   */
 473
 474 /**
 475   * @}
 476   */
 477
 478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/