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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F4 / stm32f4xx_hal_eth.c
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_eth.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 19-June-2014
7 * @brief ETH HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Ethernet (ETH) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
21 ETH_HandleTypeDef heth;
22
23 (#)Fill parameters of Init structure in heth handle
24
25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
26
27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
28 (##) Enable the Ethernet interface clock using
29 (+++) __ETHMAC_CLK_ENABLE();
30 (+++) __ETHMACTX_CLK_ENABLE();
31 (+++) __ETHMACRX_CLK_ENABLE();
32
33 (##) Initialize the related GPIO clocks
34 (##) Configure Ethernet pin-out
35 (##) Configure Ethernet NVIC interrupt (IT mode)
36
37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
40
41 (#)Enable MAC and DMA transmission and reception:
42 (##) HAL_ETH_Start();
43
44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
45 the frame to MAC TX FIFO:
46 (##) HAL_ETH_TransmitFrame();
47
48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
49 frame parameters
50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
51
52 (#) Get a received frame when an ETH RX interrupt occurs:
53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
54
55 (#) Communicate with external PHY device:
56 (##) Read a specific register from the PHY
57 HAL_ETH_ReadPHYRegister();
58 (##) Write data to a specific RHY register:
59 HAL_ETH_WritePHYRegister();
60
61 (#) Configure the Ethernet MAC after ETH peripheral initialization
62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
63
64 (#) Configure the Ethernet DMA after ETH peripheral initialization
65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
66
67 @endverbatim
68 ******************************************************************************
69 * @attention
70 *
71 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
72 *
73 * Redistribution and use in source and binary forms, with or without modification,
74 * are permitted provided that the following conditions are met:
75 * 1. Redistributions of source code must retain the above copyright notice,
76 * this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright notice,
78 * this list of conditions and the following disclaimer in the documentation
79 * and/or other materials provided with the distribution.
80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
81 * may be used to endorse or promote products derived from this software
82 * without specific prior written permission.
83 *
84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
94 *
95 ******************************************************************************
96 */
97
98 /* Includes ------------------------------------------------------------------*/
99 #include "stm32f4xx_hal.h"
100
101 /** @addtogroup STM32F4xx_HAL_Driver
102 * @{
103 */
104
105 /** @defgroup ETH
106 * @brief ETH HAL module driver
107 * @{
108 */
109
110 #ifdef HAL_ETH_MODULE_ENABLED
111
112 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
113
114 /* Private typedef -----------------------------------------------------------*/
115 /* Private define ------------------------------------------------------------*/
116 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
117 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
118
119 /* Private macro -------------------------------------------------------------*/
120 /* Private variables ---------------------------------------------------------*/
121 /* Private function prototypes -----------------------------------------------*/
122 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
123 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
124 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
125 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
126 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
127 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
128 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
129 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
130 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
131 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
132 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
133
134 /* Private functions ---------------------------------------------------------*/
135
136 /** @defgroup ETH_Private_Functions
137 * @{
138 */
139
140 /** @defgroup ETH_Group1 Initialization and de-initialization functions
141 * @brief Initialization and Configuration functions
142 *
143 @verbatim
144 ===============================================================================
145 ##### Initialization and de-initialization functions #####
146 ===============================================================================
147 [..] This section provides functions allowing to:
148 (+) Initialize and configure the Ethernet peripheral
149 (+) De-initialize the Ethernet peripheral
150
151 @endverbatim
152 * @{
153 */
154
155 /**
156 * @brief Initializes the Ethernet MAC and DMA according to default
157 * parameters.
158 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
159 * the configuration information for ETHERNET module
160 * @retval HAL status
161 */
162 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
163 {
164 uint32_t tmpreg = 0, phyreg = 0;
165 uint32_t hclk = 60000000;
166 uint32_t tickstart = 0;
167 uint32_t err = ETH_SUCCESS;
168
169 /* Check the ETH peripheral state */
170 if(heth == HAL_NULL)
171 {
172 return HAL_ERROR;
173 }
174
175 /* Check parameters */
176 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
177 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
178 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
179 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
180
181 if(heth->State == HAL_ETH_STATE_RESET)
182 {
183 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
184 HAL_ETH_MspInit(heth);
185 }
186
187 /* Enable SYSCFG Clock */
188 __SYSCFG_CLK_ENABLE();
189
190 /* Select MII or RMII Mode*/
191 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
192 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
193
194 /* Ethernet Software reset */
195 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
196 /* After reset all the registers holds their respective reset values */
197 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
198
199 /* Wait for software reset */
200 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
201 {
202 }
203
204 /*-------------------------------- MAC Initialization ----------------------*/
205 /* Get the ETHERNET MACMIIAR value */
206 tmpreg = (heth->Instance)->MACMIIAR;
207 /* Clear CSR Clock Range CR[2:0] bits */
208 tmpreg &= MACMIIAR_CR_MASK;
209
210 /* Get hclk frequency value */
211 hclk = HAL_RCC_GetHCLKFreq();
212
213 /* Set CR bits depending on hclk value */
214 if((hclk >= 20000000)&&(hclk < 35000000))
215 {
216 /* CSR Clock Range between 20-35 MHz */
217 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
218 }
219 else if((hclk >= 35000000)&&(hclk < 60000000))
220 {
221 /* CSR Clock Range between 35-60 MHz */
222 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
223 }
224 else if((hclk >= 60000000)&&(hclk < 100000000))
225 {
226 /* CSR Clock Range between 60-100 MHz */
227 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
228 }
229 else if((hclk >= 100000000)&&(hclk < 150000000))
230 {
231 /* CSR Clock Range between 100-150 MHz */
232 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
233 }
234 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
235 {
236 /* CSR Clock Range between 150-168 MHz */
237 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
238 }
239
240 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
241 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
242
243 /*-------------------- PHY initialization and configuration ----------------*/
244 /* Put the PHY in reset mode */
245 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
246 {
247 /* In case of write timeout */
248 err = ETH_ERROR;
249
250 /* Config MAC and DMA */
251 ETH_MACDMAConfig(heth, err);
252
253 /* Set the ETH peripheral state to READY */
254 heth->State = HAL_ETH_STATE_READY;
255
256 /* Return HAL_ERROR */
257 return HAL_ERROR;
258 }
259
260 /* Delay to assure PHY reset */
261 HAL_Delay(PHY_RESET_DELAY);
262
263 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
264 {
265 /* Get tick */
266 tickstart = HAL_GetTick();
267
268 /* We wait for linked status */
269 do
270 {
271 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
272
273 /* Check for the Timeout */
274 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
275 {
276 /* In case of write timeout */
277 err = ETH_ERROR;
278
279 /* Config MAC and DMA */
280 ETH_MACDMAConfig(heth, err);
281
282 heth->State= HAL_ETH_STATE_READY;
283
284 /* Process Unlocked */
285 __HAL_UNLOCK(heth);
286
287 return HAL_TIMEOUT;
288 }
289 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
290
291
292 /* Enable Auto-Negotiation */
293 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
294 {
295 /* In case of write timeout */
296 err = ETH_ERROR;
297
298 /* Config MAC and DMA */
299 ETH_MACDMAConfig(heth, err);
300
301 /* Set the ETH peripheral state to READY */
302 heth->State = HAL_ETH_STATE_READY;
303
304 /* Return HAL_ERROR */
305 return HAL_ERROR;
306 }
307
308 /* Get tick */
309 tickstart = HAL_GetTick();
310
311 /* Wait until the auto-negotiation will be completed */
312 do
313 {
314 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
315
316 /* Check for the Timeout */
317 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
318 {
319 /* In case of write timeout */
320 err = ETH_ERROR;
321
322 /* Config MAC and DMA */
323 ETH_MACDMAConfig(heth, err);
324
325 heth->State= HAL_ETH_STATE_READY;
326
327 /* Process Unlocked */
328 __HAL_UNLOCK(heth);
329
330 return HAL_TIMEOUT;
331 }
332
333 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
334
335 /* Read the result of the auto-negotiation */
336 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
337 {
338 /* In case of write timeout */
339 err = ETH_ERROR;
340
341 /* Config MAC and DMA */
342 ETH_MACDMAConfig(heth, err);
343
344 /* Set the ETH peripheral state to READY */
345 heth->State = HAL_ETH_STATE_READY;
346
347 /* Return HAL_ERROR */
348 return HAL_ERROR;
349 }
350
351 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
352 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
353 {
354 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
355 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
356 }
357 else
358 {
359 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
360 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
361 }
362 /* Configure the MAC with the speed fixed by the auto-negotiation process */
363 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
364 {
365 /* Set Ethernet speed to 10M following the auto-negotiation */
366 (heth->Init).Speed = ETH_SPEED_10M;
367 }
368 else
369 {
370 /* Set Ethernet speed to 100M following the auto-negotiation */
371 (heth->Init).Speed = ETH_SPEED_100M;
372 }
373 }
374 else /* AutoNegotiation Disable */
375 {
376 /* Check parameters */
377 assert_param(IS_ETH_SPEED(heth->Init.Speed));
378 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
379
380 /* Set MAC Speed and Duplex Mode */
381 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
382 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
383 {
384 /* In case of write timeout */
385 err = ETH_ERROR;
386
387 /* Config MAC and DMA */
388 ETH_MACDMAConfig(heth, err);
389
390 /* Set the ETH peripheral state to READY */
391 heth->State = HAL_ETH_STATE_READY;
392
393 /* Return HAL_ERROR */
394 return HAL_ERROR;
395 }
396
397 /* Delay to assure PHY configuration */
398 HAL_Delay(PHY_CONFIG_DELAY);
399 }
400
401 /* Config MAC and DMA */
402 ETH_MACDMAConfig(heth, err);
403
404 /* Set ETH HAL State to Ready */
405 heth->State= HAL_ETH_STATE_READY;
406
407 /* Return function status */
408 return HAL_OK;
409 }
410
411 /**
412 * @brief De-Initializes the ETH peripheral.
413 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
414 * the configuration information for ETHERNET module
415 * @retval HAL status
416 */
417 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
418 {
419 /* Set the ETH peripheral state to BUSY */
420 heth->State = HAL_ETH_STATE_BUSY;
421
422 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
423 HAL_ETH_MspDeInit(heth);
424
425 /* Set ETH HAL state to Disabled */
426 heth->State= HAL_ETH_STATE_RESET;
427
428 /* Release Lock */
429 __HAL_UNLOCK(heth);
430
431 /* Return function status */
432 return HAL_OK;
433 }
434
435 /**
436 * @brief Initializes the DMA Tx descriptors in chain mode.
437 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
438 * the configuration information for ETHERNET module
439 * @param DMATxDescTab: Pointer to the first Tx desc list
440 * @param TxBuff: Pointer to the first TxBuffer list
441 * @param TxBuffCount: Number of the used Tx desc in the list
442 * @retval HAL status
443 */
444 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
445 {
446 uint32_t i = 0;
447 ETH_DMADescTypeDef *dmatxdesc;
448
449 /* Process Locked */
450 __HAL_LOCK(heth);
451
452 /* Set the ETH peripheral state to BUSY */
453 heth->State = HAL_ETH_STATE_BUSY;
454
455 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
456 heth->TxDesc = DMATxDescTab;
457
458 /* Fill each DMATxDesc descriptor with the right values */
459 for(i=0; i < TxBuffCount; i++)
460 {
461 /* Get the pointer on the ith member of the Tx Desc list */
462 dmatxdesc = DMATxDescTab + i;
463
464 /* Set Second Address Chained bit */
465 dmatxdesc->Status = ETH_DMATXDESC_TCH;
466
467 /* Set Buffer1 address pointer */
468 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
469
470 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
471 {
472 /* Set the DMA Tx descriptors checksum insertion */
473 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
474 }
475
476 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
477 if(i < (TxBuffCount-1))
478 {
479 /* Set next descriptor address register with next descriptor base address */
480 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
481 }
482 else
483 {
484 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
485 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
486 }
487 }
488
489 /* Set Transmit Descriptor List Address Register */
490 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
491
492 /* Set ETH HAL State to Ready */
493 heth->State= HAL_ETH_STATE_READY;
494
495 /* Process Unlocked */
496 __HAL_UNLOCK(heth);
497
498 /* Return function status */
499 return HAL_OK;
500 }
501
502 /**
503 * @brief Initializes the DMA Rx descriptors in chain mode.
504 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
505 * the configuration information for ETHERNET module
506 * @param DMARxDescTab: Pointer to the first Rx desc list
507 * @param RxBuff: Pointer to the first RxBuffer list
508 * @param RxBuffCount: Number of the used Rx desc in the list
509 * @retval HAL status
510 */
511 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
512 {
513 uint32_t i = 0;
514 ETH_DMADescTypeDef *DMARxDesc;
515
516 /* Process Locked */
517 __HAL_LOCK(heth);
518
519 /* Set the ETH peripheral state to BUSY */
520 heth->State = HAL_ETH_STATE_BUSY;
521
522 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
523 heth->RxDesc = DMARxDescTab;
524
525 /* Fill each DMARxDesc descriptor with the right values */
526 for(i=0; i < RxBuffCount; i++)
527 {
528 /* Get the pointer on the ith member of the Rx Desc list */
529 DMARxDesc = DMARxDescTab+i;
530
531 /* Set Own bit of the Rx descriptor Status */
532 DMARxDesc->Status = ETH_DMARXDESC_OWN;
533
534 /* Set Buffer1 size and Second Address Chained bit */
535 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
536
537 /* Set Buffer1 address pointer */
538 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
539
540 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
541 {
542 /* Enable Ethernet DMA Rx Descriptor interrupt */
543 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
544 }
545
546 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
547 if(i < (RxBuffCount-1))
548 {
549 /* Set next descriptor address register with next descriptor base address */
550 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
551 }
552 else
553 {
554 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
555 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
556 }
557 }
558
559 /* Set Receive Descriptor List Address Register */
560 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
561
562 /* Set ETH HAL State to Ready */
563 heth->State= HAL_ETH_STATE_READY;
564
565 /* Process Unlocked */
566 __HAL_UNLOCK(heth);
567
568 /* Return function status */
569 return HAL_OK;
570 }
571
572 /**
573 * @brief Initializes the ETH MSP.
574 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
575 * the configuration information for ETHERNET module
576 * @retval None
577 */
578 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
579 {
580 /* NOTE : This function Should not be modified, when the callback is needed,
581 the HAL_ETH_MspInit could be implemented in the user file
582 */
583 }
584
585 /**
586 * @brief DeInitializes ETH MSP.
587 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
588 * the configuration information for ETHERNET module
589 * @retval None
590 */
591 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
592 {
593 /* NOTE : This function Should not be modified, when the callback is needed,
594 the HAL_ETH_MspDeInit could be implemented in the user file
595 */
596 }
597
598 /**
599 * @}
600 */
601
602 /** @defgroup ETH_Group2 IO operation functions
603 * @brief Data transfers functions
604 *
605 @verbatim
606 ==============================================================================
607 ##### IO operation functions #####
608 ==============================================================================
609 [..] This section provides functions allowing to:
610 (+) Transmit a frame
611 HAL_ETH_TransmitFrame();
612 (+) Receive a frame
613 HAL_ETH_GetReceivedFrame();
614 HAL_ETH_GetReceivedFrame_IT();
615 (+) Read from an External PHY register
616 HAL_ETH_ReadPHYRegister();
617 (+) Write to an External PHY register
618 HAL_ETH_WritePHYRegister();
619
620 @endverbatim
621
622 * @{
623 */
624
625 /**
626 * @brief Sends an Ethernet frame.
627 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
628 * the configuration information for ETHERNET module
629 * @param FrameLength: Amount of data to be sent
630 * @retval HAL status
631 */
632 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
633 {
634 uint32_t bufcount = 0, size = 0, i = 0;
635
636 /* Process Locked */
637 __HAL_LOCK(heth);
638
639 /* Set the ETH peripheral state to BUSY */
640 heth->State = HAL_ETH_STATE_BUSY;
641
642 if (FrameLength == 0)
643 {
644 /* Set ETH HAL state to READY */
645 heth->State = HAL_ETH_STATE_READY;
646
647 /* Process Unlocked */
648 __HAL_UNLOCK(heth);
649
650 return HAL_ERROR;
651 }
652
653 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
654 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
655 {
656 /* OWN bit set */
657 heth->State = HAL_ETH_STATE_BUSY_TX;
658
659 /* Process Unlocked */
660 __HAL_UNLOCK(heth);
661
662 return HAL_ERROR;
663 }
664
665 /* Get the number of needed Tx buffers for the current frame */
666 if (FrameLength > ETH_TX_BUF_SIZE)
667 {
668 bufcount = FrameLength/ETH_TX_BUF_SIZE;
669 if (FrameLength % ETH_TX_BUF_SIZE)
670 {
671 bufcount++;
672 }
673 }
674 else
675 {
676 bufcount = 1;
677 }
678 if (bufcount == 1)
679 {
680 /* Set LAST and FIRST segment */
681 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
682 /* Set frame size */
683 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
684 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
685 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
686 /* Point to next descriptor */
687 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
688 }
689 else
690 {
691 for (i=0; i< bufcount; i++)
692 {
693 /* Clear FIRST and LAST segment bits */
694 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
695
696 if (i == 0)
697 {
698 /* Setting the first segment bit */
699 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
700 }
701
702 /* Program size */
703 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
704
705 if (i == (bufcount-1))
706 {
707 /* Setting the last segment bit */
708 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
709 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
710 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
711 }
712
713 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
714 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
715 /* point to next descriptor */
716 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
717 }
718 }
719
720 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
721 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
722 {
723 /* Clear TBUS ETHERNET DMA flag */
724 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
725 /* Resume DMA transmission*/
726 (heth->Instance)->DMATPDR = 0;
727 }
728
729 /* Set ETH HAL State to Ready */
730 heth->State = HAL_ETH_STATE_READY;
731
732 /* Process Unlocked */
733 __HAL_UNLOCK(heth);
734
735 /* Return function status */
736 return HAL_OK;
737 }
738
739 /**
740 * @brief Checks for received frames.
741 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
742 * the configuration information for ETHERNET module
743 * @retval HAL status
744 */
745 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
746 {
747 uint32_t framelength = 0;
748
749 /* Process Locked */
750 __HAL_LOCK(heth);
751
752 /* Check the ETH state to BUSY */
753 heth->State = HAL_ETH_STATE_BUSY;
754
755 /* Check if segment is not owned by DMA */
756 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
757 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
758 {
759 /* Check if last segment */
760 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
761 {
762 /* increment segment count */
763 (heth->RxFrameInfos).SegCount++;
764
765 /* Check if last segment is first segment: one segment contains the frame */
766 if ((heth->RxFrameInfos).SegCount == 1)
767 {
768 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
769 }
770
771 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
772
773 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
774 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
775 heth->RxFrameInfos.length = framelength;
776
777 /* Get the address of the buffer start address */
778 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
779 /* point to next descriptor */
780 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
781
782 /* Set HAL State to Ready */
783 heth->State = HAL_ETH_STATE_READY;
784
785 /* Process Unlocked */
786 __HAL_UNLOCK(heth);
787
788 /* Return function status */
789 return HAL_OK;
790 }
791 /* Check if first segment */
792 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
793 {
794 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
795 (heth->RxFrameInfos).LSRxDesc = HAL_NULL;
796 (heth->RxFrameInfos).SegCount = 1;
797 /* Point to next descriptor */
798 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
799 }
800 /* Check if intermediate segment */
801 else
802 {
803 (heth->RxFrameInfos).SegCount++;
804 /* Point to next descriptor */
805 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
806 }
807 }
808
809 /* Set ETH HAL State to Ready */
810 heth->State = HAL_ETH_STATE_READY;
811
812 /* Process Unlocked */
813 __HAL_UNLOCK(heth);
814
815 /* Return function status */
816 return HAL_ERROR;
817 }
818
819 /**
820 * @brief Gets the Received frame in interrupt mode.
821 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
822 * the configuration information for ETHERNET module
823 * @retval HAL status
824 */
825 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
826 {
827 uint32_t descriptorscancounter = 0;
828
829 /* Process Locked */
830 __HAL_LOCK(heth);
831
832 /* Set ETH HAL State to BUSY */
833 heth->State = HAL_ETH_STATE_BUSY;
834
835 /* Scan descriptors owned by CPU */
836 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
837 {
838 /* Just for security */
839 descriptorscancounter++;
840
841 /* Check if first segment in frame */
842 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
843 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
844 {
845 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
846 heth->RxFrameInfos.SegCount = 1;
847 /* Point to next descriptor */
848 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
849 }
850 /* Check if intermediate segment */
851 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
852 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
853 {
854 /* Increment segment count */
855 (heth->RxFrameInfos.SegCount)++;
856 /* Point to next descriptor */
857 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
858 }
859 /* Should be last segment */
860 else
861 {
862 /* Last segment */
863 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
864
865 /* Increment segment count */
866 (heth->RxFrameInfos.SegCount)++;
867
868 /* Check if last segment is first segment: one segment contains the frame */
869 if ((heth->RxFrameInfos.SegCount) == 1)
870 {
871 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
872 }
873
874 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
875 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
876
877 /* Get the address of the buffer start address */
878 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
879
880 /* Point to next descriptor */
881 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
882
883 /* Set HAL State to Ready */
884 heth->State = HAL_ETH_STATE_READY;
885
886 /* Process Unlocked */
887 __HAL_UNLOCK(heth);
888
889 /* Return function status */
890 return HAL_OK;
891 }
892 }
893
894 /* Set HAL State to Ready */
895 heth->State = HAL_ETH_STATE_READY;
896
897 /* Process Unlocked */
898 __HAL_UNLOCK(heth);
899
900 /* Return function status */
901 return HAL_ERROR;
902 }
903
904 /**
905 * @brief This function handles ETH interrupt request.
906 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
907 * the configuration information for ETHERNET module
908 * @retval HAL status
909 */
910 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
911 {
912 /* Frame received */
913 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
914 {
915 /* Receive complete callback */
916 HAL_ETH_RxCpltCallback(heth);
917
918 /* Clear the Eth DMA Rx IT pending bits */
919 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
920
921 /* Set HAL State to Ready */
922 heth->State = HAL_ETH_STATE_READY;
923
924 /* Process Unlocked */
925 __HAL_UNLOCK(heth);
926
927 }
928 /* Frame transmitted */
929 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
930 {
931 /* Transfer complete callback */
932 HAL_ETH_TxCpltCallback(heth);
933
934 /* Clear the Eth DMA Tx IT pending bits */
935 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
936
937 /* Set HAL State to Ready */
938 heth->State = HAL_ETH_STATE_READY;
939
940 /* Process Unlocked */
941 __HAL_UNLOCK(heth);
942 }
943
944 /* Clear the interrupt flags */
945 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
946
947 /* ETH DMA Error */
948 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
949 {
950 /* Ethernet Error callback */
951 HAL_ETH_ErrorCallback(heth);
952
953 /* Clear the interrupt flags */
954 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
955
956 /* Set HAL State to Ready */
957 heth->State = HAL_ETH_STATE_READY;
958
959 /* Process Unlocked */
960 __HAL_UNLOCK(heth);
961 }
962 }
963
964 /**
965 * @brief Tx Transfer completed callbacks.
966 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
967 * the configuration information for ETHERNET module
968 * @retval None
969 */
970 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
971 {
972 /* NOTE : This function Should not be modified, when the callback is needed,
973 the HAL_ETH_TxCpltCallback could be implemented in the user file
974 */
975 }
976
977 /**
978 * @brief Rx Transfer completed callbacks.
979 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
980 * the configuration information for ETHERNET module
981 * @retval None
982 */
983 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
984 {
985 /* NOTE : This function Should not be modified, when the callback is needed,
986 the HAL_ETH_TxCpltCallback could be implemented in the user file
987 */
988 }
989
990 /**
991 * @brief Ethernet transfer error callbacks
992 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
993 * the configuration information for ETHERNET module
994 * @retval None
995 */
996 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
997 {
998 /* NOTE : This function Should not be modified, when the callback is needed,
999 the HAL_ETH_TxCpltCallback could be implemented in the user file
1000 */
1001 }
1002
1003 /**
1004 * @brief Reads a PHY register
1005 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1006 * the configuration information for ETHERNET module
1007 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
1008 * This parameter can be one of the following values:
1009 * PHY_BCR: Transceiver Basic Control Register,
1010 * PHY_BSR: Transceiver Basic Status Register.
1011 * More PHY register could be read depending on the used PHY
1012 * @param RegValue: PHY register value
1013 * @retval HAL status
1014 */
1015 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
1016 {
1017 uint32_t tmpreg = 0;
1018 uint32_t tickstart = 0;
1019
1020 /* Check parameters */
1021 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1022
1023 /* Check the ETH peripheral state */
1024 if(heth->State == HAL_ETH_STATE_BUSY_RD)
1025 {
1026 return HAL_BUSY;
1027 }
1028 /* Set ETH HAL State to BUSY_RD */
1029 heth->State = HAL_ETH_STATE_BUSY_RD;
1030
1031 /* Get the ETHERNET MACMIIAR value */
1032 tmpreg = heth->Instance->MACMIIAR;
1033
1034 /* Keep only the CSR Clock Range CR[2:0] bits value */
1035 tmpreg &= ~MACMIIAR_CR_MASK;
1036
1037 /* Prepare the MII address register value */
1038 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1039 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1040 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
1041 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1042
1043 /* Write the result value into the MII Address register */
1044 heth->Instance->MACMIIAR = tmpreg;
1045
1046 /* Get tick */
1047 tickstart = HAL_GetTick();
1048
1049 /* Check for the Busy flag */
1050 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1051 {
1052 /* Check for the Timeout */
1053 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
1054 {
1055 heth->State= HAL_ETH_STATE_READY;
1056
1057 /* Process Unlocked */
1058 __HAL_UNLOCK(heth);
1059
1060 return HAL_TIMEOUT;
1061 }
1062
1063 tmpreg = heth->Instance->MACMIIAR;
1064 }
1065
1066 /* Get MACMIIDR value */
1067 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
1068
1069 /* Set ETH HAL State to READY */
1070 heth->State = HAL_ETH_STATE_READY;
1071
1072 /* Return function status */
1073 return HAL_OK;
1074 }
1075
1076 /**
1077 * @brief Writes to a PHY register.
1078 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1079 * the configuration information for ETHERNET module
1080 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
1081 * This parameter can be one of the following values:
1082 * PHY_BCR: Transceiver Control Register.
1083 * More PHY register could be written depending on the used PHY
1084 * @param RegValue: the value to write
1085 * @retval HAL status
1086 */
1087 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
1088 {
1089 uint32_t tmpreg = 0;
1090 uint32_t tickstart = 0;
1091
1092 /* Check parameters */
1093 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1094
1095 /* Check the ETH peripheral state */
1096 if(heth->State == HAL_ETH_STATE_BUSY_WR)
1097 {
1098 return HAL_BUSY;
1099 }
1100 /* Set ETH HAL State to BUSY_WR */
1101 heth->State = HAL_ETH_STATE_BUSY_WR;
1102
1103 /* Get the ETHERNET MACMIIAR value */
1104 tmpreg = heth->Instance->MACMIIAR;
1105
1106 /* Keep only the CSR Clock Range CR[2:0] bits value */
1107 tmpreg &= ~MACMIIAR_CR_MASK;
1108
1109 /* Prepare the MII register address value */
1110 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1111 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1112 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
1113 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1114
1115 /* Give the value to the MII data register */
1116 heth->Instance->MACMIIDR = (uint16_t)RegValue;
1117
1118 /* Write the result value into the MII Address register */
1119 heth->Instance->MACMIIAR = tmpreg;
1120
1121 /* Get tick */
1122 tickstart = HAL_GetTick();
1123
1124 /* Check for the Busy flag */
1125 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1126 {
1127 /* Check for the Timeout */
1128 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
1129 {
1130 heth->State= HAL_ETH_STATE_READY;
1131
1132 /* Process Unlocked */
1133 __HAL_UNLOCK(heth);
1134
1135 return HAL_TIMEOUT;
1136 }
1137
1138 tmpreg = heth->Instance->MACMIIAR;
1139 }
1140
1141 /* Set ETH HAL State to READY */
1142 heth->State = HAL_ETH_STATE_READY;
1143
1144 /* Return function status */
1145 return HAL_OK;
1146 }
1147
1148 /**
1149 * @}
1150 */
1151
1152 /** @defgroup ETH_Group3 Peripheral Control functions
1153 * @brief Peripheral Control functions
1154 *
1155 @verbatim
1156 ===============================================================================
1157 ##### Peripheral Control functions #####
1158 ===============================================================================
1159 [..] This section provides functions allowing to:
1160 (+) Enable MAC and DMA transmission and reception.
1161 HAL_ETH_Start();
1162 (+) Disable MAC and DMA transmission and reception.
1163 HAL_ETH_Stop();
1164 (+) Set the MAC configuration in runtime mode
1165 HAL_ETH_ConfigMAC();
1166 (+) Set the DMA configuration in runtime mode
1167 HAL_ETH_ConfigDMA();
1168
1169 @endverbatim
1170 * @{
1171 */
1172
1173 /**
1174 * @brief Enables Ethernet MAC and DMA reception/transmission
1175 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1176 * the configuration information for ETHERNET module
1177 * @retval HAL status
1178 */
1179 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
1180 {
1181 /* Process Locked */
1182 __HAL_LOCK(heth);
1183
1184 /* Set the ETH peripheral state to BUSY */
1185 heth->State = HAL_ETH_STATE_BUSY;
1186
1187 /* Enable transmit state machine of the MAC for transmission on the MII */
1188 ETH_MACTransmissionEnable(heth);
1189
1190 /* Enable receive state machine of the MAC for reception from the MII */
1191 ETH_MACReceptionEnable(heth);
1192
1193 /* Flush Transmit FIFO */
1194 ETH_FlushTransmitFIFO(heth);
1195
1196 /* Start DMA transmission */
1197 ETH_DMATransmissionEnable(heth);
1198
1199 /* Start DMA reception */
1200 ETH_DMAReceptionEnable(heth);
1201
1202 /* Set the ETH state to READY*/
1203 heth->State= HAL_ETH_STATE_READY;
1204
1205 /* Process Unlocked */
1206 __HAL_UNLOCK(heth);
1207
1208 /* Return function status */
1209 return HAL_OK;
1210 }
1211
1212 /**
1213 * @brief Stop Ethernet MAC and DMA reception/transmission
1214 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1215 * the configuration information for ETHERNET module
1216 * @retval HAL status
1217 */
1218 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
1219 {
1220 /* Process Locked */
1221 __HAL_LOCK(heth);
1222
1223 /* Set the ETH peripheral state to BUSY */
1224 heth->State = HAL_ETH_STATE_BUSY;
1225
1226 /* Stop DMA transmission */
1227 ETH_DMATransmissionDisable(heth);
1228
1229 /* Stop DMA reception */
1230 ETH_DMAReceptionDisable(heth);
1231
1232 /* Disable receive state machine of the MAC for reception from the MII */
1233 ETH_MACReceptionDisable(heth);
1234
1235 /* Flush Transmit FIFO */
1236 ETH_FlushTransmitFIFO(heth);
1237
1238 /* Disable transmit state machine of the MAC for transmission on the MII */
1239 ETH_MACTransmissionDisable(heth);
1240
1241 /* Set the ETH state*/
1242 heth->State = HAL_ETH_STATE_READY;
1243
1244 /* Process Unlocked */
1245 __HAL_UNLOCK(heth);
1246
1247 /* Return function status */
1248 return HAL_OK;
1249 }
1250
1251 /**
1252 * @brief Set ETH MAC Configuration.
1253 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1254 * the configuration information for ETHERNET module
1255 * @param macconf: MAC Configuration structure
1256 * @retval HAL status
1257 */
1258 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
1259 {
1260 uint32_t tmpreg = 0;
1261
1262 /* Process Locked */
1263 __HAL_LOCK(heth);
1264
1265 /* Set the ETH peripheral state to BUSY */
1266 heth->State= HAL_ETH_STATE_BUSY;
1267
1268 assert_param(IS_ETH_SPEED(heth->Init.Speed));
1269 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
1270
1271 if (macconf != HAL_NULL)
1272 {
1273 /* Check the parameters */
1274 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
1275 assert_param(IS_ETH_JABBER(macconf->Jabber));
1276 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
1277 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
1278 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
1279 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
1280 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
1281 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
1282 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
1283 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
1284 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
1285 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
1286 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
1287 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
1288 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
1289 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
1290 assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
1291 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
1292 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
1293 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
1294 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
1295 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
1296 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
1297 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
1298 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
1299 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
1300 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
1301
1302 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1303 /* Get the ETHERNET MACCR value */
1304 tmpreg = (heth->Instance)->MACCR;
1305 /* Clear WD, PCE, PS, TE and RE bits */
1306 tmpreg &= MACCR_CLEAR_MASK;
1307
1308 tmpreg |= (uint32_t)(macconf->Watchdog |
1309 macconf->Jabber |
1310 macconf->InterFrameGap |
1311 macconf->CarrierSense |
1312 (heth->Init).Speed |
1313 macconf->ReceiveOwn |
1314 macconf->LoopbackMode |
1315 (heth->Init).DuplexMode |
1316 macconf->ChecksumOffload |
1317 macconf->RetryTransmission |
1318 macconf->AutomaticPadCRCStrip |
1319 macconf->BackOffLimit |
1320 macconf->DeferralCheck);
1321
1322 /* Write to ETHERNET MACCR */
1323 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1324
1325 /* Wait until the write operation will be taken into account :
1326 at least four TX_CLK/RX_CLK clock cycles */
1327 tmpreg = (heth->Instance)->MACCR;
1328 HAL_Delay(ETH_REG_WRITE_DELAY);
1329 (heth->Instance)->MACCR = tmpreg;
1330
1331 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1332 /* Write to ETHERNET MACFFR */
1333 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
1334 macconf->SourceAddrFilter |
1335 macconf->PassControlFrames |
1336 macconf->BroadcastFramesReception |
1337 macconf->DestinationAddrFilter |
1338 macconf->PromiscuousMode |
1339 macconf->MulticastFramesFilter |
1340 macconf->UnicastFramesFilter);
1341
1342 /* Wait until the write operation will be taken into account :
1343 at least four TX_CLK/RX_CLK clock cycles */
1344 tmpreg = (heth->Instance)->MACFFR;
1345 HAL_Delay(ETH_REG_WRITE_DELAY);
1346 (heth->Instance)->MACFFR = tmpreg;
1347
1348 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
1349 /* Write to ETHERNET MACHTHR */
1350 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
1351
1352 /* Write to ETHERNET MACHTLR */
1353 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
1354 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
1355
1356 /* Get the ETHERNET MACFCR value */
1357 tmpreg = (heth->Instance)->MACFCR;
1358 /* Clear xx bits */
1359 tmpreg &= MACFCR_CLEAR_MASK;
1360
1361 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
1362 macconf->ZeroQuantaPause |
1363 macconf->PauseLowThreshold |
1364 macconf->UnicastPauseFrameDetect |
1365 macconf->ReceiveFlowControl |
1366 macconf->TransmitFlowControl);
1367
1368 /* Write to ETHERNET MACFCR */
1369 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
1370
1371 /* Wait until the write operation will be taken into account :
1372 at least four TX_CLK/RX_CLK clock cycles */
1373 tmpreg = (heth->Instance)->MACFCR;
1374 HAL_Delay(ETH_REG_WRITE_DELAY);
1375 (heth->Instance)->MACFCR = tmpreg;
1376
1377 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
1378 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
1379 macconf->VLANTagIdentifier);
1380
1381 /* Wait until the write operation will be taken into account :
1382 at least four TX_CLK/RX_CLK clock cycles */
1383 tmpreg = (heth->Instance)->MACVLANTR;
1384 HAL_Delay(ETH_REG_WRITE_DELAY);
1385 (heth->Instance)->MACVLANTR = tmpreg;
1386 }
1387 else /* macconf == NULL : here we just configure Speed and Duplex mode */
1388 {
1389 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1390 /* Get the ETHERNET MACCR value */
1391 tmpreg = (heth->Instance)->MACCR;
1392
1393 /* Clear FES and DM bits */
1394 tmpreg &= ~((uint32_t)0x00004800);
1395
1396 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
1397
1398 /* Write to ETHERNET MACCR */
1399 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1400
1401 /* Wait until the write operation will be taken into account:
1402 at least four TX_CLK/RX_CLK clock cycles */
1403 tmpreg = (heth->Instance)->MACCR;
1404 HAL_Delay(ETH_REG_WRITE_DELAY);
1405 (heth->Instance)->MACCR = tmpreg;
1406 }
1407
1408 /* Set the ETH state to Ready */
1409 heth->State= HAL_ETH_STATE_READY;
1410
1411 /* Process Unlocked */
1412 __HAL_UNLOCK(heth);
1413
1414 /* Return function status */
1415 return HAL_OK;
1416 }
1417
1418 /**
1419 * @brief Sets ETH DMA Configuration.
1420 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1421 * the configuration information for ETHERNET module
1422 * @param dmaconf: DMA Configuration structure
1423 * @retval HAL status
1424 */
1425 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
1426 {
1427 uint32_t tmpreg = 0;
1428
1429 /* Process Locked */
1430 __HAL_LOCK(heth);
1431
1432 /* Set the ETH peripheral state to BUSY */
1433 heth->State= HAL_ETH_STATE_BUSY;
1434
1435 /* Check parameters */
1436 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
1437 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
1438 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
1439 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
1440 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
1441 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
1442 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
1443 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
1444 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
1445 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
1446 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
1447 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
1448 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
1449 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
1450 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
1451 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
1452
1453 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
1454 /* Get the ETHERNET DMAOMR value */
1455 tmpreg = (heth->Instance)->DMAOMR;
1456 /* Clear xx bits */
1457 tmpreg &= DMAOMR_CLEAR_MASK;
1458
1459 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
1460 dmaconf->ReceiveStoreForward |
1461 dmaconf->FlushReceivedFrame |
1462 dmaconf->TransmitStoreForward |
1463 dmaconf->TransmitThresholdControl |
1464 dmaconf->ForwardErrorFrames |
1465 dmaconf->ForwardUndersizedGoodFrames |
1466 dmaconf->ReceiveThresholdControl |
1467 dmaconf->SecondFrameOperate);
1468
1469 /* Write to ETHERNET DMAOMR */
1470 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
1471
1472 /* Wait until the write operation will be taken into account:
1473 at least four TX_CLK/RX_CLK clock cycles */
1474 tmpreg = (heth->Instance)->DMAOMR;
1475 HAL_Delay(ETH_REG_WRITE_DELAY);
1476 (heth->Instance)->DMAOMR = tmpreg;
1477
1478 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
1479 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
1480 dmaconf->FixedBurst |
1481 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1482 dmaconf->TxDMABurstLength |
1483 dmaconf->EnhancedDescriptorFormat |
1484 (dmaconf->DescriptorSkipLength << 2) |
1485 dmaconf->DMAArbitration |
1486 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1487
1488 /* Wait until the write operation will be taken into account:
1489 at least four TX_CLK/RX_CLK clock cycles */
1490 tmpreg = (heth->Instance)->DMABMR;
1491 HAL_Delay(ETH_REG_WRITE_DELAY);
1492 (heth->Instance)->DMABMR = tmpreg;
1493
1494 /* Set the ETH state to Ready */
1495 heth->State= HAL_ETH_STATE_READY;
1496
1497 /* Process Unlocked */
1498 __HAL_UNLOCK(heth);
1499
1500 /* Return function status */
1501 return HAL_OK;
1502 }
1503
1504 /**
1505 * @}
1506 */
1507
1508 /** @defgroup ETH_Group4 Peripheral State functions
1509 * @brief Peripheral State functions
1510 *
1511 @verbatim
1512 ===============================================================================
1513 ##### Peripheral State functions #####
1514 ===============================================================================
1515 [..]
1516 This subsection permits to get in run-time the status of the peripheral
1517 and the data flow.
1518 (+) Get the ETH handle state:
1519 HAL_ETH_GetState();
1520
1521
1522 @endverbatim
1523 * @{
1524 */
1525
1526 /**
1527 * @brief Return the ETH HAL state
1528 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1529 * the configuration information for ETHERNET module
1530 * @retval HAL state
1531 */
1532 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
1533 {
1534 /* Return ETH state */
1535 return heth->State;
1536 }
1537
1538 /**
1539 * @}
1540 */
1541
1542 /**
1543 * @brief Configures Ethernet MAC and DMA with default parameters.
1544 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1545 * the configuration information for ETHERNET module
1546 * @param err: Ethernet Init error
1547 * @retval HAL status
1548 */
1549 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
1550 {
1551 ETH_MACInitTypeDef macinit;
1552 ETH_DMAInitTypeDef dmainit;
1553 uint32_t tmpreg = 0;
1554
1555 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
1556 {
1557 /* Set Ethernet duplex mode to Full-duplex */
1558 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
1559
1560 /* Set Ethernet speed to 100M */
1561 (heth->Init).Speed = ETH_SPEED_100M;
1562 }
1563
1564 /* Ethernet MAC default initialization **************************************/
1565 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
1566 macinit.Jabber = ETH_JABBER_ENABLE;
1567 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
1568 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
1569 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
1570 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
1571 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
1572 {
1573 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
1574 }
1575 else
1576 {
1577 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
1578 }
1579 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
1580 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
1581 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
1582 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
1583 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
1584 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
1585 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
1586 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
1587 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
1588 macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
1589 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
1590 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
1591 macinit.HashTableHigh = 0x0;
1592 macinit.HashTableLow = 0x0;
1593 macinit.PauseTime = 0x0;
1594 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
1595 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
1596 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
1597 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
1598 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
1599 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
1600 macinit.VLANTagIdentifier = 0x0;
1601
1602 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1603 /* Get the ETHERNET MACCR value */
1604 tmpreg = (heth->Instance)->MACCR;
1605 /* Clear WD, PCE, PS, TE and RE bits */
1606 tmpreg &= MACCR_CLEAR_MASK;
1607 /* Set the WD bit according to ETH Watchdog value */
1608 /* Set the JD: bit according to ETH Jabber value */
1609 /* Set the IFG bit according to ETH InterFrameGap value */
1610 /* Set the DCRS bit according to ETH CarrierSense value */
1611 /* Set the FES bit according to ETH Speed value */
1612 /* Set the DO bit according to ETH ReceiveOwn value */
1613 /* Set the LM bit according to ETH LoopbackMode value */
1614 /* Set the DM bit according to ETH Mode value */
1615 /* Set the IPCO bit according to ETH ChecksumOffload value */
1616 /* Set the DR bit according to ETH RetryTransmission value */
1617 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
1618 /* Set the BL bit according to ETH BackOffLimit value */
1619 /* Set the DC bit according to ETH DeferralCheck value */
1620 tmpreg |= (uint32_t)(macinit.Watchdog |
1621 macinit.Jabber |
1622 macinit.InterFrameGap |
1623 macinit.CarrierSense |
1624 (heth->Init).Speed |
1625 macinit.ReceiveOwn |
1626 macinit.LoopbackMode |
1627 (heth->Init).DuplexMode |
1628 macinit.ChecksumOffload |
1629 macinit.RetryTransmission |
1630 macinit.AutomaticPadCRCStrip |
1631 macinit.BackOffLimit |
1632 macinit.DeferralCheck);
1633
1634 /* Write to ETHERNET MACCR */
1635 (heth->Instance)->MACCR = (uint32_t)tmpreg;
1636
1637 /* Wait until the write operation will be taken into account:
1638 at least four TX_CLK/RX_CLK clock cycles */
1639 tmpreg = (heth->Instance)->MACCR;
1640 HAL_Delay(ETH_REG_WRITE_DELAY);
1641 (heth->Instance)->MACCR = tmpreg;
1642
1643 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1644 /* Set the RA bit according to ETH ReceiveAll value */
1645 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
1646 /* Set the PCF bit according to ETH PassControlFrames value */
1647 /* Set the DBF bit according to ETH BroadcastFramesReception value */
1648 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
1649 /* Set the PR bit according to ETH PromiscuousMode value */
1650 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
1651 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
1652 /* Write to ETHERNET MACFFR */
1653 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
1654 macinit.SourceAddrFilter |
1655 macinit.PassControlFrames |
1656 macinit.BroadcastFramesReception |
1657 macinit.DestinationAddrFilter |
1658 macinit.PromiscuousMode |
1659 macinit.MulticastFramesFilter |
1660 macinit.UnicastFramesFilter);
1661
1662 /* Wait until the write operation will be taken into account:
1663 at least four TX_CLK/RX_CLK clock cycles */
1664 tmpreg = (heth->Instance)->MACFFR;
1665 HAL_Delay(ETH_REG_WRITE_DELAY);
1666 (heth->Instance)->MACFFR = tmpreg;
1667
1668 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
1669 /* Write to ETHERNET MACHTHR */
1670 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
1671
1672 /* Write to ETHERNET MACHTLR */
1673 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
1674 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
1675
1676 /* Get the ETHERNET MACFCR value */
1677 tmpreg = (heth->Instance)->MACFCR;
1678 /* Clear xx bits */
1679 tmpreg &= MACFCR_CLEAR_MASK;
1680
1681 /* Set the PT bit according to ETH PauseTime value */
1682 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
1683 /* Set the PLT bit according to ETH PauseLowThreshold value */
1684 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
1685 /* Set the RFE bit according to ETH ReceiveFlowControl value */
1686 /* Set the TFE bit according to ETH TransmitFlowControl value */
1687 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
1688 macinit.ZeroQuantaPause |
1689 macinit.PauseLowThreshold |
1690 macinit.UnicastPauseFrameDetect |
1691 macinit.ReceiveFlowControl |
1692 macinit.TransmitFlowControl);
1693
1694 /* Write to ETHERNET MACFCR */
1695 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
1696
1697 /* Wait until the write operation will be taken into account:
1698 at least four TX_CLK/RX_CLK clock cycles */
1699 tmpreg = (heth->Instance)->MACFCR;
1700 HAL_Delay(ETH_REG_WRITE_DELAY);
1701 (heth->Instance)->MACFCR = tmpreg;
1702
1703 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
1704 /* Set the ETV bit according to ETH VLANTagComparison value */
1705 /* Set the VL bit according to ETH VLANTagIdentifier value */
1706 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
1707 macinit.VLANTagIdentifier);
1708
1709 /* Wait until the write operation will be taken into account:
1710 at least four TX_CLK/RX_CLK clock cycles */
1711 tmpreg = (heth->Instance)->MACVLANTR;
1712 HAL_Delay(ETH_REG_WRITE_DELAY);
1713 (heth->Instance)->MACVLANTR = tmpreg;
1714
1715 /* Ethernet DMA default initialization ************************************/
1716 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
1717 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
1718 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
1719 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
1720 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
1721 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
1722 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
1723 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
1724 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
1725 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
1726 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
1727 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
1728 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
1729 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
1730 dmainit.DescriptorSkipLength = 0x0;
1731 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
1732
1733 /* Get the ETHERNET DMAOMR value */
1734 tmpreg = (heth->Instance)->DMAOMR;
1735 /* Clear xx bits */
1736 tmpreg &= DMAOMR_CLEAR_MASK;
1737
1738 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
1739 /* Set the RSF bit according to ETH ReceiveStoreForward value */
1740 /* Set the DFF bit according to ETH FlushReceivedFrame value */
1741 /* Set the TSF bit according to ETH TransmitStoreForward value */
1742 /* Set the TTC bit according to ETH TransmitThresholdControl value */
1743 /* Set the FEF bit according to ETH ForwardErrorFrames value */
1744 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
1745 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
1746 /* Set the OSF bit according to ETH SecondFrameOperate value */
1747 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
1748 dmainit.ReceiveStoreForward |
1749 dmainit.FlushReceivedFrame |
1750 dmainit.TransmitStoreForward |
1751 dmainit.TransmitThresholdControl |
1752 dmainit.ForwardErrorFrames |
1753 dmainit.ForwardUndersizedGoodFrames |
1754 dmainit.ReceiveThresholdControl |
1755 dmainit.SecondFrameOperate);
1756
1757 /* Write to ETHERNET DMAOMR */
1758 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
1759
1760 /* Wait until the write operation will be taken into account:
1761 at least four TX_CLK/RX_CLK clock cycles */
1762 tmpreg = (heth->Instance)->DMAOMR;
1763 HAL_Delay(ETH_REG_WRITE_DELAY);
1764 (heth->Instance)->DMAOMR = tmpreg;
1765
1766 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
1767 /* Set the AAL bit according to ETH AddressAlignedBeats value */
1768 /* Set the FB bit according to ETH FixedBurst value */
1769 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
1770 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
1771 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
1772 /* Set the DSL bit according to ETH DesciptorSkipLength value */
1773 /* Set the PR and DA bits according to ETH DMAArbitration value */
1774 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
1775 dmainit.FixedBurst |
1776 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1777 dmainit.TxDMABurstLength |
1778 dmainit.EnhancedDescriptorFormat |
1779 (dmainit.DescriptorSkipLength << 2) |
1780 dmainit.DMAArbitration |
1781 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1782
1783 /* Wait until the write operation will be taken into account:
1784 at least four TX_CLK/RX_CLK clock cycles */
1785 tmpreg = (heth->Instance)->DMABMR;
1786 HAL_Delay(ETH_REG_WRITE_DELAY);
1787 (heth->Instance)->DMABMR = tmpreg;
1788
1789 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
1790 {
1791 /* Enable the Ethernet Rx Interrupt */
1792 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
1793 }
1794
1795 /* Initialize MAC address in ethernet MAC */
1796 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
1797 }
1798
1799 /**
1800 * @brief Configures the selected MAC address.
1801 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1802 * the configuration information for ETHERNET module
1803 * @param MacAddr: The MAC address to configure
1804 * This parameter can be one of the following values:
1805 * @arg ETH_MAC_Address0: MAC Address0
1806 * @arg ETH_MAC_Address1: MAC Address1
1807 * @arg ETH_MAC_Address2: MAC Address2
1808 * @arg ETH_MAC_Address3: MAC Address3
1809 * @param Addr: Pointer to MAC address buffer data (6 bytes)
1810 * @retval HAL status
1811 */
1812 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
1813 {
1814 uint32_t tmpreg;
1815
1816 /* Check the parameters */
1817 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1818
1819 /* Calculate the selected MAC address high register */
1820 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
1821 /* Load the selected MAC address high register */
1822 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
1823 /* Calculate the selected MAC address low register */
1824 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
1825
1826 /* Load the selected MAC address low register */
1827 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
1828 }
1829
1830 /**
1831 * @brief Enables the MAC transmission.
1832 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1833 * the configuration information for ETHERNET module
1834 * @retval None
1835 */
1836 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
1837 {
1838 __IO uint32_t tmpreg = 0;
1839
1840 /* Enable the MAC transmission */
1841 (heth->Instance)->MACCR |= ETH_MACCR_TE;
1842
1843 /* Wait until the write operation will be taken into account:
1844 at least four TX_CLK/RX_CLK clock cycles */
1845 tmpreg = (heth->Instance)->MACCR;
1846 HAL_Delay(ETH_REG_WRITE_DELAY);
1847 (heth->Instance)->MACCR = tmpreg;
1848 }
1849
1850 /**
1851 * @brief Disables the MAC transmission.
1852 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1853 * the configuration information for ETHERNET module
1854 * @retval None
1855 */
1856 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
1857 {
1858 __IO uint32_t tmpreg = 0;
1859
1860 /* Disable the MAC transmission */
1861 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
1862
1863 /* Wait until the write operation will be taken into account:
1864 at least four TX_CLK/RX_CLK clock cycles */
1865 tmpreg = (heth->Instance)->MACCR;
1866 HAL_Delay(ETH_REG_WRITE_DELAY);
1867 (heth->Instance)->MACCR = tmpreg;
1868 }
1869
1870 /**
1871 * @brief Enables the MAC reception.
1872 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1873 * the configuration information for ETHERNET module
1874 * @retval None
1875 */
1876 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
1877 {
1878 __IO uint32_t tmpreg = 0;
1879
1880 /* Enable the MAC reception */
1881 (heth->Instance)->MACCR |= ETH_MACCR_RE;
1882
1883 /* Wait until the write operation will be taken into account:
1884 at least four TX_CLK/RX_CLK clock cycles */
1885 tmpreg = (heth->Instance)->MACCR;
1886 HAL_Delay(ETH_REG_WRITE_DELAY);
1887 (heth->Instance)->MACCR = tmpreg;
1888 }
1889
1890 /**
1891 * @brief Disables the MAC reception.
1892 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1893 * the configuration information for ETHERNET module
1894 * @retval None
1895 */
1896 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
1897 {
1898 __IO uint32_t tmpreg = 0;
1899
1900 /* Disable the MAC reception */
1901 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
1902
1903 /* Wait until the write operation will be taken into account:
1904 at least four TX_CLK/RX_CLK clock cycles */
1905 tmpreg = (heth->Instance)->MACCR;
1906 HAL_Delay(ETH_REG_WRITE_DELAY);
1907 (heth->Instance)->MACCR = tmpreg;
1908 }
1909
1910 /**
1911 * @brief Enables the DMA transmission.
1912 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1913 * the configuration information for ETHERNET module
1914 * @retval None
1915 */
1916 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
1917 {
1918 /* Enable the DMA transmission */
1919 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
1920 }
1921
1922 /**
1923 * @brief Disables the DMA transmission.
1924 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1925 * the configuration information for ETHERNET module
1926 * @retval None
1927 */
1928 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
1929 {
1930 /* Disable the DMA transmission */
1931 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
1932 }
1933
1934 /**
1935 * @brief Enables the DMA reception.
1936 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1937 * the configuration information for ETHERNET module
1938 * @retval None
1939 */
1940 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
1941 {
1942 /* Enable the DMA reception */
1943 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
1944 }
1945
1946 /**
1947 * @brief Disables the DMA reception.
1948 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1949 * the configuration information for ETHERNET module
1950 * @retval None
1951 */
1952 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
1953 {
1954 /* Disable the DMA reception */
1955 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
1956 }
1957
1958 /**
1959 * @brief Clears the ETHERNET transmit FIFO.
1960 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1961 * the configuration information for ETHERNET module
1962 * @retval None
1963 */
1964 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
1965 {
1966 __IO uint32_t tmpreg = 0;
1967
1968 /* Set the Flush Transmit FIFO bit */
1969 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
1970
1971 /* Wait until the write operation will be taken into account:
1972 at least four TX_CLK/RX_CLK clock cycles */
1973 tmpreg = (heth->Instance)->DMAOMR;
1974 HAL_Delay(ETH_REG_WRITE_DELAY);
1975 (heth->Instance)->DMAOMR = tmpreg;
1976 }
1977
1978 /**
1979 * @}
1980 */
1981
1982 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1983 #endif /* HAL_ETH_MODULE_ENABLED */
1984 /**
1985 * @}
1986 */
1987
1988 /**
1989 * @}
1990 */
1991
1992 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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