tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_i2s.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   I2S HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
  10   *           + Initialization and de-initialization functions
  11   *           + IO operation functions
  12   *           + Peripheral State and Errors functions
  13   @verbatim
  14  ===============================================================================
  15                   ##### How to use this driver #####
  16  ===============================================================================
  17  [..]
  18     The I2S HAL driver can be used as follow:
  19
  20     (#) Declare a I2S_HandleTypeDef handle structure.
  21     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
  22         (##) Enable the SPIx interface clock.
  23         (##) I2S pins configuration:
  24             (+++) Enable the clock for the I2S GPIOs.
  25             (+++) Configure these I2S pins as alternate function pull-up.
  26         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
  27              and HAL_I2S_Receive_IT() APIs).
  28             (+++) Configure the I2Sx interrupt priority.
  29             (+++) Enable the NVIC I2S IRQ handle.
  30         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
  31              and HAL_I2S_Receive_DMA() APIs:
  32             (+++) Declare a DMA handle structure for the Tx/Rx stream.
  33             (+++) Enable the DMAx interface clock.
  34             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
  35             (+++) Configure the DMA Tx/Rx Stream.
  36             (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
  37             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
  38                 DMA Tx/Rx Stream.
  39
  40    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
  41        using HAL_I2S_Init() function.
  42
  43    -@- The specific I2S interrupts (Transmission complete interrupt,
  44        RXNE interrupt and Error Interrupts) will be managed using the macros
  45        __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
  46    -@- Make sure that either:
  47         (+@) I2S PLL is configured or
  48         (+@) External clock source is configured after setting correctly
  49              the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
  50
  51    (#) Three operation modes are available within this driver :
  52
  53    *** Polling mode IO operation ***
  54    =================================
  55    [..]
  56      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
  57      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
  58
  59    *** Interrupt mode IO operation ***
  60    ===================================
  61    [..]
  62      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
  63      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  64          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  65      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  66          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  67      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
  68      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  69          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  70      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  71          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  72      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  73          add his own code by customization of function pointer HAL_I2S_ErrorCallback
  74
  75    *** DMA mode IO operation ***
  76    ==============================
  77    [..]
  78      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
  79      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  80          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  81      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  82          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  83      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
  84      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  85          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  86      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  87          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  88      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  89          add his own code by customization of function pointer HAL_I2S_ErrorCallback
  90      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
  91      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
  92      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
  93
  94    *** I2S HAL driver macros list ***
  95    =============================================
  96    [..]
  97      Below the list of most used macros in USART HAL driver.
  98
  99       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
 100       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
 101       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
 102       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
 103       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
 104
 105     [..]
 106       (@) You can refer to the I2S HAL driver header file for more useful macros
 107
 108   @endverbatim
 109   ******************************************************************************
 110   * @attention
 111   *
 112   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
 113   *
 114   * Redistribution and use in source and binary forms, with or without modification,
 115   * are permitted provided that the following conditions are met:
 116   *   1. Redistributions of source code must retain the above copyright notice,
 117   *      this list of conditions and the following disclaimer.
 118   *   2. Redistributions in binary form must reproduce the above copyright notice,
 119   *      this list of conditions and the following disclaimer in the documentation
 120   *      and/or other materials provided with the distribution.
 121   *   3. Neither the name of STMicroelectronics nor the names of its contributors
 122   *      may be used to endorse or promote products derived from this software
 123   *      without specific prior written permission.
 124   *
 125   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 126   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 127   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 128   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 129   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 130   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 131   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 132   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 133   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 134   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 135   *
 136   ******************************************************************************
 137   */
 138
 139 /* Includes ------------------------------------------------------------------*/
 140 #include "stm32f4xx_hal.h"
 141
 142 /** @addtogroup STM32F4xx_HAL_Driver
 143   * @{
 144   */
 145
 146 /** @defgroup I2S
 147   * @brief I2S HAL module driver
 148   * @{
 149   */
 150
 151 #ifdef HAL_I2S_MODULE_ENABLED
 152
 153 /* Private typedef -----------------------------------------------------------*/
 154 /* Private define ------------------------------------------------------------*/
 155 /* Private macro -------------------------------------------------------------*/
 156 /* Private variables ---------------------------------------------------------*/
 157 /* Private function prototypes -----------------------------------------------*/
 158 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
 159 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
 160 /* Private functions ---------------------------------------------------------*/
 161
 162 /** @defgroup I2S_Private_Functions
 163   * @{
 164   */
 165
 166 /** @defgroup  I2S_Group1 Initialization and de-initialization functions
 167   *  @brief    Initialization and Configuration functions
 168   *
 169 @verbatim
 170  ===============================================================================
 171               ##### Initialization and de-initialization functions #####
 172  ===============================================================================
 173     [..]  This subsection provides a set of functions allowing to initialize and
 174           de-initialiaze the I2Sx peripheral in simplex mode:
 175
 176       (+) User must Implement HAL_I2S_MspInit() function in which he configures
 177           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 178
 179       (+) Call the function HAL_I2S_Init() to configure the selected device with
 180           the selected configuration:
 181         (++) Mode
 182         (++) Standard
 183         (++) Data Format
 184         (++) MCLK Output
 185         (++) Audio frequency
 186         (++) Polarity
 187         (++) Full duplex mode
 188
 189       (+) Call the function HAL_I2S_DeInit() to restore the default configuration
 190           of the selected I2Sx periperal.
 191 @endverbatim
 192   * @{
 193   */
 194
 195 /**
 196   * @brief Initializes the I2S according to the specified parameters
 197   *         in the I2S_InitTypeDef and create the associated handle.
 198   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 199   *         the configuration information for I2S module
 200   * @retval HAL status
 201   */
 202 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
 203 {
 204   uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
 205   uint32_t tmp = 0, i2sclk = 0;
 206
 207   /* Check the I2S handle allocation */
 208   if(hi2s == HAL_NULL)
 209   {
 210     return HAL_ERROR;
 211   }
 212
 213   /* Check the I2S parameters */
 214   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
 215   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
 216   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
 217   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
 218   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
 219   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
 220   assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
 221   assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
 222
 223   if(hi2s->State == HAL_I2S_STATE_RESET)
 224   {
 225     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
 226     HAL_I2S_MspInit(hi2s);
 227   }
 228
 229   hi2s->State = HAL_I2S_STATE_BUSY;
 230
 231   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
 232   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
 233   hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
 234                                SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
 235                                SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
 236   hi2s->Instance->I2SPR = 0x0002;
 237
 238   /* Get the I2SCFGR register value */
 239   tmpreg = hi2s->Instance->I2SCFGR;
 240
 241   /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
 242   /* If the requested audio frequency is not the default, compute the prescaler */
 243   if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
 244   {
 245     /* Check the frame length (For the Prescaler computing) *******************/
 246     if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
 247     {
 248       /* Packet length is 32 bits */
 249       packetlength = 2;
 250     }
 251
 252     /* Get I2S source Clock frequency  ****************************************/
 253     /* If an external I2S clock has to be used, the specific define should be set
 254     in the project configuration or in the stm32f4xx_conf.h file */
 255     if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
 256     {
 257       /* Set external clock as I2S clock source */
 258       if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
 259       {
 260         RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
 261       }
 262
 263       /* Set the I2S clock to the external clock  value */
 264       i2sclk = EXTERNAL_CLOCK_VALUE;
 265     }
 266     else
 267     {
 268       /* Check if PLLI2S is enabled or Not */
 269       if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
 270       {
 271         hi2s->State= HAL_I2S_STATE_READY;
 272
 273         return HAL_ERROR;
 274       }
 275
 276       /* Set PLLI2S as I2S clock source */
 277       if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
 278       {
 279         RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
 280       }
 281
 282       /* Get the PLLM value */
 283       if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
 284       {
 285         /* Get the I2S source clock value */
 286         i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
 287       }
 288       else
 289       {
 290         /* Get the I2S source clock value */
 291         i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
 292       }
 293       i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6));
 294       i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28));
 295     }
 296
 297     /* Compute the Real divider depending on the MCLK output state, with a floating point */
 298     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
 299     {
 300       /* MCLK output is enabled */
 301       tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
 302     }
 303     else
 304     {
 305       /* MCLK output is disabled */
 306       tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
 307     }
 308
 309     /* Remove the flatting point */
 310     tmp = tmp / 10;
 311
 312     /* Check the parity of the divider */
 313     i2sodd = (uint32_t)(tmp & (uint32_t)1);
 314
 315     /* Compute the i2sdiv prescaler */
 316     i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
 317
 318     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 319     i2sodd = (uint32_t) (i2sodd << 8);
 320   }
 321
 322   /* Test if the divider is 1 or 0 or greater than 0xFF */
 323   if((i2sdiv < 2) || (i2sdiv > 0xFF))
 324   {
 325     /* Set the default values */
 326     i2sdiv = 2;
 327     i2sodd = 0;
 328   }
 329
 330   /* Write to SPIx I2SPR register the computed value */
 331   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
 332
 333   /* Configure the I2S with the I2S_InitStruct values */
 334   tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
 335
 336   /* Write to SPIx I2SCFGR */
 337   hi2s->Instance->I2SCFGR = tmpreg;
 338
 339   /* Configure the I2S extended if the full duplex mode is enabled */
 340   if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
 341   {
 342     /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
 343     I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
 344                                           SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
 345                                           SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
 346     I2SxEXT(hi2s->Instance)->I2SPR = 2;
 347
 348     /* Get the I2SCFGR register value */
 349     tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
 350
 351     /* Get the mode to be configured for the extended I2S */
 352     if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
 353     {
 354       tmp = I2S_MODE_SLAVE_RX;
 355     }
 356     else
 357     {
 358       if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
 359       {
 360         tmp = I2S_MODE_SLAVE_TX;
 361       }
 362     }
 363
 364     /* Configure the I2S Slave with the I2S Master parameter values */
 365     tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
 366
 367     /* Write to SPIx I2SCFGR */
 368     I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
 369   }
 370
 371   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 372   hi2s->State= HAL_I2S_STATE_READY;
 373
 374   return HAL_OK;
 375 }
 376
 377 /**
 378   * @brief DeInitializes the I2S peripheral
 379   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 380   *         the configuration information for I2S module
 381   * @retval HAL status
 382   */
 383 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
 384 {
 385   /* Check the I2S handle allocation */
 386   if(hi2s == HAL_NULL)
 387   {
 388     return HAL_ERROR;
 389   }
 390
 391   hi2s->State = HAL_I2S_STATE_BUSY;
 392
 393   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 394   HAL_I2S_MspDeInit(hi2s);
 395
 396   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 397   hi2s->State = HAL_I2S_STATE_RESET;
 398
 399   /* Release Lock */
 400   __HAL_UNLOCK(hi2s);
 401
 402   return HAL_OK;
 403 }
 404
 405 /**
 406   * @brief I2S MSP Init
 407   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 408   *         the configuration information for I2S module
 409   * @retval None
 410   */
 411  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
 412 {
 413   /* NOTE : This function Should not be modified, when the callback is needed,
 414             the HAL_I2S_MspInit could be implenetd in the user file
 415    */
 416 }
 417
 418 /**
 419   * @brief I2S MSP DeInit
 420   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 421   *         the configuration information for I2S module
 422   * @retval None
 423   */
 424  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
 425 {
 426   /* NOTE : This function Should not be modified, when the callback is needed,
 427             the HAL_I2S_MspDeInit could be implenetd in the user file
 428    */
 429 }
 430
 431 /**
 432   * @}
 433   */
 434
 435 /** @defgroup I2S_Group2 IO operation functions
 436   *  @brief Data transfers functions
 437   *
 438 @verbatim
 439  ===============================================================================
 440                       ##### IO operation functions #####
 441  ===============================================================================
 442     [..]
 443     This subsection provides a set of functions allowing to manage the I2S data
 444     transfers.
 445
 446     (#) There are two modes of transfer:
 447        (++) Blocking mode : The communication is performed in the polling mode.
 448             The status of all data processing is returned by the same function
 449             after finishing transfer.
 450        (++) No-Blocking mode : The communication is performed using Interrupts
 451             or DMA. These functions return the status of the transfer startup.
 452             The end of the data processing will be indicated through the
 453             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
 454             using DMA mode.
 455
 456     (#) Blocking mode functions are :
 457         (++) HAL_I2S_Transmit()
 458         (++) HAL_I2S_Receive()
 459
 460     (#) No-Blocking mode functions with Interrupt are :
 461         (++) HAL_I2S_Transmit_IT()
 462         (++) HAL_I2S_Receive_IT()
 463
 464     (#) No-Blocking mode functions with DMA are :
 465         (++) HAL_I2S_Transmit_DMA()
 466         (++) HAL_I2S_Receive_DMA()
 467
 468     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
 469         (++) HAL_I2S_TxCpltCallback()
 470         (++) HAL_I2S_RxCpltCallback()
 471         (++) HAL_I2S_ErrorCallback()
 472
 473 @endverbatim
 474   * @{
 475   */
 476
 477 /**
 478   * @brief Transmit an amount of data in blocking mode
 479   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 480   *         the configuration information for I2S module
 481   * @param pData: a 16-bit pointer to data buffer.
 482   * @param Size: number of data sample to be sent:
 483   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 484   *       configuration phase, the Size parameter means the number of 16-bit data length
 485   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 486   *       the Size parameter means the number of 16-bit data length.
 487   * @param  Timeout: Timeout duration
 488   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 489   *       between Master and Slave(example: audio streaming).
 490   * @retval HAL status
 491   */
 492 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 493 {
 494   uint32_t tmp1 = 0, tmp2 = 0;
 495   if((pData == HAL_NULL ) || (Size == 0))
 496   {
 497     return  HAL_ERROR;
 498   }
 499
 500   if(hi2s->State == HAL_I2S_STATE_READY)
 501   {
 502     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 503     tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 504     if((tmp1 == I2S_DATAFORMAT_24B)|| \
 505        (tmp2 == I2S_DATAFORMAT_32B))
 506     {
 507       hi2s->TxXferSize = Size*2;
 508       hi2s->TxXferCount = Size*2;
 509     }
 510     else
 511     {
 512       hi2s->TxXferSize = Size;
 513       hi2s->TxXferCount = Size;
 514     }
 515
 516     /* Process Locked */
 517     __HAL_LOCK(hi2s);
 518
 519     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 520
 521     /* Check if the I2S is already enabled */
 522     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 523     {
 524       /* Enable I2S peripheral */
 525       __HAL_I2S_ENABLE(hi2s);
 526     }
 527
 528     while(hi2s->TxXferCount > 0)
 529     {
 530       hi2s->Instance->DR = (*pData++);
 531       hi2s->TxXferCount--;
 532       /* Wait until TXE flag is set */
 533       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
 534       {
 535         return HAL_TIMEOUT;
 536       }
 537     }
 538     /* Wait until Busy flag is reset */
 539     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
 540     {
 541       return HAL_TIMEOUT;
 542     }
 543
 544     hi2s->State = HAL_I2S_STATE_READY;
 545
 546     /* Process Unlocked */
 547     __HAL_UNLOCK(hi2s);
 548
 549     return HAL_OK;
 550   }
 551   else
 552   {
 553     return HAL_BUSY;
 554   }
 555 }
 556
 557 /**
 558   * @brief Receive an amount of data in blocking mode
 559   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 560   *         the configuration information for I2S module
 561   * @param pData: a 16-bit pointer to data buffer.
 562   * @param Size: number of data sample to be sent:
 563   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 564   *       configuration phase, the Size parameter means the number of 16-bit data length
 565   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 566   *       the Size parameter means the number of 16-bit data length.
 567   * @param Timeout: Timeout duration
 568   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 569   *       between Master and Slave(example: audio streaming).
 570   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
 571   *       in continouse way and as the I2S is not disabled at the end of the I2S transaction.
 572   * @retval HAL status
 573   */
 574 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 575 {
 576   uint32_t tmp1 = 0, tmp2 = 0;
 577   if((pData == HAL_NULL ) || (Size == 0))
 578   {
 579     return  HAL_ERROR;
 580   }
 581
 582   if(hi2s->State == HAL_I2S_STATE_READY)
 583   {
 584     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 585     tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 586     if((tmp1 == I2S_DATAFORMAT_24B)|| \
 587        (tmp2 == I2S_DATAFORMAT_32B))
 588     {
 589       hi2s->RxXferSize = Size*2;
 590       hi2s->RxXferCount = Size*2;
 591     }
 592     else
 593     {
 594       hi2s->RxXferSize = Size;
 595       hi2s->RxXferCount = Size;
 596     }
 597     /* Process Locked */
 598     __HAL_LOCK(hi2s);
 599
 600     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 601
 602     /* Check if the I2S is already enabled */
 603     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 604     {
 605       /* Enable I2S peripheral */
 606       __HAL_I2S_ENABLE(hi2s);
 607     }
 608
 609     /* Check if Master Receiver mode is selected */
 610     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
 611     {
 612       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
 613       access to the SPI_SR register. */
 614       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
 615     }
 616
 617     /* Receive data */
 618     while(hi2s->RxXferCount > 0)
 619     {
 620       /* Wait until RXNE flag is set */
 621       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
 622       {
 623         return HAL_TIMEOUT;
 624       }
 625
 626       (*pData++) = hi2s->Instance->DR;
 627       hi2s->RxXferCount--;
 628     }
 629
 630     hi2s->State = HAL_I2S_STATE_READY;
 631
 632     /* Process Unlocked */
 633     __HAL_UNLOCK(hi2s);
 634
 635     return HAL_OK;
 636   }
 637   else
 638   {
 639     return HAL_BUSY;
 640   }
 641 }
 642
 643 /**
 644   * @brief Transmit an amount of data in non-blocking mode with Interrupt
 645   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 646   *         the configuration information for I2S module
 647   * @param pData: a 16-bit pointer to data buffer.
 648   * @param Size: number of data sample to be sent:
 649   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 650   *       configuration phase, the Size parameter means the number of 16-bit data length
 651   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 652   *       the Size parameter means the number of 16-bit data length.
 653   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 654   *       between Master and Slave(example: audio streaming).
 655   * @retval HAL status
 656   */
 657 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 658 {
 659   uint32_t tmp1 = 0, tmp2 = 0;
 660   if(hi2s->State == HAL_I2S_STATE_READY)
 661   {
 662     if((pData == HAL_NULL) || (Size == 0))
 663     {
 664       return  HAL_ERROR;
 665     }
 666
 667     hi2s->pTxBuffPtr = pData;
 668     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 669     tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 670     if((tmp1 == I2S_DATAFORMAT_24B)|| \
 671       (tmp2 == I2S_DATAFORMAT_32B))
 672     {
 673       hi2s->TxXferSize = Size*2;
 674       hi2s->TxXferCount = Size*2;
 675     }
 676     else
 677     {
 678       hi2s->TxXferSize = Size;
 679       hi2s->TxXferCount = Size;
 680     }
 681
 682     /* Process Locked */
 683     __HAL_LOCK(hi2s);
 684
 685     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 686     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 687
 688     /* Enable TXE and ERR interrupt */
 689     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
 690
 691     /* Check if the I2S is already enabled */
 692     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 693     {
 694       /* Enable I2S peripheral */
 695       __HAL_I2S_ENABLE(hi2s);
 696     }
 697
 698     /* Process Unlocked */
 699     __HAL_UNLOCK(hi2s);
 700
 701     return HAL_OK;
 702   }
 703   else
 704   {
 705     return HAL_BUSY;
 706   }
 707 }
 708
 709 /**
 710   * @brief Receive an amount of data in non-blocking mode with Interrupt
 711   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 712   *         the configuration information for I2S module
 713   * @param pData: a 16-bit pointer to the Receive data buffer.
 714   * @param Size: number of data sample to be sent:
 715   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 716   *       configuration phase, the Size parameter means the number of 16-bit data length
 717   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 718   *       the Size parameter means the number of 16-bit data length.
 719   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 720   *       between Master and Slave(example: audio streaming).
 721   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
 722   * between Master and Slave otherwise the I2S interrupt should be optimized.
 723   * @retval HAL status
 724   */
 725 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 726 {
 727   uint32_t tmp1 = 0, tmp2 = 0;
 728   if(hi2s->State == HAL_I2S_STATE_READY)
 729   {
 730     if((pData == HAL_NULL) || (Size == 0))
 731     {
 732       return  HAL_ERROR;
 733     }
 734
 735     hi2s->pRxBuffPtr = pData;
 736     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 737     tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 738     if((tmp1 == I2S_DATAFORMAT_24B)||\
 739       (tmp2 == I2S_DATAFORMAT_32B))
 740     {
 741       hi2s->RxXferSize = Size*2;
 742       hi2s->RxXferCount = Size*2;
 743     }
 744     else
 745     {
 746       hi2s->RxXferSize = Size;
 747       hi2s->RxXferCount = Size;
 748     }
 749     /* Process Locked */
 750     __HAL_LOCK(hi2s);
 751
 752     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 753     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 754
 755     /* Enable TXE and ERR interrupt */
 756     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
 757
 758     /* Check if the I2S is already enabled */
 759     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 760     {
 761       /* Enable I2S peripheral */
 762       __HAL_I2S_ENABLE(hi2s);
 763     }
 764
 765     /* Process Unlocked */
 766     __HAL_UNLOCK(hi2s);
 767
 768     return HAL_OK;
 769   }
 770
 771   else
 772   {
 773     return HAL_BUSY;
 774   }
 775 }
 776
 777 /**
 778   * @brief Transmit an amount of data in non-blocking mode with DMA
 779   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 780   *         the configuration information for I2S module
 781   * @param pData: a 16-bit pointer to the Transmit data buffer.
 782   * @param Size: number of data sample to be sent:
 783   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 784   *       configuration phase, the Size parameter means the number of 16-bit data length
 785   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 786   *       the Size parameter means the number of 16-bit data length.
 787   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 788   *       between Master and Slave(example: audio streaming).
 789   * @retval HAL status
 790   */
 791 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 792 {
 793   uint32_t *tmp;
 794   uint32_t tmp1 = 0, tmp2 = 0;
 795
 796   if((pData == HAL_NULL) || (Size == 0))
 797   {
 798     return  HAL_ERROR;
 799   }
 800
 801   if(hi2s->State == HAL_I2S_STATE_READY)
 802   {
 803     hi2s->pTxBuffPtr = pData;
 804     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 805     tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 806     if((tmp1 == I2S_DATAFORMAT_24B)|| \
 807       (tmp2 == I2S_DATAFORMAT_32B))
 808     {
 809       hi2s->TxXferSize = Size*2;
 810       hi2s->TxXferCount = Size*2;
 811     }
 812     else
 813     {
 814       hi2s->TxXferSize = Size;
 815       hi2s->TxXferCount = Size;
 816     }
 817
 818     /* Process Locked */
 819     __HAL_LOCK(hi2s);
 820
 821     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 822     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 823
 824     /* Set the I2S Tx DMA Half transfert complete callback */
 825     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
 826
 827     /* Set the I2S Tx DMA transfert complete callback */
 828     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
 829
 830     /* Set the DMA error callback */
 831     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
 832
 833     /* Enable the Tx DMA Stream */
 834     tmp = (uint32_t*)&pData;
 835     HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
 836
 837     /* Check if the I2S is already enabled */
 838     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 839     {
 840       /* Enable I2S peripheral */
 841       __HAL_I2S_ENABLE(hi2s);
 842     }
 843
 844      /* Check if the I2S Tx request is already enabled */
 845     if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
 846     {
 847       /* Enable Tx DMA Request */
 848       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
 849     }
 850
 851     /* Process Unlocked */
 852     __HAL_UNLOCK(hi2s);
 853
 854     return HAL_OK;
 855   }
 856   else
 857   {
 858     return HAL_BUSY;
 859   }
 860 }
 861
 862 /**
 863   * @brief Receive an amount of data in non-blocking mode with DMA
 864   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 865   *         the configuration information for I2S module
 866   * @param pData: a 16-bit pointer to the Receive data buffer.
 867   * @param Size: number of data sample to be sent:
 868   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 869   *       configuration phase, the Size parameter means the number of 16-bit data length
 870   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 871   *       the Size parameter means the number of 16-bit data length.
 872   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 873   *       between Master and Slave(example: audio streaming).
 874   * @retval HAL status
 875   */
 876 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 877 {
 878   uint32_t *tmp;
 879   uint32_t tmp1 = 0, tmp2 = 0;
 880
 881   if((pData == HAL_NULL) || (Size == 0))
 882   {
 883     return  HAL_ERROR;
 884   }
 885
 886   if(hi2s->State == HAL_I2S_STATE_READY)
 887   {
 888     hi2s->pRxBuffPtr = pData;
 889     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 890     tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 891     if((tmp1 == I2S_DATAFORMAT_24B)|| \
 892       (tmp2 == I2S_DATAFORMAT_32B))
 893     {
 894       hi2s->RxXferSize = Size*2;
 895       hi2s->RxXferCount = Size*2;
 896     }
 897     else
 898     {
 899       hi2s->RxXferSize = Size;
 900       hi2s->RxXferCount = Size;
 901     }
 902     /* Process Locked */
 903     __HAL_LOCK(hi2s);
 904
 905     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 906     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 907
 908     /* Set the I2S Rx DMA Half transfert complete callback */
 909     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
 910
 911     /* Set the I2S Rx DMA transfert complete callback */
 912     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
 913
 914     /* Set the DMA error callback */
 915     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
 916
 917     /* Check if Master Receiver mode is selected */
 918     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
 919     {
 920       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
 921       access to the SPI_SR register. */
 922       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
 923     }
 924
 925     /* Enable the Rx DMA Stream */
 926     tmp = (uint32_t*)&pData;
 927     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
 928
 929     /* Check if the I2S is already enabled */
 930     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 931     {
 932       /* Enable I2S peripheral */
 933       __HAL_I2S_ENABLE(hi2s);
 934     }
 935
 936      /* Check if the I2S Rx request is already enabled */
 937     if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
 938     {
 939       /* Enable Rx DMA Request */
 940       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
 941     }
 942
 943     /* Process Unlocked */
 944     __HAL_UNLOCK(hi2s);
 945
 946     return HAL_OK;
 947   }
 948   else
 949   {
 950     return HAL_BUSY;
 951   }
 952 }
 953
 954 /**
 955   * @brief Pauses the audio stream playing from the Media.
 956   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 957   *         the configuration information for I2S module
 958   * @retval HAL status
 959   */
 960 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
 961 {
 962   /* Process Locked */
 963   __HAL_LOCK(hi2s);
 964
 965   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
 966   {
 967     /* Disable the I2S DMA Tx request */
 968     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
 969   }
 970   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
 971   {
 972     /* Disable the I2S DMA Rx request */
 973     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
 974   }
 975   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
 976   {
 977     if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
 978     {
 979       /* Disable the I2S DMA Tx request */
 980       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
 981       /* Disable the I2SEx Rx DMA Request */
 982       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
 983     }
 984     else
 985     {
 986       /* Disable the I2S DMA Rx request */
 987       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
 988       /* Disable the I2SEx Tx DMA Request */
 989       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
 990     }
 991   }
 992
 993   /* Process Unlocked */
 994   __HAL_UNLOCK(hi2s);
 995
 996   return HAL_OK;
 997 }
 998
 999 /**
1000   * @brief Resumes the audio stream playing from the Media.
1001   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1002   *         the configuration information for I2S module
1003   * @retval HAL status
1004   */
1005 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
1006 {
1007   /* Process Locked */
1008   __HAL_LOCK(hi2s);
1009
1010   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
1011   {
1012     /* Enable the I2S DMA Tx request */
1013     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
1014   }
1015   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
1016   {
1017     /* Enable the I2S DMA Rx request */
1018     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
1019   }
1020   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
1021   {
1022     if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
1023     {
1024       /* Enable the I2S DMA Tx request */
1025       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
1026       /* Disable the I2SEx Rx DMA Request */
1027       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
1028     }
1029     else
1030     {
1031       /* Enable the I2S DMA Rx request */
1032       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
1033       /* Enable the I2SEx Tx DMA Request */
1034       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
1035     }
1036   }
1037
1038   /* If the I2S peripheral is still not enabled, enable it */
1039   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
1040   {
1041     /* Enable I2S peripheral */
1042     __HAL_I2S_ENABLE(hi2s);
1043   }
1044
1045   /* Process Unlocked */
1046   __HAL_UNLOCK(hi2s);
1047
1048   return HAL_OK;
1049 }
1050
1051 /**
1052   * @brief Resumes the audio stream playing from the Media.
1053   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1054   *         the configuration information for I2S module
1055   * @retval HAL status
1056   */
1057 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
1058 {
1059   /* Process Locked */
1060   __HAL_LOCK(hi2s);
1061
1062   /* Disable the I2S Tx/Rx DMA requests */
1063   hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
1064   hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
1065
1066   if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
1067   {
1068     /* Disable the I2S extended Tx/Rx DMA requests */
1069     I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
1070     I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
1071   }
1072
1073   /* Abort the I2S DMA Stream tx */
1074   if(hi2s->hdmatx != HAL_NULL)
1075   {
1076     HAL_DMA_Abort(hi2s->hdmatx);
1077   }
1078   /* Abort the I2S DMA Stream rx */
1079   if(hi2s->hdmarx != HAL_NULL)
1080   {
1081     HAL_DMA_Abort(hi2s->hdmarx);
1082   }
1083
1084   /* Disable I2S peripheral */
1085   __HAL_I2S_DISABLE(hi2s);
1086
1087   if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
1088   {
1089     /* Disable the I2Sext peripheral */
1090     I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
1091   }
1092
1093   hi2s->State = HAL_I2S_STATE_READY;
1094
1095   /* Process Unlocked */
1096   __HAL_UNLOCK(hi2s);
1097
1098   return HAL_OK;
1099 }
1100
1101 /**
1102   * @brief  This function handles I2S interrupt request.
1103   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1104   *         the configuration information for I2S module
1105   * @retval None
1106   */
1107 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
1108 {
1109   uint32_t tmp1 = 0, tmp2 = 0;
1110   if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
1111   {
1112     if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
1113     {
1114       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
1115       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
1116       /* I2S in mode Receiver ------------------------------------------------*/
1117       if((tmp1 != RESET) && (tmp2 != RESET))
1118       {
1119         I2S_Receive_IT(hi2s);
1120       }
1121
1122       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
1123       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
1124       /* I2S Overrun error interrupt occurred ---------------------------------*/
1125       if((tmp1 != RESET) && (tmp2 != RESET))
1126       {
1127         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1128         hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
1129       }
1130     }
1131
1132     if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
1133     {
1134       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
1135       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
1136       /* I2S in mode Tramitter -----------------------------------------------*/
1137       if((tmp1 != RESET) && (tmp2 != RESET))
1138       {
1139         I2S_Transmit_IT(hi2s);
1140       }
1141
1142       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
1143       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
1144       /* I2S Underrun error interrupt occurred --------------------------------*/
1145       if((tmp1 != RESET) && (tmp2 != RESET))
1146       {
1147         __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1148         hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
1149       }
1150     }
1151   }
1152   else
1153   {
1154     tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1155     tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1156     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
1157     if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
1158     {
1159       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
1160       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
1161       /* I2Sext in mode Receiver ---------------------------------------------*/
1162       if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
1163       {
1164         tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1165         tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1166         /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
1167         the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
1168         if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
1169         {
1170           I2SEx_TransmitReceive_IT(hi2s);
1171         }
1172       }
1173
1174       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
1175       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
1176       /* I2Sext Overrun error interrupt occurred ------------------------------*/
1177       if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
1178       {
1179         /* Clear I2Sext OVR Flag */
1180         I2SxEXT(hi2s->Instance)->DR;
1181         I2SxEXT(hi2s->Instance)->SR;
1182         hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
1183       }
1184
1185       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
1186       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
1187       /* I2S in mode Tramitter -----------------------------------------------*/
1188       if((tmp1 != RESET) && (tmp2 != RESET))
1189       {
1190         tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1191         tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1192         /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
1193         the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
1194         if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
1195         {
1196           I2SEx_TransmitReceive_IT(hi2s);
1197         }
1198       }
1199
1200       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
1201       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
1202       /* I2S Underrun error interrupt occurred --------------------------------*/
1203       if((tmp1 != RESET) && (tmp2 != RESET))
1204       {
1205         __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1206         hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
1207       }
1208     }
1209     /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
1210     else
1211     {
1212       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
1213       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
1214       /* I2S in mode Receiver ------------------------------------------------*/
1215       if((tmp1 != RESET) && (tmp2 != RESET))
1216       {
1217         tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1218         tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1219         /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
1220         the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
1221         if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
1222         {
1223           I2SEx_TransmitReceive_IT(hi2s);
1224         }
1225       }
1226
1227       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
1228       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
1229       /* I2S Overrun error interrupt occurred ---------------------------------*/
1230       if((tmp1 != RESET) && (tmp2 != RESET))
1231       {
1232         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1233         hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
1234       }
1235
1236       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
1237       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
1238       /* I2Sext in mode Tramitter --------------------------------------------*/
1239       if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
1240       {
1241         tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1242         tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
1243         /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
1244         the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
1245         if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
1246         {
1247           I2SEx_TransmitReceive_IT(hi2s);
1248         }
1249       }
1250
1251       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
1252       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
1253       /* I2Sext Underrun error interrupt occurred -----------------------------*/
1254       if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
1255       {
1256         /* Clear I2Sext UDR Flag */
1257         I2SxEXT(hi2s->Instance)->SR;
1258         hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
1259       }
1260     }
1261   }
1262
1263   /* Call the Error call Back in case of Errors */
1264   if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
1265   {
1266     /* Set the I2S state ready to be able to start again the process */
1267     hi2s->State= HAL_I2S_STATE_READY;
1268     HAL_I2S_ErrorCallback(hi2s);
1269   }
1270 }
1271
1272 /**
1273   * @brief Tx Transfer Half completed callbacks
1274   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1275   *         the configuration information for I2S module
1276   * @retval None
1277   */
1278  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1279 {
1280   /* NOTE : This function Should not be modified, when the callback is needed,
1281             the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file
1282    */
1283 }
1284
1285 /**
1286   * @brief Tx Transfer completed callbacks
1287   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1288   *         the configuration information for I2S module
1289   * @retval None
1290   */
1291  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
1292 {
1293   /* NOTE : This function Should not be modified, when the callback is needed,
1294             the HAL_I2S_TxCpltCallback could be implenetd in the user file
1295    */
1296 }
1297
1298 /**
1299   * @brief Rx Transfer half completed callbacks
1300   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1301   *         the configuration information for I2S module
1302   * @retval None
1303   */
1304 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1305 {
1306   /* NOTE : This function Should not be modified, when the callback is needed,
1307             the HAL_I2S_RxCpltCallback could be implenetd in the user file
1308    */
1309 }
1310
1311 /**
1312   * @brief Rx Transfer completed callbacks
1313   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1314   *         the configuration information for I2S module
1315   * @retval None
1316   */
1317 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
1318 {
1319   /* NOTE : This function Should not be modified, when the callback is needed,
1320             the HAL_I2S_RxCpltCallback could be implenetd in the user file
1321    */
1322 }
1323
1324 /**
1325   * @brief I2S error callbacks
1326   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1327   *         the configuration information for I2S module
1328   * @retval None
1329   */
1330  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
1331 {
1332   /* NOTE : This function Should not be modified, when the callback is needed,
1333             the HAL_I2S_ErrorCallback could be implenetd in the user file
1334    */
1335 }
1336
1337 /**
1338   * @}
1339   */
1340
1341 /** @defgroup I2S_Group3 Peripheral State and Errors functions
1342   *  @brief   Peripheral State functions
1343   *
1344 @verbatim
1345  ===============================================================================
1346                       ##### Peripheral State and Errors functions #####
1347  ===============================================================================
1348     [..]
1349     This subsection permits to get in run-time the status of the peripheral
1350     and the data flow.
1351
1352 @endverbatim
1353   * @{
1354   */
1355
1356 /**
1357   * @brief  Return the I2S state
1358   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1359   *         the configuration information for I2S module
1360   * @retval HAL state
1361   */
1362 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
1363 {
1364   return hi2s->State;
1365 }
1366
1367 /**
1368   * @brief  Return the I2S error code
1369   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1370   *         the configuration information for I2S module
1371   * @retval I2S Error Code
1372   */
1373 HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
1374 {
1375   return hi2s->ErrorCode;
1376 }
1377
1378 /**
1379   * @}
1380   */
1381
1382 /**
1383   * @brief DMA I2S transmit process complete callback
1384   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1385   *                the configuration information for the specified DMA module.
1386   * @retval None
1387   */
1388 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
1389 {
1390   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1391
1392   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
1393   {
1394     hi2s->TxXferCount = 0;
1395
1396     /* Disable Tx DMA Request */
1397     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
1398
1399     if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
1400     {
1401       /* Disable Rx DMA Request for the slave*/
1402       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
1403     }
1404
1405     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
1406     {
1407       if(hi2s->RxXferCount == 0)
1408       {
1409         hi2s->State = HAL_I2S_STATE_READY;
1410       }
1411     }
1412     else
1413     {
1414       hi2s->State = HAL_I2S_STATE_READY;
1415     }
1416   }
1417   HAL_I2S_TxCpltCallback(hi2s);
1418 }
1419
1420 /**
1421   * @brief DMA I2S transmit process half complete callback
1422   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1423   *                the configuration information for the specified DMA module.
1424   * @retval None
1425   */
1426 void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1427 {
1428   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1429
1430   HAL_I2S_TxHalfCpltCallback(hi2s);
1431 }
1432
1433 /**
1434   * @brief DMA I2S receive process complete callback
1435   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1436   *                the configuration information for the specified DMA module.
1437   * @retval None
1438   */
1439 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
1440 {
1441   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1442
1443   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
1444   {
1445     /* Disable Rx DMA Request */
1446     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
1447
1448     if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
1449     {
1450       /* Disable Tx DMA Request for the slave*/
1451       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
1452     }
1453
1454     hi2s->RxXferCount = 0;
1455     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
1456     {
1457       if(hi2s->TxXferCount == 0)
1458       {
1459         hi2s->State = HAL_I2S_STATE_READY;
1460       }
1461     }
1462     else
1463     {
1464       hi2s->State = HAL_I2S_STATE_READY;
1465     }
1466   }
1467   HAL_I2S_RxCpltCallback(hi2s);
1468 }
1469
1470 /**
1471   * @brief DMA I2S receive process half complete callback
1472   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1473   *                the configuration information for the specified DMA module.
1474   * @retval None
1475   */
1476 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
1477 {
1478   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1479
1480   HAL_I2S_RxHalfCpltCallback(hi2s);
1481 }
1482
1483 /**
1484   * @brief DMA I2S communication error callback
1485   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1486   *                the configuration information for the specified DMA module.
1487   * @retval None
1488   */
1489 void I2S_DMAError(DMA_HandleTypeDef *hdma)
1490 {
1491   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1492
1493   hi2s->TxXferCount = 0;
1494   hi2s->RxXferCount = 0;
1495
1496   hi2s->State= HAL_I2S_STATE_READY;
1497
1498   hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
1499   HAL_I2S_ErrorCallback(hi2s);
1500 }
1501
1502 /**
1503   * @brief Transmit an amount of data in non-blocking mode with Interrupt
1504   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1505   *         the configuration information for I2S module
1506   * @retval HAL status
1507   */
1508 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
1509 {
1510  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
1511   {
1512     /* Process Locked */
1513     __HAL_LOCK(hi2s);
1514
1515     /* Transmit data */
1516     hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
1517
1518     hi2s->TxXferCount--;
1519
1520     if(hi2s->TxXferCount == 0)
1521     {
1522       /* Disable TXE and ERR interrupt */
1523       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1524
1525       hi2s->State = HAL_I2S_STATE_READY;
1526
1527       /* Process Unlocked */
1528       __HAL_UNLOCK(hi2s);
1529       HAL_I2S_TxCpltCallback(hi2s);
1530     }
1531     else
1532     {
1533       /* Process Unlocked */
1534       __HAL_UNLOCK(hi2s);
1535     }
1536
1537     return HAL_OK;
1538   }
1539
1540   else
1541   {
1542     return HAL_BUSY;
1543   }
1544 }
1545
1546 /**
1547   * @brief Receive an amount of data in non-blocking mode with Interrupt
1548   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1549   *         the configuration information for I2S module
1550   * @retval HAL status
1551   */
1552 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
1553 {
1554   if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
1555   {
1556     /* Process Locked */
1557     __HAL_LOCK(hi2s);
1558
1559     /* Receive data */
1560     (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
1561
1562     hi2s->RxXferCount--;
1563
1564     /* Check if Master Receiver mode is selected */
1565     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
1566     {
1567       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
1568       access to the SPI_SR register. */
1569       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1570     }
1571
1572     if(hi2s->RxXferCount == 0)
1573     {
1574       /* Disable RXNE and ERR interrupt */
1575       __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
1576
1577       hi2s->State = HAL_I2S_STATE_READY;
1578
1579       /* Process Unlocked */
1580       __HAL_UNLOCK(hi2s);
1581
1582       HAL_I2S_RxCpltCallback(hi2s);
1583     }
1584     else
1585     {
1586       /* Process Unlocked */
1587       __HAL_UNLOCK(hi2s);
1588     }
1589
1590     return HAL_OK;
1591   }
1592   else
1593   {
1594     return HAL_BUSY;
1595   }
1596 }
1597
1598 /**
1599   * @brief This function handles I2S Communication Timeout.
1600   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1601   *         the configuration information for I2S module
1602   * @param Flag: Flag checked
1603   * @param State: Value of the flag expected
1604   * @param Timeout: Duration of the timeout
1605   * @retval HAL status
1606   */
1607 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
1608 {
1609   uint32_t tickstart = 0;
1610
1611   /* Get tick */
1612   tickstart = HAL_GetTick();
1613
1614   /* Wait until flag is set */
1615   if(Status == RESET)
1616   {
1617     while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
1618     {
1619       if(Timeout != HAL_MAX_DELAY)
1620       {
1621         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1622         {
1623           /* Set the I2S State ready */
1624           hi2s->State= HAL_I2S_STATE_READY;
1625
1626           /* Process Unlocked */
1627           __HAL_UNLOCK(hi2s);
1628
1629           return HAL_TIMEOUT;
1630         }
1631       }
1632     }
1633   }
1634   else
1635   {
1636     while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
1637     {
1638       if(Timeout != HAL_MAX_DELAY)
1639       {
1640         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1641         {
1642           /* Set the I2S State ready */
1643           hi2s->State= HAL_I2S_STATE_READY;
1644
1645           /* Process Unlocked */
1646           __HAL_UNLOCK(hi2s);
1647
1648           return HAL_TIMEOUT;
1649         }
1650       }
1651     }
1652   }
1653   return HAL_OK;
1654 }
1655
1656 /**
1657   * @}
1658   */
1659
1660 #endif /* HAL_I2S_MODULE_ENABLED */
1661 /**
1662   * @}
1663   */
1664
1665 /**
1666   * @}
1667   */
1668
1669 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/