tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_nor.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   NOR HAL module driver.
   8   *          This file provides a generic firmware to drive NOR memories mounted
   9   *          as external device.
  10   *
  11   @verbatim
  12   ==============================================================================
  13                      ##### How to use this driver #####
  14   ==============================================================================
  15     [..]
  16       This driver is a generic layered driver which contains a set of APIs used to
  17       control NOR flash memories. It uses the FMC/FSMC layer functions to interface
  18       with NOR devices. This driver is used as follows:
  19
  20       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
  21           with control and timing parameters for both normal and extended mode.
  22
  23       (+) Read NOR flash memory manufacturer code and device IDs using the function
  24           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
  25           structure declared by the function caller.
  26
  27       (+) Access NOR flash memory by read/write data unit operations using the functions
  28           HAL_NOR_Read(), HAL_NOR_Program().
  29
  30       (+) Perform NOR flash erase block/chip operations using the functions
  31           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
  32
  33       (+) Read the NOR flash CFI (common flash interface) IDs using the function
  34           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
  35           structure declared by the function caller.
  36
  37       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
  38           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
  39
  40       (+) You can monitor the NOR device HAL state by calling the function
  41           HAL_NOR_GetState()
  42     [..]
  43      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
  44          If a NOR flash device contains different operations and/or implementations,
  45          it should be implemented separately.
  46
  47      *** NOR HAL driver macros list ***
  48      =============================================
  49      [..]
  50        Below the list of most used macros in NOR HAL driver.
  51
  52       (+) __NOR_WRITE : NOR memory write data to specified address
  53
  54   @endverbatim
  55   ******************************************************************************
  56   * @attention
  57   *
  58   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  59   *
  60   * Redistribution and use in source and binary forms, with or without modification,
  61   * are permitted provided that the following conditions are met:
  62   *   1. Redistributions of source code must retain the above copyright notice,
  63   *      this list of conditions and the following disclaimer.
  64   *   2. Redistributions in binary form must reproduce the above copyright notice,
  65   *      this list of conditions and the following disclaimer in the documentation
  66   *      and/or other materials provided with the distribution.
  67   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  68   *      may be used to endorse or promote products derived from this software
  69   *      without specific prior written permission.
  70   *
  71   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  72   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  73   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  74   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  75   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  76   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  77   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  78   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  79   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  80   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  81   *
  82   ******************************************************************************
  83   */
  84
  85 /* Includes ------------------------------------------------------------------*/
  86 #include "stm32f4xx_hal.h"
  87
  88 /** @addtogroup STM32F4xx_HAL_Driver
  89   * @{
  90   */
  91
  92 /** @defgroup NOR
  93   * @brief NOR driver modules
  94   * @{
  95   */
  96 #ifdef HAL_NOR_MODULE_ENABLED
  97 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
  98
  99 /* Private typedef -----------------------------------------------------------*/
 100 /* Private define ------------------------------------------------------------*/
 101 /* Private macro -------------------------------------------------------------*/
 102 /* Private variables ---------------------------------------------------------*/
 103 /* Private function prototypes -----------------------------------------------*/
 104
 105
 106 /* Private functions ---------------------------------------------------------*/
 107
 108 /** @defgroup NOR_Private_Functions
 109   * @{
 110   */
 111
 112 /** @defgroup NOR_Group1 Initialization and de-initialization functions
 113   * @brief    Initialization and Configuration functions
 114   *
 115   @verbatim
 116   ==============================================================================
 117            ##### NOR Initialization and de_initialization functions #####
 118   ==============================================================================
 119   [..]
 120     This section provides functions allowing to initialize/de-initialize
 121     the NOR memory
 122
 123 @endverbatim
 124   * @{
 125   */
 126
 127 /**
 128   * @brief  Perform the NOR memory Initialization sequence
 129   * @param  hnor: pointer to the NOR handle
 130   * @param  Timing: pointer to NOR control timing structure
 131   * @param  ExtTiming: pointer to NOR extended mode timing structure
 132   * @retval HAL status
 133   */
 134 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
 135 {
 136   /* Check the NOR handle parameter */
 137   if(hnor == HAL_NULL)
 138   {
 139      return HAL_ERROR;
 140   }
 141
 142   if(hnor->State == HAL_NOR_STATE_RESET)
 143   {
 144     /* Initialize the low level hardware (MSP) */
 145     HAL_NOR_MspInit(hnor);
 146   }
 147
 148   /* Initialize NOR control Interface */
 149   FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
 150
 151   /* Initialize NOR timing Interface */
 152   FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
 153
 154   /* Initialize NOR extended mode timing Interface */
 155   FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
 156
 157   /* Enable the NORSRAM device */
 158   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
 159
 160   /* Check the NOR controller state */
 161   hnor->State = HAL_NOR_STATE_READY;
 162
 163   return HAL_OK;
 164 }
 165
 166 /**
 167   * @brief  Perform NOR memory De-Initialization sequence
 168   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 169   *                the configuration information for NOR module.
 170   * @retval HAL status
 171   */
 172 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
 173 {
 174   /* De-Initialize the low level hardware (MSP) */
 175   HAL_NOR_MspDeInit(hnor);
 176
 177   /* Configure the NOR registers with their reset values */
 178   FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
 179
 180   /* Update the NOR controller state */
 181   hnor->State = HAL_NOR_STATE_RESET;
 182
 183   /* Release Lock */
 184   __HAL_UNLOCK(hnor);
 185
 186   return HAL_OK;
 187 }
 188
 189 /**
 190   * @brief  NOR MSP Init
 191   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 192   *                the configuration information for NOR module.
 193   * @retval None
 194   */
 195 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
 196 {
 197   /* NOTE : This function Should not be modified, when the callback is needed,
 198             the HAL_NOR_MspInit could be implemented in the user file
 199    */
 200 }
 201
 202 /**
 203   * @brief  NOR MSP DeInit
 204   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 205   *                the configuration information for NOR module.
 206   * @retval None
 207   */
 208 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
 209 {
 210   /* NOTE : This function Should not be modified, when the callback is needed,
 211             the HAL_NOR_MspDeInit could be implemented in the user file
 212    */
 213 }
 214
 215 /**
 216   * @brief  NOR BSP Wait fro Ready/Busy signal
 217   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 218   *                the configuration information for NOR module.
 219   * @param  Timeout: Maximum timeout value
 220   * @retval None
 221   */
 222 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
 223 {
 224   /* NOTE : This function Should not be modified, when the callback is needed,
 225             the HAL_NOR_BspWait could be implemented in the user file
 226    */
 227 }
 228
 229 /**
 230   * @}
 231   */
 232
 233 /** @defgroup NOR_Group2 Input and Output functions
 234   * @brief    Input Output and memory control functions
 235   *
 236   @verbatim
 237   ==============================================================================
 238                 ##### NOR Input and Output functions #####
 239   ==============================================================================
 240   [..]
 241     This section provides functions allowing to use and control the NOR memory
 242
 243 @endverbatim
 244   * @{
 245   */
 246
 247 /**
 248   * @brief  Read NOR flash IDs
 249   * @param  hnor: pointer to the NOR handle
 250   * @param  pNOR_ID : pointer to NOR ID structure
 251   * @retval HAL status
 252   */
 253 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
 254 {
 255   uint32_t deviceAddress = 0;
 256
 257   /* Process Locked */
 258   __HAL_LOCK(hnor);
 259
 260   /* Check the NOR controller state */
 261   if(hnor->State == HAL_NOR_STATE_BUSY)
 262   {
 263      return HAL_BUSY;
 264   }
 265
 266   /* Select the NOR device address */
 267   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 268   {
 269     deviceAddress = NOR_MEMORY_ADRESS1;
 270   }
 271   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 272   {
 273     deviceAddress = NOR_MEMORY_ADRESS2;
 274   }
 275   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 276   {
 277     deviceAddress = NOR_MEMORY_ADRESS3;
 278   }
 279   else /* FMC_NORSRAM_BANK4 */
 280   {
 281     deviceAddress = NOR_MEMORY_ADRESS4;
 282   }
 283
 284   /* Update the NOR controller state */
 285   hnor->State = HAL_NOR_STATE_BUSY;
 286
 287   /* Send read ID command */
 288   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
 289   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
 290   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090);
 291
 292   /* Read the NOR IDs */
 293   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS);
 294   pNOR_ID->Device_Code1      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
 295   pNOR_ID->Device_Code2      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
 296   pNOR_ID->Device_Code3      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
 297
 298   /* Check the NOR controller state */
 299   hnor->State = HAL_NOR_STATE_READY;
 300
 301   /* Process unlocked */
 302   __HAL_UNLOCK(hnor);
 303
 304   return HAL_OK;
 305 }
 306
 307 /**
 308   * @brief  Returns the NOR memory to Read mode.
 309   * @param  hnor: pointer to the NOR handle
 310   * @retval HAL status
 311   */
 312 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
 313 {
 314   uint32_t deviceAddress = 0;
 315
 316   /* Process Locked */
 317   __HAL_LOCK(hnor);
 318
 319   /* Check the NOR controller state */
 320   if(hnor->State == HAL_NOR_STATE_BUSY)
 321   {
 322      return HAL_BUSY;
 323   }
 324
 325   /* Select the NOR device address */
 326   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 327   {
 328     deviceAddress = NOR_MEMORY_ADRESS1;
 329   }
 330   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 331   {
 332     deviceAddress = NOR_MEMORY_ADRESS2;
 333   }
 334   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 335   {
 336     deviceAddress = NOR_MEMORY_ADRESS3;
 337   }
 338   else /* FMC_NORSRAM_BANK4 */
 339   {
 340     deviceAddress = NOR_MEMORY_ADRESS4;
 341   }
 342
 343   __NOR_WRITE(deviceAddress, 0x00F0);
 344
 345   /* Check the NOR controller state */
 346   hnor->State = HAL_NOR_STATE_READY;
 347
 348   /* Process unlocked */
 349   __HAL_UNLOCK(hnor);
 350
 351   return HAL_OK;
 352 }
 353
 354 /**
 355   * @brief  Read data from NOR memory
 356   * @param  hnor: pointer to the NOR handle
 357   * @param  pAddress: pointer to Device address
 358   * @param  pData : pointer to read data
 359   * @retval HAL status
 360   */
 361 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
 362 {
 363   uint32_t deviceAddress = 0;
 364
 365   /* Process Locked */
 366   __HAL_LOCK(hnor);
 367
 368   /* Check the NOR controller state */
 369   if(hnor->State == HAL_NOR_STATE_BUSY)
 370   {
 371      return HAL_BUSY;
 372   }
 373
 374   /* Select the NOR device address */
 375   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 376   {
 377     deviceAddress = NOR_MEMORY_ADRESS1;
 378   }
 379   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 380   {
 381     deviceAddress = NOR_MEMORY_ADRESS2;
 382   }
 383   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 384   {
 385     deviceAddress = NOR_MEMORY_ADRESS3;
 386   }
 387   else /* FMC_NORSRAM_BANK4 */
 388   {
 389     deviceAddress = NOR_MEMORY_ADRESS4;
 390   }
 391
 392   /* Update the NOR controller state */
 393   hnor->State = HAL_NOR_STATE_BUSY;
 394
 395   /* Send read data command */
 396   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
 397   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
 398   __NOR_WRITE(pAddress, 0x00F0);
 399
 400   /* Read the data */
 401   *pData = *(__IO uint32_t *)pAddress;
 402
 403   /* Check the NOR controller state */
 404   hnor->State = HAL_NOR_STATE_READY;
 405
 406   /* Process unlocked */
 407   __HAL_UNLOCK(hnor);
 408
 409   return HAL_OK;
 410 }
 411
 412 /**
 413   * @brief  Program data to NOR memory
 414   * @param  hnor: pointer to the NOR handle
 415   * @param  pAddress: Device address
 416   * @param  pData : pointer to the data to write
 417   * @retval HAL status
 418   */
 419 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
 420 {
 421   uint32_t deviceAddress = 0;
 422
 423   /* Process Locked */
 424   __HAL_LOCK(hnor);
 425
 426   /* Check the NOR controller state */
 427   if(hnor->State == HAL_NOR_STATE_BUSY)
 428   {
 429      return HAL_BUSY;
 430   }
 431
 432   /* Select the NOR device address */
 433   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 434   {
 435     deviceAddress = NOR_MEMORY_ADRESS1;
 436   }
 437   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 438   {
 439     deviceAddress = NOR_MEMORY_ADRESS2;
 440   }
 441   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 442   {
 443     deviceAddress = NOR_MEMORY_ADRESS3;
 444   }
 445   else /* FMC_NORSRAM_BANK4 */
 446   {
 447     deviceAddress = NOR_MEMORY_ADRESS4;
 448   }
 449
 450   /* Update the NOR controller state */
 451   hnor->State = HAL_NOR_STATE_BUSY;
 452
 453   /* Send program data command */
 454   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
 455   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
 456   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0);
 457
 458   /* Write the data */
 459   __NOR_WRITE(pAddress, *pData);
 460
 461   /* Check the NOR controller state */
 462   hnor->State = HAL_NOR_STATE_READY;
 463
 464   /* Process unlocked */
 465   __HAL_UNLOCK(hnor);
 466
 467   return HAL_OK;
 468 }
 469
 470 /**
 471   * @brief  Reads a half-word buffer from the NOR memory.
 472   * @param  hnor: pointer to the NOR handle
 473   * @param  uwAddress: NOR memory internal address to read from.
 474   * @param  pData: pointer to the buffer that receives the data read from the
 475   *         NOR memory.
 476   * @param  uwBufferSize : number of Half word to read.
 477   * @retval HAL status
 478   */
 479 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
 480 {
 481   uint32_t deviceAddress = 0;
 482
 483   /* Process Locked */
 484   __HAL_LOCK(hnor);
 485
 486   /* Check the NOR controller state */
 487   if(hnor->State == HAL_NOR_STATE_BUSY)
 488   {
 489      return HAL_BUSY;
 490   }
 491
 492   /* Select the NOR device address */
 493   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 494   {
 495     deviceAddress = NOR_MEMORY_ADRESS1;
 496   }
 497   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 498   {
 499     deviceAddress = NOR_MEMORY_ADRESS2;
 500   }
 501   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 502   {
 503     deviceAddress = NOR_MEMORY_ADRESS3;
 504   }
 505   else /* FMC_NORSRAM_BANK4 */
 506   {
 507     deviceAddress = NOR_MEMORY_ADRESS4;
 508   }
 509
 510   /* Update the NOR controller state */
 511   hnor->State = HAL_NOR_STATE_BUSY;
 512
 513   /* Send read data command */
 514   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
 515   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
 516   __NOR_WRITE(uwAddress, 0x00F0);
 517
 518   /* Read buffer */
 519   while( uwBufferSize > 0)
 520   {
 521     *pData++ = *(__IO uint16_t *)uwAddress;
 522     uwAddress += 2;
 523     uwBufferSize--;
 524   }
 525
 526   /* Check the NOR controller state */
 527   hnor->State = HAL_NOR_STATE_READY;
 528
 529   /* Process unlocked */
 530   __HAL_UNLOCK(hnor);
 531
 532   return HAL_OK;
 533 }
 534
 535 /**
 536   * @brief  Writes a half-word buffer to the NOR memory. This function must be used
 537             only with S29GL128P NOR memory.
 538   * @param  hnor: pointer to the NOR handle
 539   * @param  uwAddress: NOR memory internal start write address
 540   * @param  pData: pointer to source data buffer.
 541   * @param  uwBufferSize: Size of the buffer to write
 542   * @retval HAL status
 543   */
 544 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
 545 {
 546   uint32_t lastloadedaddress = 0;
 547   uint32_t currentaddress = 0;
 548   uint32_t endaddress = 0;
 549   uint32_t deviceAddress = 0;
 550
 551   /* Process Locked */
 552   __HAL_LOCK(hnor);
 553
 554   /* Check the NOR controller state */
 555   if(hnor->State == HAL_NOR_STATE_BUSY)
 556   {
 557      return HAL_BUSY;
 558   }
 559
 560   /* Select the NOR device address */
 561   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 562   {
 563     deviceAddress = NOR_MEMORY_ADRESS1;
 564   }
 565   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 566   {
 567     deviceAddress = NOR_MEMORY_ADRESS2;
 568   }
 569   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 570   {
 571     deviceAddress = NOR_MEMORY_ADRESS3;
 572   }
 573   else /* FMC_NORSRAM_BANK4 */
 574   {
 575     deviceAddress = NOR_MEMORY_ADRESS4;
 576   }
 577
 578   /* Update the NOR controller state */
 579   hnor->State = HAL_NOR_STATE_BUSY;
 580
 581   /* Initialize variables */
 582   currentaddress    = uwAddress;
 583   endaddress        = uwAddress + uwBufferSize - 1;
 584   lastloadedaddress = uwAddress;
 585
 586   /* Issue unlock command sequence */
 587   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
 588   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
 589
 590   /* Write Buffer Load Command */
 591   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
 592   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
 593
 594   /* Load Data into NOR Buffer */
 595   while(currentaddress <= endaddress)
 596   {
 597     /* Store last loaded address & data value (for polling) */
 598     lastloadedaddress = currentaddress;
 599
 600     __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
 601
 602     currentaddress += 1;
 603   }
 604
 605   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
 606
 607   /* Check the NOR controller state */
 608   hnor->State = HAL_NOR_STATE_READY;
 609
 610   /* Process unlocked */
 611   __HAL_UNLOCK(hnor);
 612
 613   return HAL_OK;
 614
 615 }
 616
 617 /**
 618   * @brief  Erase the specified block of the NOR memory
 619   * @param  hnor: pointer to the NOR handle
 620   * @param  BlockAddress : Block to erase address
 621   * @param  Address: Device address
 622   * @retval HAL status
 623   */
 624 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
 625 {
 626   uint32_t deviceAddress = 0;
 627
 628   /* Process Locked */
 629   __HAL_LOCK(hnor);
 630
 631   /* Check the NOR controller state */
 632   if(hnor->State == HAL_NOR_STATE_BUSY)
 633   {
 634      return HAL_BUSY;
 635   }
 636
 637   /* Select the NOR device address */
 638   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 639   {
 640     deviceAddress = NOR_MEMORY_ADRESS1;
 641   }
 642   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 643   {
 644     deviceAddress = NOR_MEMORY_ADRESS2;
 645   }
 646   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 647   {
 648     deviceAddress = NOR_MEMORY_ADRESS3;
 649   }
 650   else /* FMC_NORSRAM_BANK4 */
 651   {
 652     deviceAddress = NOR_MEMORY_ADRESS4;
 653   }
 654
 655   /* Update the NOR controller state */
 656   hnor->State = HAL_NOR_STATE_BUSY;
 657
 658   /* Send block erase command sequence */
 659   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
 660   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
 661   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
 662   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
 663   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
 664   __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
 665
 666   /* Check the NOR memory status and update the controller state */
 667   hnor->State = HAL_NOR_STATE_READY;
 668
 669   /* Process unlocked */
 670   __HAL_UNLOCK(hnor);
 671
 672   return HAL_OK;
 673
 674 }
 675
 676 /**
 677   * @brief  Erase the entire NOR chip.
 678   * @param  hnor: pointer to the NOR handle
 679   * @param  Address : Device address
 680   * @retval HAL status
 681   */
 682 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
 683 {
 684   uint32_t deviceAddress = 0;
 685
 686   /* Process Locked */
 687   __HAL_LOCK(hnor);
 688
 689   /* Check the NOR controller state */
 690   if(hnor->State == HAL_NOR_STATE_BUSY)
 691   {
 692      return HAL_BUSY;
 693   }
 694
 695   /* Select the NOR device address */
 696   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 697   {
 698     deviceAddress = NOR_MEMORY_ADRESS1;
 699   }
 700   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 701   {
 702     deviceAddress = NOR_MEMORY_ADRESS2;
 703   }
 704   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 705   {
 706     deviceAddress = NOR_MEMORY_ADRESS3;
 707   }
 708   else /* FMC_NORSRAM_BANK4 */
 709   {
 710     deviceAddress = NOR_MEMORY_ADRESS4;
 711   }
 712
 713   /* Update the NOR controller state */
 714   hnor->State = HAL_NOR_STATE_BUSY;
 715
 716   /* Send NOR chip erase command sequence */
 717   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
 718   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
 719   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
 720   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
 721   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
 722   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010);
 723
 724   /* Check the NOR memory status and update the controller state */
 725   hnor->State = HAL_NOR_STATE_READY;
 726
 727   /* Process unlocked */
 728   __HAL_UNLOCK(hnor);
 729
 730   return HAL_OK;
 731 }
 732
 733 /**
 734   * @brief  Read NOR flash CFI IDs
 735   * @param  hnor: pointer to the NOR handle
 736   * @param  pNOR_CFI : pointer to NOR CFI IDs structure
 737   * @retval HAL status
 738   */
 739 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
 740 {
 741   uint32_t deviceAddress = 0;
 742
 743   /* Process Locked */
 744   __HAL_LOCK(hnor);
 745
 746   /* Check the NOR controller state */
 747   if(hnor->State == HAL_NOR_STATE_BUSY)
 748   {
 749      return HAL_BUSY;
 750   }
 751
 752   /* Select the NOR device address */
 753   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
 754   {
 755     deviceAddress = NOR_MEMORY_ADRESS1;
 756   }
 757   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
 758   {
 759     deviceAddress = NOR_MEMORY_ADRESS2;
 760   }
 761   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
 762   {
 763     deviceAddress = NOR_MEMORY_ADRESS3;
 764   }
 765   else /* FMC_NORSRAM_BANK4 */
 766   {
 767     deviceAddress = NOR_MEMORY_ADRESS4;
 768   }
 769
 770   /* Update the NOR controller state */
 771   hnor->State = HAL_NOR_STATE_BUSY;
 772
 773   /* Send read CFI query command */
 774   __NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098);
 775
 776   /* read the NOR CFI information */
 777   pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS);
 778   pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS);
 779   pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS);
 780   pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS);
 781
 782   /* Check the NOR controller state */
 783   hnor->State = HAL_NOR_STATE_READY;
 784
 785   /* Process unlocked */
 786   __HAL_UNLOCK(hnor);
 787
 788   return HAL_OK;
 789 }
 790
 791 /**
 792   * @}
 793   */
 794
 795 /** @defgroup NOR_Group3 Control functions
 796  *  @brief   management functions
 797  *
 798 @verbatim
 799   ==============================================================================
 800                         ##### NOR Control functions #####
 801   ==============================================================================
 802   [..]
 803     This subsection provides a set of functions allowing to control dynamically
 804     the NOR interface.
 805
 806 @endverbatim
 807   * @{
 808   */
 809
 810 /**
 811   * @brief  Enables dynamically NOR write operation.
 812   * @param  hnor: pointer to the NOR handle
 813   * @retval HAL status
 814   */
 815 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
 816 {
 817   /* Process Locked */
 818   __HAL_LOCK(hnor);
 819
 820   /* Enable write operation */
 821   FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
 822
 823   /* Update the NOR controller state */
 824   hnor->State = HAL_NOR_STATE_READY;
 825
 826   /* Process unlocked */
 827   __HAL_UNLOCK(hnor);
 828
 829   return HAL_OK;
 830 }
 831
 832 /**
 833   * @brief  Disables dynamically NOR write operation.
 834   * @param  hnor: pointer to the NOR handle
 835   * @retval HAL status
 836   */
 837 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
 838 {
 839   /* Process Locked */
 840   __HAL_LOCK(hnor);
 841
 842   /* Update the SRAM controller state */
 843   hnor->State = HAL_NOR_STATE_BUSY;
 844
 845   /* Disable write operation */
 846   FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
 847
 848   /* Update the NOR controller state */
 849   hnor->State = HAL_NOR_STATE_PROTECTED;
 850
 851   /* Process unlocked */
 852   __HAL_UNLOCK(hnor);
 853
 854   return HAL_OK;
 855 }
 856
 857 /**
 858   * @}
 859   */
 860
 861 /** @defgroup NOR_Group4 State functions
 862  *  @brief   Peripheral State functions
 863  *
 864 @verbatim
 865   ==============================================================================
 866                       ##### NOR State functions #####
 867   ==============================================================================
 868   [..]
 869     This subsection permits to get in run-time the status of the NOR controller
 870     and the data flow.
 871
 872 @endverbatim
 873   * @{
 874   */
 875
 876 /**
 877   * @brief  return the NOR controller state
 878   * @param  hnor: pointer to the NOR handle
 879   * @retval NOR controller state
 880   */
 881 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
 882 {
 883   return hnor->State;
 884 }
 885
 886 /**
 887   * @brief  Returns the NOR operation status.
 888   * @param  hnor: pointer to the NOR handle
 889   * @param  Address: Device address
 890   * @param  Timeout: NOR progamming Timeout
 891   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
 892   *         or NOR_TIMEOUT
 893   */
 894 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
 895 {
 896   NOR_StatusTypedef status = NOR_ONGOING;
 897   uint16_t tmpSR1 = 0, tmpSR2 = 0;
 898   uint32_t tickstart = 0;
 899
 900   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
 901   HAL_NOR_MspWait(hnor, Timeout);
 902
 903   /* Get the NOR memory operation status -------------------------------------*/
 904   while(status != NOR_SUCCESS)
 905   {
 906     /* Get tick */
 907     tickstart = HAL_GetTick();
 908     /* Check for the Timeout */
 909     if(Timeout != HAL_MAX_DELAY)
 910     {
 911       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
 912       {
 913         status = NOR_TIMEOUT;
 914       }
 915     }
 916
 917     /* Read NOR status register (DQ6 and DQ5) */
 918     tmpSR1 = *(__IO uint16_t *)Address;
 919     tmpSR2 = *(__IO uint16_t *)Address;
 920
 921     /* If DQ6 did not toggle between the two reads then return NOR_Success */
 922     if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
 923     {
 924       return NOR_SUCCESS;
 925     }
 926
 927     if((tmpSR1 & 0x0020) == 0x0020)
 928     {
 929       return NOR_ONGOING;
 930     }
 931
 932     tmpSR1 = *(__IO uint16_t *)Address;
 933     tmpSR2 = *(__IO uint16_t *)Address;
 934
 935     /* If DQ6 did not toggle between the two reads then return NOR_Success */
 936     if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
 937     {
 938       return NOR_SUCCESS;
 939     }
 940
 941     if((tmpSR1 & 0x0020) == 0x0020)
 942     {
 943       return NOR_ERROR;
 944     }
 945   }
 946
 947   /* Return the operation status */
 948   return status;
 949 }
 950
 951 /**
 952   * @}
 953   */
 954
 955 /**
 956   * @}
 957   */
 958 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 959 #endif /* HAL_NOR_MODULE_ENABLED */
 960 /**
 961   * @}
 962   */
 963
 964 /**
 965   * @}
 966   */
 967
 968 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/