tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_spi.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   Header file of SPI HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_HAL_SPI_H
  40 #define __STM32F4xx_HAL_SPI_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx_hal_def.h"
  48
  49 /** @addtogroup STM32F4xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SPI
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /**
  60   * @brief  SPI Configuration Structure definition
  61   */
  62 typedef struct
  63 {
  64   uint32_t Mode;               /*!< Specifies the SPI operating mode.
  65                                     This parameter can be a value of @ref SPI_mode */
  66
  67   uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
  68                                     This parameter can be a value of @ref SPI_Direction_mode */
  69
  70   uint32_t DataSize;           /*!< Specifies the SPI data size.
  71                                     This parameter can be a value of @ref SPI_data_size */
  72
  73   uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
  74                                     This parameter can be a value of @ref SPI_Clock_Polarity */
  75
  76   uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
  77                                     This parameter can be a value of @ref SPI_Clock_Phase */
  78
  79   uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
  80                                     hardware (NSS pin) or by software using the SSI bit.
  81                                     This parameter can be a value of @ref SPI_Slave_Select_management */
  82
  83   uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
  84                                     used to configure the transmit and receive SCK clock.
  85                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
  86                                     @note The communication clock is derived from the master
  87                                     clock. The slave clock does not need to be set */
  88
  89   uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
  90                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
  91
  92   uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
  93                                     This parameter can be a value of @ref SPI_TI_mode */
  94
  95   uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
  96                                     This parameter can be a value of @ref SPI_CRC_Calculation */
  97
  98   uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
  99                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
 100
 101 }SPI_InitTypeDef;
 102
 103 /**
 104   * @brief  HAL SPI State structure definition
 105   */
 106 typedef enum
 107 {
 108   HAL_SPI_STATE_RESET      = 0x00,  /*!< SPI not yet initialized or disabled                */
 109   HAL_SPI_STATE_READY      = 0x01,  /*!< SPI initialized and ready for use                  */
 110   HAL_SPI_STATE_BUSY       = 0x02,  /*!< SPI process is ongoing                             */
 111   HAL_SPI_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
 112   HAL_SPI_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
 113   HAL_SPI_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
 114   HAL_SPI_STATE_ERROR      = 0x03   /*!< SPI error state                                    */
 115
 116 }HAL_SPI_StateTypeDef;
 117
 118 /**
 119   * @brief  HAL SPI Error Code structure definition
 120   */
 121 typedef enum
 122 {
 123   HAL_SPI_ERROR_NONE      = 0x00,    /*!< No error             */
 124   HAL_SPI_ERROR_MODF      = 0x01,    /*!< MODF error           */
 125   HAL_SPI_ERROR_CRC       = 0x02,    /*!< CRC error            */
 126   HAL_SPI_ERROR_OVR       = 0x04,    /*!< OVR error            */
 127   HAL_SPI_ERROR_FRE       = 0x08,    /*!< FRE error            */
 128   HAL_SPI_ERROR_DMA       = 0x10,    /*!< DMA transfer error   */
 129   HAL_SPI_ERROR_FLAG      = 0x20     /*!< Flag: RXNE,TXE, BSY  */
 130
 131 }HAL_SPI_ErrorTypeDef;
 132
 133 /**
 134   * @brief  SPI handle Structure definition
 135   */
 136 typedef struct __SPI_HandleTypeDef
 137 {
 138   SPI_TypeDef                *Instance;    /* SPI registers base address */
 139
 140   SPI_InitTypeDef            Init;         /* SPI communication parameters */
 141
 142   uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
 143
 144   uint16_t                   TxXferSize;   /* SPI Tx transfer size */
 145
 146   uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
 147
 148   uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
 149
 150   uint16_t                   RxXferSize;   /* SPI Rx transfer size */
 151
 152   uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
 153
 154   DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA handle parameters */
 155
 156   DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA handle parameters */
 157
 158   void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
 159
 160   void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
 161
 162   HAL_LockTypeDef            Lock;         /* SPI locking object */
 163
 164   __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
 165
 166   __IO HAL_SPI_ErrorTypeDef  ErrorCode;         /* SPI Error code */
 167
 168 }SPI_HandleTypeDef;
 169
 170 /* Exported constants --------------------------------------------------------*/
 171
 172 /** @defgroup SPI_Exported_Constants
 173   * @{
 174   */
 175
 176 /** @defgroup SPI_mode
 177   * @{
 178   */
 179 #define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
 180 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 181
 182 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
 183                            ((MODE) == SPI_MODE_MASTER))
 184 /**
 185   * @}
 186   */
 187
 188 /** @defgroup SPI_Direction_mode
 189   * @{
 190   */
 191 #define SPI_DIRECTION_2LINES             ((uint32_t)0x00000000)
 192 #define SPI_DIRECTION_2LINES_RXONLY      SPI_CR1_RXONLY
 193 #define SPI_DIRECTION_1LINE              SPI_CR1_BIDIMODE
 194
 195 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
 196                                      ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
 197                                      ((MODE) == SPI_DIRECTION_1LINE))
 198
 199 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
 200                                                 ((MODE) == SPI_DIRECTION_1LINE))
 201
 202 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
 203
 204 /**
 205   * @}
 206   */
 207
 208 /** @defgroup SPI_data_size
 209   * @{
 210   */
 211 #define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
 212 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
 213
 214 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
 215                                    ((DATASIZE) == SPI_DATASIZE_8BIT))
 216 /**
 217   * @}
 218   */
 219
 220 /** @defgroup SPI_Clock_Polarity
 221   * @{
 222   */
 223 #define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
 224 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 225
 226 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
 227                            ((CPOL) == SPI_POLARITY_HIGH))
 228 /**
 229   * @}
 230   */
 231
 232 /** @defgroup SPI_Clock_Phase
 233   * @{
 234   */
 235 #define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
 236 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 237
 238 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
 239                            ((CPHA) == SPI_PHASE_2EDGE))
 240 /**
 241   * @}
 242   */
 243
 244 /** @defgroup SPI_Slave_Select_management
 245   * @{
 246   */
 247 #define SPI_NSS_SOFT                    SPI_CR1_SSM
 248 #define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
 249 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
 250
 251 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
 252                          ((NSS) == SPI_NSS_HARD_INPUT) || \
 253                          ((NSS) == SPI_NSS_HARD_OUTPUT))
 254 /**
 255   * @}
 256   */
 257
 258 /** @defgroup SPI_BaudRate_Prescaler
 259   * @{
 260   */
 261 #define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
 262 #define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
 263 #define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
 264 #define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
 265 #define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
 266 #define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
 267 #define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
 268 #define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
 269
 270 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
 271                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
 272                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
 273                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
 274                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
 275                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
 276                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
 277                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
 278 /**
 279   * @}
 280   */
 281
 282 /** @defgroup SPI_MSB_LSB_transmission
 283   * @{
 284   */
 285 #define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
 286 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 287
 288 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
 289                                ((BIT) == SPI_FIRSTBIT_LSB))
 290 /**
 291   * @}
 292   */
 293
 294 /** @defgroup SPI_TI_mode
 295   * @{
 296   */
 297 #define SPI_TIMODE_DISABLED             ((uint32_t)0x00000000)
 298 #define SPI_TIMODE_ENABLED              SPI_CR2_FRF
 299
 300 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
 301                              ((MODE) == SPI_TIMODE_ENABLED))
 302 /**
 303   * @}
 304   */
 305
 306 /** @defgroup SPI_CRC_Calculation
 307   * @{
 308   */
 309 #define SPI_CRCCALCULATION_DISABLED     ((uint32_t)0x00000000)
 310 #define SPI_CRCCALCULATION_ENABLED      SPI_CR1_CRCEN
 311
 312 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
 313                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
 314 /**
 315   * @}
 316   */
 317
 318 /** @defgroup SPI_Interrupt_configuration_definition
 319   * @{
 320   */
 321 #define SPI_IT_TXE                      SPI_CR2_TXEIE
 322 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
 323 #define SPI_IT_ERR                      SPI_CR2_ERRIE
 324 /**
 325   * @}
 326   */
 327
 328 /** @defgroup SPI_Flag_definition
 329   * @{
 330   */
 331 #define SPI_FLAG_RXNE                   SPI_SR_RXNE
 332 #define SPI_FLAG_TXE                    SPI_SR_TXE
 333 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
 334 #define SPI_FLAG_MODF                   SPI_SR_MODF
 335 #define SPI_FLAG_OVR                    SPI_SR_OVR
 336 #define SPI_FLAG_BSY                    SPI_SR_BSY
 337 #define SPI_FLAG_FRE                    SPI_SR_FRE
 338
 339 /**
 340   * @}
 341   */
 342
 343 /**
 344   * @}
 345   */
 346
 347 /* Exported macro ------------------------------------------------------------*/
 348
 349 /** @brief Reset SPI handle state
 350   * @param  __HANDLE__: specifies the SPI handle.
 351   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 352   * @retval None
 353   */
 354 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
 355
 356 /** @brief  Enable or disable the specified SPI interrupts.
 357   * @param  __HANDLE__: specifies the SPI handle.
 358   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 359   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
 360   *         This parameter can be one of the following values:
 361   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 362   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 363   *            @arg SPI_IT_ERR: Error interrupt enable
 364   * @retval None
 365   */
 366 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
 367 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
 368
 369 /** @brief  Check if the specified SPI interrupt source is enabled or disabled.
 370   * @param  __HANDLE__: specifies the SPI handle.
 371   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 372   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
 373   *          This parameter can be one of the following values:
 374   *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 375   *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 376   *             @arg SPI_IT_ERR: Error interrupt enable
 377   * @retval The new state of __IT__ (TRUE or FALSE).
 378   */
 379 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 380
 381 /** @brief  Check whether the specified SPI flag is set or not.
 382   * @param  __HANDLE__: specifies the SPI handle.
 383   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 384   * @param  __FLAG__: specifies the flag to check.
 385   *         This parameter can be one of the following values:
 386   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
 387   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
 388   *            @arg SPI_FLAG_CRCERR: CRC error flag
 389   *            @arg SPI_FLAG_MODF: Mode fault flag
 390   *            @arg SPI_FLAG_OVR: Overrun flag
 391   *            @arg SPI_FLAG_BSY: Busy flag
 392   *            @arg SPI_FLAG_FRE: Frame format error flag
 393   * @retval The new state of __FLAG__ (TRUE or FALSE).
 394   */
 395 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 396
 397 /** @brief  Clear the SPI CRCERR pending flag.
 398   * @param  __HANDLE__: specifies the SPI handle.
 399   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 400   * @retval None
 401   */
 402 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
 403
 404 /** @brief  Clear the SPI MODF pending flag.
 405   * @param  __HANDLE__: specifies the SPI handle.
 406   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 407   * @retval None
 408   */
 409 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
 410                                                 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
 411
 412 /** @brief  Clear the SPI OVR pending flag.
 413   * @param  __HANDLE__: specifies the SPI handle.
 414   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 415   * @retval None
 416   */
 417 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
 418                                                (__HANDLE__)->Instance->SR;}while(0)
 419
 420 /** @brief  Clear the SPI FRE pending flag.
 421   * @param  __HANDLE__: specifies the SPI handle.
 422   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 423   * @retval None
 424   */
 425 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
 426
 427 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
 428 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SPI_CR1_SPE)
 429
 430 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
 431
 432 #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
 433
 434 #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
 435
 436 #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
 437                                            (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
 438
 439 /* Exported functions --------------------------------------------------------*/
 440
 441 /* Initialization/de-initialization functions  **********************************/
 442 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
 443 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
 444 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
 445 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
 446
 447 /* I/O operation functions  *****************************************************/
 448 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 449 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 450 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
 451 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 452 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 453 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
 454 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 455 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 456 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
 457 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 458 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 459 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
 460
 461 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 462 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
 463 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
 464 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
 465 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
 466 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 467 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 468 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 469
 470 /* Peripheral State and Control functions  **************************************/
 471 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
 472 HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 473
 474 /**
 475   * @}
 476   */
 477
 478 /**
 479   * @}
 480   */
 481
 482 #ifdef __cplusplus
 483 }
 484 #endif
 485
 486 #endif /* __STM32F4xx_HAL_SPI_H */
 487
 488 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/