tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f4xx.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    11-January-2013
   7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8   *          This file contains the system clock configuration for STM32F4xx devices,
   9   *          and is generated by the clock configuration tool
  10   *          stm32f4xx_Clock_Configuration_V1.1.0.xls
  11   *
  12   * 1.  This file provides two functions and one global variable to be called from
  13   *     user application:
  14   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  15   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  16   *                      depending on the configuration made in the clock xls tool.
  17   *                      This function is called at startup just after reset and
  18   *                      before branch to main program. This call is made inside
  19   *                      the "startup_stm32f4xx.s" file.
  20   *
  21   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  22   *                                  by the user application to setup the SysTick
  23   *                                  timer or configure other parameters.
  24   *
  25   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  26   *                                 be called whenever the core clock is changed
  27   *                                 during program execution.
  28   *
  29   * 2. After each device reset the HSI (16 MHz) is used as system clock source.
  30   *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
  31   *    configure the system clock before to branch to main program.
  32   *
  33   * 3. If the system clock source selected by user fails to startup, the SystemInit()
  34   *    function will do nothing and HSI still used as system clock source. User can
  35   *    add some code to deal with this issue inside the SetSysClock() function.
  36   *
  37   * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
  38   *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
  39   *    through PLL, and you are using different crystal you have to adapt the HSE
  40   *    value to your own configuration.
  41   *
  42   * 5. This file configures the system clock as follows:
  43   *=============================================================================
  44   *=============================================================================
  45   *               Supported STM32F40xx/41xx/427x/437x devices
  46   *-----------------------------------------------------------------------------
  47   *        System Clock source                    | PLL (HSE)
  48   *-----------------------------------------------------------------------------
  49   *        SYSCLK(Hz)                             | 168000000
  50   *-----------------------------------------------------------------------------
  51   *        HCLK(Hz)                               | 168000000
  52   *-----------------------------------------------------------------------------
  53   *        AHB Prescaler                          | 1
  54   *-----------------------------------------------------------------------------
  55   *        APB1 Prescaler                         | 4
  56   *-----------------------------------------------------------------------------
  57   *        APB2 Prescaler                         | 2
  58   *-----------------------------------------------------------------------------
  59   *        HSE Frequency(Hz)                      | 8000000
  60   *-----------------------------------------------------------------------------
  61   *        PLL_M                                  | 8
  62   *-----------------------------------------------------------------------------
  63   *        PLL_N                                  | 336
  64   *-----------------------------------------------------------------------------
  65   *        PLL_P                                  | 2
  66   *-----------------------------------------------------------------------------
  67   *        PLL_Q                                  | 7
  68   *-----------------------------------------------------------------------------
  69   *        PLLI2S_N                               | 271
  70   *-----------------------------------------------------------------------------
  71   *        PLLI2S_R                               | 2
  72   *-----------------------------------------------------------------------------
  73   *        I2S input clock                        | NA
  74   *-----------------------------------------------------------------------------
  75   *        VDD(V)                                 | 3.3
  76   *-----------------------------------------------------------------------------
  77   *        Main regulator output voltage          | Scale1 mode
  78   *-----------------------------------------------------------------------------
  79   *        Flash Latency(WS)                      | 5
  80   *-----------------------------------------------------------------------------
  81   *        Prefetch Buffer                        | ON
  82   *-----------------------------------------------------------------------------
  83   *        Instruction cache                      | ON
  84   *-----------------------------------------------------------------------------
  85   *        Data cache                             | ON
  86   *-----------------------------------------------------------------------------
  87   *        Require 48MHz for USB OTG FS,          | Disabled
  88   *        SDIO and RNG clock                     |
  89   *-----------------------------------------------------------------------------
  90   *=============================================================================
  91   ******************************************************************************
  92   * @attention
  93   *
  94   * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
  95   *
  96   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  97   * You may not use this file except in compliance with the License.
  98   * You may obtain a copy of the License at:
  99   *
 100   *        http://www.st.com/software_license_agreement_liberty_v2
 101   *
 102   * Unless required by applicable law or agreed to in writing, software
 103   * distributed under the License is distributed on an "AS IS" BASIS,
 104   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 105   * See the License for the specific language governing permissions and
 106   * limitations under the License.
 107   *
 108   ******************************************************************************
 109   */
 110
 111 /** @addtogroup CMSIS
 112   * @{
 113   */
 114
 115 /** @addtogroup stm32f4xx_system
 116   * @{
 117   */
 118
 119 /** @addtogroup STM32F4xx_System_Private_Includes
 120   * @{
 121   */
 122
 123 #include "stm32f4xx.h"
 124
 125 /**
 126   * @}
 127   */
 128
 129 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
 130   * @{
 131   */
 132
 133 /**
 134   * @}
 135   */
 136
 137 /** @addtogroup STM32F4xx_System_Private_Defines
 138   * @{
 139   */
 140
 141 /************************* Miscellaneous Configuration ************************/
 142 /*!< Uncomment the following line if you need to use external SRAM mounted
 143      on STM324xG_EVAL/STM324x7I_EVAL boards as data memory  */
 144 /* #define DATA_IN_ExtSRAM */
 145
 146 /*!< Uncomment the following line if you need to relocate your vector Table in
 147      Internal SRAM. */
 148 /* #define VECT_TAB_SRAM */
 149 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
 150                                    This value must be a multiple of 0x200. */
 151 /******************************************************************************/
 152
 153 /************************* PLL Parameters *************************************/
 154 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
 155 #define PLL_M      8
 156 #define PLL_N      336
 157
 158 /* SYSCLK = PLL_VCO / PLL_P */
 159 #define PLL_P      2
 160
 161 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
 162 #define PLL_Q      7
 163
 164 #define PLLI2S_N  271
 165 #define PLLI2S_R  2
 166
 167 /******************************************************************************/
 168
 169 /**
 170   * @}
 171   */
 172
 173 /** @addtogroup STM32F4xx_System_Private_Macros
 174   * @{
 175   */
 176
 177 /**
 178   * @}
 179   */
 180
 181 /** @addtogroup STM32F4xx_System_Private_Variables
 182   * @{
 183   */
 184
 185   uint32_t SystemCoreClock = 168000000;
 186
 187 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 188
 189 /**
 190   * @}
 191   */
 192
 193 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
 194   * @{
 195   */
 196
 197 static void SetSysClock(void);
 198 #ifdef DATA_IN_ExtSRAM
 199   static void SystemInit_ExtMemCtl(void);
 200 #endif /* DATA_IN_ExtSRAM */
 201
 202 /**
 203   * @}
 204   */
 205
 206 /** @addtogroup STM32F4xx_System_Private_Functions
 207   * @{
 208   */
 209
 210 /**
 211   * @brief  Setup the microcontroller system
 212   *         Initialize the Embedded Flash Interface, the PLL and update the
 213   *         SystemFrequency variable.
 214   * @param  None
 215   * @retval None
 216   */
 217 void SystemInit(void)
 218 {
 219   /* FPU settings ------------------------------------------------------------*/
 220   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 221     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 222   #endif
 223   /* Reset the RCC clock configuration to the default reset state ------------*/
 224   /* Set HSION bit */
 225   RCC->CR |= (uint32_t)0x00000001;
 226
 227   /* Reset CFGR register */
 228   RCC->CFGR = 0x00000000;
 229
 230   /* Reset HSEON, CSSON and PLLON bits */
 231   RCC->CR &= (uint32_t)0xFEF6FFFF;
 232
 233   /* Reset PLLCFGR register */
 234   RCC->PLLCFGR = 0x24003010;
 235
 236   /* Reset HSEBYP bit */
 237   RCC->CR &= (uint32_t)0xFFFBFFFF;
 238
 239   /* Disable all interrupts */
 240   RCC->CIR = 0x00000000;
 241
 242 #ifdef DATA_IN_ExtSRAM
 243   SystemInit_ExtMemCtl();
 244 #endif /* DATA_IN_ExtSRAM */
 245
 246   /* Configure the System clock source, PLL Multiplier and Divider factors,
 247      AHB/APBx prescalers and Flash settings ----------------------------------*/
 248   SetSysClock();
 249
 250   /* Configure the Vector Table location add offset address ------------------*/
 251 #ifdef VECT_TAB_SRAM
 252   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 253 #else
 254   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 255 #endif
 256 }
 257
 258 /**
 259    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 260   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 261   *         be used by the user application to setup the SysTick timer or configure
 262   *         other parameters.
 263   *
 264   * @note   Each time the core clock (HCLK) changes, this function must be called
 265   *         to update SystemCoreClock variable value. Otherwise, any configuration
 266   *         based on this variable will be incorrect.
 267   *
 268   * @note   - The system frequency computed by this function is not the real
 269   *           frequency in the chip. It is calculated based on the predefined
 270   *           constant and the selected clock source:
 271   *
 272   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 273   *
 274   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 275   *
 276   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 277   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 278   *
 279   *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
 280   *             16 MHz) but the real value may vary depending on the variations
 281   *             in voltage and temperature.
 282   *
 283   *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
 284   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
 285   *              frequency of the crystal used. Otherwise, this function may
 286   *              have wrong result.
 287   *
 288   *         - The result of this function could be not correct when using fractional
 289   *           value for HSE crystal.
 290   *
 291   * @param  None
 292   * @retval None
 293   */
 294 void SystemCoreClockUpdate(void)
 295 {
 296   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 297
 298   /* Get SYSCLK source -------------------------------------------------------*/
 299   tmp = RCC->CFGR & RCC_CFGR_SWS;
 300
 301   switch (tmp)
 302   {
 303     case 0x00:  /* HSI used as system clock source */
 304       SystemCoreClock = HSI_VALUE;
 305       break;
 306     case 0x04:  /* HSE used as system clock source */
 307       SystemCoreClock = HSE_VALUE;
 308       break;
 309     case 0x08:  /* PLL used as system clock source */
 310
 311       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 312          SYSCLK = PLL_VCO / PLL_P
 313          */
 314       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 315       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 316
 317       if (pllsource != 0)
 318       {
 319         /* HSE used as PLL clock source */
 320         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 321       }
 322       else
 323       {
 324         /* HSI used as PLL clock source */
 325         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 326       }
 327
 328       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 329       SystemCoreClock = pllvco/pllp;
 330       break;
 331     default:
 332       SystemCoreClock = HSI_VALUE;
 333       break;
 334   }
 335   /* Compute HCLK frequency --------------------------------------------------*/
 336   /* Get HCLK prescaler */
 337   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 338   /* HCLK frequency */
 339   SystemCoreClock >>= tmp;
 340 }
 341
 342 /**
 343   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 344   *         AHB/APBx prescalers and Flash settings
 345   * @Note   This function should be called only once the RCC clock configuration
 346   *         is reset to the default reset state (done in SystemInit() function).
 347   * @param  None
 348   * @retval None
 349   */
 350 static void SetSysClock(void)
 351 {
 352 /******************************************************************************/
 353 /*            PLL (clocked by HSE) used as System clock source                */
 354 /******************************************************************************/
 355   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 356
 357   /* Enable HSE */
 358   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 359
 360   /* Wait till HSE is ready and if Time out is reached exit */
 361   do
 362   {
 363     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 364     StartUpCounter++;
 365   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 366
 367   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 368   {
 369     HSEStatus = (uint32_t)0x01;
 370   }
 371   else
 372   {
 373     HSEStatus = (uint32_t)0x00;
 374   }
 375
 376   if (HSEStatus == (uint32_t)0x01)
 377   {
 378     /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
 379     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 380     PWR->CR |= PWR_CR_VOS;
 381
 382     /* HCLK = SYSCLK / 1*/
 383     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
 384
 385     /* PCLK2 = HCLK / 2*/
 386     RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
 387
 388     /* PCLK1 = HCLK / 4*/
 389     RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
 390
 391     /* Configure the main PLL */
 392     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
 393                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
 394
 395     /* Enable the main PLL */
 396     RCC->CR |= RCC_CR_PLLON;
 397
 398     /* Wait till the main PLL is ready */
 399     while((RCC->CR & RCC_CR_PLLRDY) == 0)
 400     {
 401     }
 402
 403     /* Configure the I2S PLL */
 404     RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
 405
 406     /* Enable the I2S PLL */
 407     RCC->CR |= RCC_CR_PLLI2SON;
 408
 409     /* Wait until the I2S PLL is ready */
 410     while (!(RCC->CR & RCC_CR_PLLI2SRDY));
 411
 412     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 413     FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
 414
 415     /* Select the main PLL as system clock source */
 416     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 417     RCC->CFGR |= RCC_CFGR_SW_PLL;
 418
 419     /* Wait till the main PLL is used as system clock source */
 420     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
 421     {
 422     }
 423   }
 424   else
 425   { /* If HSE fails to start-up, the application will have wrong clock
 426          configuration. User can add here some code to deal with this error */
 427   }
 428
 429 }
 430
 431 /**
 432   * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s
 433   *          before jump to __main
 434   * @param  None
 435   * @retval None
 436   */
 437 #ifdef DATA_IN_ExtSRAM
 438 /**
 439   * @brief  Setup the external memory controller.
 440   *         Called in startup_stm32f4xx.s before jump to main.
 441   *         This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
 442   *         This SRAM will be used as program data memory (including heap and stack).
 443   * @param  None
 444   * @retval None
 445   */
 446 void SystemInit_ExtMemCtl(void)
 447 {
 448 /*-- GPIOs Configuration -----------------------------------------------------*/
 449 /*
 450  +-------------------+--------------------+------------------+------------------+
 451  +                       SRAM pins assignment                                   +
 452  +-------------------+--------------------+------------------+------------------+
 453  | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0 <-> FSMC_A0  | PG0 <-> FSMC_A10 |
 454  | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1 <-> FSMC_A1  | PG1 <-> FSMC_A11 |
 455  | PD4  <-> FSMC_NOE | PE2  <-> FSMC_A23  | PF2 <-> FSMC_A2  | PG2 <-> FSMC_A12 |
 456  | PD5  <-> FSMC_NWE | PE3  <-> FSMC_A19  | PF3 <-> FSMC_A3  | PG3 <-> FSMC_A13 |
 457  | PD8  <-> FSMC_D13 | PE4  <-> FSMC_A20  | PF4 <-> FSMC_A4  | PG4 <-> FSMC_A14 |
 458  | PD9  <-> FSMC_D14 | PE5  <-> FSMC_A21  | PF5 <-> FSMC_A5  | PG5 <-> FSMC_A15 |
 459  | PD10 <-> FSMC_D15 | PE6  <-> FSMC_A22  | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
 460  | PD11 <-> FSMC_A16 | PE7  <-> FSMC_D4   | PF13 <-> FSMC_A7 |------------------+
 461  | PD12 <-> FSMC_A17 | PE8  <-> FSMC_D5   | PF14 <-> FSMC_A8 |
 462  | PD13 <-> FSMC_A18 | PE9  <-> FSMC_D6   | PF15 <-> FSMC_A9 |
 463  | PD14 <-> FSMC_D0  | PE10 <-> FSMC_D7   |------------------+
 464  | PD15 <-> FSMC_D1  | PE11 <-> FSMC_D8   |
 465  +-------------------| PE12 <-> FSMC_D9   |
 466                      | PE13 <-> FSMC_D10  |
 467                      | PE14 <-> FSMC_D11  |
 468                      | PE15 <-> FSMC_D12  |
 469                      +--------------------+
 470 */
 471    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
 472   RCC->AHB1ENR   |= 0x00000078;
 473
 474   /* Connect PDx pins to FSMC Alternate function */
 475   GPIOD->AFR[0]  = 0x00cc00cc;
 476   GPIOD->AFR[1]  = 0xcccccccc;
 477   /* Configure PDx pins in Alternate function mode */
 478   GPIOD->MODER   = 0xaaaa0a0a;
 479   /* Configure PDx pins speed to 100 MHz */
 480   GPIOD->OSPEEDR = 0xffff0f0f;
 481   /* Configure PDx pins Output type to push-pull */
 482   GPIOD->OTYPER  = 0x00000000;
 483   /* No pull-up, pull-down for PDx pins */
 484   GPIOD->PUPDR   = 0x00000000;
 485
 486   /* Connect PEx pins to FSMC Alternate function */
 487   GPIOE->AFR[0]  = 0xcccccccc;
 488   GPIOE->AFR[1]  = 0xcccccccc;
 489   /* Configure PEx pins in Alternate function mode */
 490   GPIOE->MODER   = 0xaaaaaaaa;
 491   /* Configure PEx pins speed to 100 MHz */
 492   GPIOE->OSPEEDR = 0xffffffff;
 493   /* Configure PEx pins Output type to push-pull */
 494   GPIOE->OTYPER  = 0x00000000;
 495   /* No pull-up, pull-down for PEx pins */
 496   GPIOE->PUPDR   = 0x00000000;
 497
 498   /* Connect PFx pins to FSMC Alternate function */
 499   GPIOF->AFR[0]  = 0x00cccccc;
 500   GPIOF->AFR[1]  = 0xcccc0000;
 501   /* Configure PFx pins in Alternate function mode */
 502   GPIOF->MODER   = 0xaa000aaa;
 503   /* Configure PFx pins speed to 100 MHz */
 504   GPIOF->OSPEEDR = 0xff000fff;
 505   /* Configure PFx pins Output type to push-pull */
 506   GPIOF->OTYPER  = 0x00000000;
 507   /* No pull-up, pull-down for PFx pins */
 508   GPIOF->PUPDR   = 0x00000000;
 509
 510   /* Connect PGx pins to FSMC Alternate function */
 511   GPIOG->AFR[0]  = 0x00cccccc;
 512   GPIOG->AFR[1]  = 0x000000c0;
 513   /* Configure PGx pins in Alternate function mode */
 514   GPIOG->MODER   = 0x00080aaa;
 515   /* Configure PGx pins speed to 100 MHz */
 516   GPIOG->OSPEEDR = 0x000c0fff;
 517   /* Configure PGx pins Output type to push-pull */
 518   GPIOG->OTYPER  = 0x00000000;
 519   /* No pull-up, pull-down for PGx pins */
 520   GPIOG->PUPDR   = 0x00000000;
 521
 522 /*-- FSMC Configuration ------------------------------------------------------*/
 523   /* Enable the FSMC interface clock */
 524   RCC->AHB3ENR         |= 0x00000001;
 525
 526   /* Configure and enable Bank1_SRAM2 */
 527   FSMC_Bank1->BTCR[2]  = 0x00001011;
 528   FSMC_Bank1->BTCR[3]  = 0x00000201;
 529   FSMC_Bank1E->BWTR[2] = 0x0fffffff;
 530 /*
 531   Bank1_SRAM2 is configured as follow:
 532
 533   p.FSMC_AddressSetupTime = 1;
 534   p.FSMC_AddressHoldTime = 0;
 535   p.FSMC_DataSetupTime = 2;
 536   p.FSMC_BusTurnAroundDuration = 0;
 537   p.FSMC_CLKDivision = 0;
 538   p.FSMC_DataLatency = 0;
 539   p.FSMC_AccessMode = FSMC_AccessMode_A;
 540
 541   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
 542   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
 543   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
 544   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
 545   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
 546   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
 547   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
 548   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
 549   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
 550   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
 551   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
 552   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
 553   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
 554   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
 555   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
 556 */
 557 }
 558 #endif /* DATA_IN_ExtSRAM */
 559
 560
 561 /**
 562   * @}
 563   */
 564
 565 /**
 566   * @}
 567   */
 568
 569 /**
 570   * @}
 571   */
 572 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 573