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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32L0 / TARGET_DISCO_L053C8 / stm32l053xx.h
1 /**
2 ******************************************************************************
3 * @file stm32l053xx.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 06-February-2015
7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for stm32l053xx devices.
10 *
11 * This file contains:
12 * - Data structures and the address mapping for all peripherals
13 * - Peripheral's registers declarations and bits definition
14 * - Macros to access peripheral's registers hardware
15 *
16 ******************************************************************************
17 * @attention
18 *
19 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
20 *
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ******************************************************************************
44 */
45
46 /** @addtogroup CMSIS
47 * @{
48 */
49
50 /** @addtogroup stm32l053xx
51 * @{
52 */
53
54 #ifndef __STM32L053xx_H
55 #define __STM32L053xx_H
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61
62 /** @addtogroup Configuration_section_for_CMSIS
63 * @{
64 */
65 /**
66 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
67 */
68 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
69 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
70 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
71 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
72 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
73
74 /**
75 * @}
76 */
77
78 /** @addtogroup Peripheral_interrupt_number_definition
79 * @{
80 */
81
82 /**
83 * @brief stm32l053xx Interrupt Number Definition, according to the selected device
84 * in @ref Library_configuration_section
85 */
86
87 /*!< Interrupt Number Definition */
88 typedef enum
89 {
90 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
91 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
92 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
93 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
94 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
95 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
96
97 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
99 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
100 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
101 FLASH_IRQn = 3, /*!< FLASH Interrupt */
102 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
103 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
104 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
105 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
106 TSC_IRQn = 8, /*!< TSC Interrupt */
107 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
108 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
109 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
110 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
111 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
112 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
113 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
114 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
115 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
116 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
117 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
118 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
119 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
120 USART1_IRQn = 27, /*!< USART1 Interrupt */
121 USART2_IRQn = 28, /*!< USART2 Interrupt */
122 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
123 LCD_IRQn = 30, /*!< LCD Interrupt */
124 USB_IRQn = 31, /*!< USB global Interrupt */
125 } IRQn_Type;
126
127 /**
128 * @}
129 */
130
131 #include "core_cm0plus.h"
132 #include "system_stm32l0xx.h"
133 #include <stdint.h>
134
135 /** @addtogroup Peripheral_registers_structures
136 * @{
137 */
138
139 /**
140 * @brief Analog to Digital Converter
141 */
142
143 typedef struct
144 {
145 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
146 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
147 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
148 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
149 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
150 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
151 uint32_t RESERVED1; /*!< Reserved, 0x18 */
152 uint32_t RESERVED2; /*!< Reserved, 0x1C */
153 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
154 uint32_t RESERVED3; /*!< Reserved, 0x24 */
155 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
156 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
157 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
158 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
159 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
160 } ADC_TypeDef;
161
162 typedef struct
163 {
164 __IO uint32_t CCR;
165 } ADC_Common_TypeDef;
166
167
168 /**
169 * @brief Comparator
170 */
171
172 typedef struct
173 {
174 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
175 } COMP_TypeDef;
176
177
178 /**
179 * @brief CRC calculation unit
180 */
181
182 typedef struct
183 {
184 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
185 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
186 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
187 uint32_t RESERVED2; /*!< Reserved, 0x0C */
188 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
189 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
190 } CRC_TypeDef;
191
192 /**
193 * @brief Clock Recovery System
194 */
195
196 typedef struct
197 {
198 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
199 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
200 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
201 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
202 } CRS_TypeDef;
203
204 /**
205 * @brief Digital to Analog Converter
206 */
207
208 typedef struct
209 {
210 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
211 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
212 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
213 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
214 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
215 uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
216 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
217 uint32_t RESERVED1; /*!< 0x30 */
218 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
219 } DAC_TypeDef;
220
221 /**
222 * @brief Debug MCU
223 */
224
225 typedef struct
226 {
227 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
228 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
229 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
230 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
231 }DBGMCU_TypeDef;
232
233 /**
234 * @brief DMA Controller
235 */
236
237 typedef struct
238 {
239 __IO uint32_t CCR; /*!< DMA channel x configuration register */
240 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
241 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
242 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
243 } DMA_Channel_TypeDef;
244
245 typedef struct
246 {
247 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
248 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
249 } DMA_TypeDef;
250
251 typedef struct
252 {
253 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
254 } DMA_Request_TypeDef;
255
256 /**
257 * @brief External Interrupt/Event Controller
258 */
259
260 typedef struct
261 {
262 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
263 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
264 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
265 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
266 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
267 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
268 }EXTI_TypeDef;
269
270 /**
271 * @brief FLASH Registers
272 */
273 typedef struct
274 {
275 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
276 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
277 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
278 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
279 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
280 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
281 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
282 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
283 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
284 } FLASH_TypeDef;
285
286
287 /**
288 * @brief Option Bytes Registers
289 */
290 typedef struct
291 {
292 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
293 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
294 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
295 } OB_TypeDef;
296
297
298 /**
299 * @brief General Purpose IO
300 */
301
302 typedef struct
303 {
304 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
305 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
306 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
307 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
308 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
309 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
310 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
311 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
312 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
313 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
314 }GPIO_TypeDef;
315
316 /**
317 * @brief LPTIMIMER
318 */
319 typedef struct
320 {
321 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
322 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
323 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
324 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
325 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
326 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
327 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
328 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
329 } LPTIM_TypeDef;
330
331 /**
332 * @brief SysTem Configuration
333 */
334
335 typedef struct
336 {
337 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
338 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
339 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
340 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
341 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
342 } SYSCFG_TypeDef;
343
344
345
346 /**
347 * @brief Inter-integrated Circuit Interface
348 */
349
350 typedef struct
351 {
352 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
353 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
354 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
355 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
356 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
357 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
358 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
359 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
360 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
361 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
362 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
363 }I2C_TypeDef;
364
365
366 /**
367 * @brief Independent WATCHDOG
368 */
369 typedef struct
370 {
371 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
372 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
373 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
374 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
375 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
376 } IWDG_TypeDef;
377
378 /**
379 * @brief LCD
380 */
381
382 typedef struct
383 {
384 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
385 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
386 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
387 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
388 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
389 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
390 } LCD_TypeDef;
391
392 /**
393 * @brief MIFARE Firewall
394 */
395
396 typedef struct
397 {
398 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
399 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
400 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
401 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
402 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
403 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
404 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
405 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
406 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
407
408 } FW_TypeDef;
409
410 /**
411 * @brief Power Control
412 */
413
414 typedef struct
415 {
416 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
417 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
418 } PWR_TypeDef;
419
420 /**
421 * @brief Reset and Clock Control
422 */
423 typedef struct
424 {
425 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
426 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
427 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
428 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
429 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
430 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
431 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
432 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
433 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
434 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
435 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
436 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
437 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
438 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
439 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
440 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
441 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
442 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
443 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
444 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
445 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
446 } RCC_TypeDef;
447
448 /**
449 * @brief Random numbers generator
450 */
451 typedef struct
452 {
453 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
454 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
455 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
456 } RNG_TypeDef;
457
458 /**
459 * @brief Real-Time Clock
460 */
461 typedef struct
462 {
463 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
464 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
465 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
466 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
467 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
468 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
469 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
470 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
471 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
472 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
473 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
474 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
475 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
476 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
477 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
478 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
479 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
480 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
481 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
482 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
483 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
484 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
485 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
486 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
487 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
488 } RTC_TypeDef;
489
490
491 /**
492 * @brief Serial Peripheral Interface
493 */
494
495 typedef struct
496 {
497 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
498 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
499 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
500 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
501 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
502 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
503 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
504 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
505 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
506 } SPI_TypeDef;
507
508 /**
509 * @brief TIM
510 */
511 typedef struct
512 {
513 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
514 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
515 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
516 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
517 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
518 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
519 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
520 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
521 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
522 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
523 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
524 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
525 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
526 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
527 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
528 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
529 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
530 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
531 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
532 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
533 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
534 } TIM_TypeDef;
535
536 /**
537 * @brief Touch Sensing Controller (TSC)
538 */
539 typedef struct
540 {
541 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
542 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
543 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
544 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
545 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
546 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
547 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
548 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
549 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
550 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
551 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
552 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
553 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
554 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
555 } TSC_TypeDef;
556
557 /**
558 * @brief Universal Synchronous Asynchronous Receiver Transmitter
559 */
560
561 typedef struct
562 {
563 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
564 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
565 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
566 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
567 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
568 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
569 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
570 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
571 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
572 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
573 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
574 } USART_TypeDef;
575
576 /**
577 * @brief Window WATCHDOG
578 */
579 typedef struct
580 {
581 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
582 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
583 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
584 } WWDG_TypeDef;
585
586 /**
587 * @brief Universal Serial Bus Full Speed Device
588 */
589
590 typedef struct
591 {
592 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
593 __IO uint16_t RESERVED0; /*!< Reserved */
594 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
595 __IO uint16_t RESERVED1; /*!< Reserved */
596 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
597 __IO uint16_t RESERVED2; /*!< Reserved */
598 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
599 __IO uint16_t RESERVED3; /*!< Reserved */
600 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
601 __IO uint16_t RESERVED4; /*!< Reserved */
602 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
603 __IO uint16_t RESERVED5; /*!< Reserved */
604 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
605 __IO uint16_t RESERVED6; /*!< Reserved */
606 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
607 __IO uint16_t RESERVED7[17]; /*!< Reserved */
608 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
609 __IO uint16_t RESERVED8; /*!< Reserved */
610 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
611 __IO uint16_t RESERVED9; /*!< Reserved */
612 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
613 __IO uint16_t RESERVEDA; /*!< Reserved */
614 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
615 __IO uint16_t RESERVEDB; /*!< Reserved */
616 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
617 __IO uint16_t RESERVEDC; /*!< Reserved */
618 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
619 __IO uint16_t RESERVEDD; /*!< Reserved */
620 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
621 __IO uint16_t RESERVEDE; /*!< Reserved */
622 } USB_TypeDef;
623
624 /**
625 * @}
626 */
627
628 /** @addtogroup Peripheral_memory_map
629 * @{
630 */
631
632 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
633 #define FLASH_END ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */
634 #define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
635 #define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!< DATA EEPROM end address in the alias region */
636 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
637 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
638
639 /*!< Peripheral memory map */
640 #define APBPERIPH_BASE PERIPH_BASE
641 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
642 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000)
643
644 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
645 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
646 #define LCD_BASE (APBPERIPH_BASE + 0x00002400)
647 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
648 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
649 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
650 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
651 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
652 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800)
653 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
654 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
655 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
656 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
657 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
658 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00)
659
660 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
661 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
662 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
663 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
664 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
665 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
666 #define FW_BASE (APBPERIPH_BASE + 0x00011C00)
667 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
668 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
669 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
670 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
671 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
672
673 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
674 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
675 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
676 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
677 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
678 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
679 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
680 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
681 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8)
682
683
684 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
685 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
686 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
687 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
688 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
689 #define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
690
691 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000)
692 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400)
693 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800)
694 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00)
695 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00)
696
697 /**
698 * @}
699 */
700
701 /** @addtogroup Peripheral_declaration
702 * @{
703 */
704
705 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
706 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
707 #define RTC ((RTC_TypeDef *) RTC_BASE)
708 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
709 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
710 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
711 #define USART2 ((USART_TypeDef *) USART2_BASE)
712 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
713 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
714 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
715 #define CRS ((CRS_TypeDef *) CRS_BASE)
716 #define PWR ((PWR_TypeDef *) PWR_BASE)
717 #define DAC ((DAC_TypeDef *) DAC_BASE)
718 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
719 #define LCD ((LCD_TypeDef *) LCD_BASE)
720
721 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
722 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
723 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
724 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
725 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
726 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
727 #define FW ((FW_TypeDef *) FW_BASE)
728 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
729 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
730 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
731 #define USART1 ((USART_TypeDef *) USART1_BASE)
732 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
733
734 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
735 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
736 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
737 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
738 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
739 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
740 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
741 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
742 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
743
744
745 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
746 #define OB ((OB_TypeDef *) OB_BASE)
747 #define RCC ((RCC_TypeDef *) RCC_BASE)
748 #define CRC ((CRC_TypeDef *) CRC_BASE)
749 #define TSC ((TSC_TypeDef *) TSC_BASE)
750 #define RNG ((RNG_TypeDef *) RNG_BASE)
751
752 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
753 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
754 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
755 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
756 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
757
758 #define USB ((USB_TypeDef *) USB_BASE)
759
760 /**
761 * @}
762 */
763
764 /** @addtogroup Exported_constants
765 * @{
766 */
767
768 /** @addtogroup Peripheral_Registers_Bits_Definition
769 * @{
770 */
771
772 /******************************************************************************/
773 /* Peripheral Registers Bits Definition */
774 /******************************************************************************/
775 /******************************************************************************/
776 /* */
777 /* Analog to Digital Converter (ADC) */
778 /* */
779 /******************************************************************************/
780 /******************** Bits definition for ADC_ISR register ******************/
781 #define ADC_ISR_EOCAL ((uint32_t)0x00000800) /*!< End of calibration flag */
782 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
783 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
784 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
785 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
786 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
787 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
788
789 /* Old EOSEQ bit definition, maintained for legacy purpose */
790 #define ADC_ISR_EOS ADC_ISR_EOSEQ
791
792 /******************** Bits definition for ADC_IER register ******************/
793 #define ADC_IER_EOCALIE ((uint32_t)0x00000800) /*!< Enf Of Calibration interrupt enable */
794 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
795 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
796 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
797 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
798 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
799 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
800
801 /* Old EOSEQIE bit definition, maintained for legacy purpose */
802 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
803
804 /******************** Bits definition for ADC_CR register *******************/
805 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
806 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage Regulator Enable */
807 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
808 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
809 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
810 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ /*#### TBV */
811
812 /******************* Bits definition for ADC_CFGR1 register *****************/
813 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
814 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
815 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
816 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
817 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
818 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
819 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
820 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
821 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
822 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
823 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
824 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
825 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
826 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
827 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
828 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
829 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
830 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
831 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
832 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
833 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
834 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
835 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
836 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
837 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
838 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
839 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
840
841 /* Old WAIT bit definition, maintained for legacy purpose */
842 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
843
844 /******************* Bits definition for ADC_CFGR2 register *****************/
845 #define ADC_CFGR2_TOVS ((uint32_t)0x80000200) /*!< Triggered Oversampling */
846 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< OVSS [3:0] bits (Oversampling shift) */
847 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
848 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
849 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
850 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< Bit 3 */
851 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< OVSR [2:0] bits (Oversampling ratio) */
852 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< Bit 0 */
853 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< Bit 1 */
854 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< Bit 2 */
855 #define ADC_CFGR2_OVSE ((uint32_t)0x00000001) /*!< Oversampler Enable */
856 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< CKMODE [1:0] bits (ADC clock mode) */
857 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< Bit 0 */
858 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< Bit 1 */
859
860
861 /****************** Bit definition for ADC_SMPR register ********************/
862 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMPR[2:0] bits (Sampling time selection) */
863 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
864 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
865 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
866
867 /* Bit names aliases maintained for legacy */
868 #define ADC_SMPR_SMPR ADC_SMPR_SMP
869 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
870 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
871 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
872
873 /******************* Bit definition for ADC_TR register ********************/
874 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
875 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
876
877 /****************** Bit definition for ADC_CHSELR register ******************/
878 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
879 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
880 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
881 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
882 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
883 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
884 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
885 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
886 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
887 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
888 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
889 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
890 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
891 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
892 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
893 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
894 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
895 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
896 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
897
898 /******************** Bit definition for ADC_DR register ********************/
899 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
900
901 /******************** Bit definition for ADC_CALFACT register ********************/
902 #define ADC_CALFACT_CALFACT ((uint32_t)0x0000007F) /*!< Calibration factor */
903
904 /******************* Bit definition for ADC_CCR register ********************/
905 #define ADC_CCR_LFMEN ((uint32_t)0x02000000) /*!< Low Frequency Mode enable */
906 #define ADC_CCR_VLCDEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
907 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensore enable */
908 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
909 #define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< PRESC [3:0] bits (ADC prescaler) */
910 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
911 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
912 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
913 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
914
915 /******************************************************************************/
916 /* */
917 /* Analog Comparators (COMP) */
918 /* */
919 /******************************************************************************/
920 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
921 /* COMP1 bits definition */
922 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
923 #define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
924 #define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
925 #define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
926 #define COMP_CSR_COMP1WM ((uint32_t)0x00000100) /*!< Comparators window mode enable */
927 #define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
928 #define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000) /*!< COMP1 output polarity */
929 #define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000) /*!< COMP1 output level */
930 #define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
931 /* COMP2 bits definition */
932 #define COMP_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
933 #define COMP_CSR_COMP2SPEED ((uint32_t)0x000C0008) /*!< COMP2 power mode */
934 #define COMP_CSR_COMP2INNSEL ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
935 #define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
936 #define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
937 #define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
938 #define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
939 #define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
940 #define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
941 #define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
942 #define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
943 #define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000) /*!< COMP2 output polarity */
944 #define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000) /*!< COMP2 output level */
945 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
946
947 /********************** Bit definition for COMP_CSR register common ****************/
948 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
949 #define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000) /*!< COMPx output polarity */
950 #define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000) /*!< COMPx output level */
951 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
952
953
954 /******************************************************************************/
955 /* */
956 /* CRC calculation unit (CRC) */
957 /* */
958 /******************************************************************************/
959 /******************* Bit definition for CRC_DR register *********************/
960 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
961
962 /******************* Bit definition for CRC_IDR register ********************/
963 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
964
965 /******************** Bit definition for CRC_CR register ********************/
966 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
967 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
968 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
969 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
970 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
971 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
972 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
973 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
974
975 /******************* Bit definition for CRC_INIT register *******************/
976 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
977
978 /******************* Bit definition for CRC_POL register ********************/
979 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
980
981 /******************************************************************************/
982 /* */
983 /* CRS Clock Recovery System */
984 /* */
985 /******************************************************************************/
986
987 /******************* Bit definition for CRS_CR register *********************/
988 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
989 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
990 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
991 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
992 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
993 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
994 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
995 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
996
997 /******************* Bit definition for CRS_CFGR register *********************/
998 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
999 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
1000
1001 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
1002 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
1003 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
1004 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
1005
1006 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
1007 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
1008 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
1009
1010 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
1011
1012 /******************* Bit definition for CRS_ISR register *********************/
1013 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
1014 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
1015 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
1016 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
1017 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
1018 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
1019 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
1020 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
1021 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
1022
1023 /******************* Bit definition for CRS_ICR register *********************/
1024 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
1025 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
1026 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
1027 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
1028
1029 /******************************************************************************/
1030 /* */
1031 /* Digital to Analog Converter (DAC) */
1032 /* */
1033 /******************************************************************************/
1034 /******************** Bit definition for DAC_CR register ********************/
1035 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
1036 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
1037 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
1038
1039 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1040 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
1041 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
1042 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
1043
1044 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1045 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1046 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1047
1048 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1049 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1050 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1051 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
1052 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
1053
1054 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
1055 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun interrupt enable */
1056
1057 /***************** Bit definition for DAC_SWTRIGR register ******************/
1058 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
1059
1060 /***************** Bit definition for DAC_DHR12R1 register ******************/
1061 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
1062
1063 /***************** Bit definition for DAC_DHR12L1 register ******************/
1064 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
1065
1066 /****************** Bit definition for DAC_DHR8R1 register ******************/
1067 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
1068
1069 /******************* Bit definition for DAC_DOR1 register *******************/
1070 #define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFF) /*!< DAC channel1 data output */
1071
1072 /******************** Bit definition for DAC_SR register ********************/
1073 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
1074
1075 /******************************************************************************/
1076 /* */
1077 /* Debug MCU (DBGMCU) */
1078 /* */
1079 /******************************************************************************/
1080
1081 /**************** Bit definition for DBGMCU_IDCODE register *****************/
1082 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
1083
1084 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
1085 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1086 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1087 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
1088 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
1089 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
1090 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
1091 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
1092 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
1093 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
1094 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
1095 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
1096 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
1097 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
1098 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
1099 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
1100 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
1101
1102 /****************** Bit definition for DBGMCU_CR register *******************/
1103 #define DBGMCU_CR_DBG ((uint32_t)0x00000007) /*!< Debug mode mask */
1104 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
1105 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
1106 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
1107
1108 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
1109 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
1110 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
1111 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
1112 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
1113 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
1114 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1115 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
1116 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000) /*!< LPTIM1 counter stopped when core is halted */
1117 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
1118 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020) /*!< TIM22 counter stopped when core is halted */
1119 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004) /*!< TIM21 counter stopped when core is halted */
1120
1121 /******************************************************************************/
1122 /* */
1123 /* DMA Controller (DMA) */
1124 /* */
1125 /******************************************************************************/
1126
1127 /******************* Bit definition for DMA_ISR register ********************/
1128 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
1129 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
1130 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
1131 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
1132 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
1133 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
1134 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
1135 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
1136 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
1137 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
1138 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
1139 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
1140 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
1141 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
1142 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
1143 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
1144 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
1145 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
1146 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
1147 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
1148 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
1149 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
1150 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
1151 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
1152 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
1153 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
1154 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
1155 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
1156
1157 /******************* Bit definition for DMA_IFCR register *******************/
1158 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
1159 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
1160 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
1161 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
1162 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
1163 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
1164 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
1165 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
1166 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
1167 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
1168 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
1169 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
1170 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
1171 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
1172 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
1173 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
1174 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
1175 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
1176 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
1177 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
1178 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
1179 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
1180 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
1181 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
1182 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
1183 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
1184 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
1185 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
1186
1187 /******************* Bit definition for DMA_CCR register ********************/
1188 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
1189 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
1190 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
1191 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
1192 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
1193 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
1194 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
1195 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
1196
1197 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
1198 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1199 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1200
1201 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
1202 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1203 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1204
1205 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
1206 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1207 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1208
1209 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
1210
1211 /****************** Bit definition for DMA_CNDTR register *******************/
1212 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1213
1214 /****************** Bit definition for DMA_CPAR register ********************/
1215 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1216
1217 /****************** Bit definition for DMA_CMAR register ********************/
1218 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1219
1220
1221 /******************* Bit definition for DMA_CSELR register *******************/
1222 #define DMA_CSELR_C1S ((uint32_t)0x0000000F) /*!< Channel 1 Selection */
1223 #define DMA_CSELR_C2S ((uint32_t)0x000000F0) /*!< Channel 2 Selection */
1224 #define DMA_CSELR_C3S ((uint32_t)0x00000F00) /*!< Channel 3 Selection */
1225 #define DMA_CSELR_C4S ((uint32_t)0x0000F000) /*!< Channel 4 Selection */
1226 #define DMA_CSELR_C5S ((uint32_t)0x000F0000) /*!< Channel 5 Selection */
1227 #define DMA_CSELR_C6S ((uint32_t)0x00F00000) /*!< Channel 6 Selection */
1228 #define DMA_CSELR_C7S ((uint32_t)0x0F000000) /*!< Channel 7 Selection */
1229
1230
1231 /******************************************************************************/
1232 /* */
1233 /* External Interrupt/Event Controller (EXTI) */
1234 /* */
1235 /******************************************************************************/
1236
1237 /******************* Bit definition for EXTI_IMR register *******************/
1238 #define EXTI_IMR_IM0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
1239 #define EXTI_IMR_IM1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
1240 #define EXTI_IMR_IM2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
1241 #define EXTI_IMR_IM3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
1242 #define EXTI_IMR_IM4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
1243 #define EXTI_IMR_IM5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
1244 #define EXTI_IMR_IM6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
1245 #define EXTI_IMR_IM7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
1246 #define EXTI_IMR_IM8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
1247 #define EXTI_IMR_IM9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
1248 #define EXTI_IMR_IM10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
1249 #define EXTI_IMR_IM11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
1250 #define EXTI_IMR_IM12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
1251 #define EXTI_IMR_IM13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
1252 #define EXTI_IMR_IM14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
1253 #define EXTI_IMR_IM15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
1254 #define EXTI_IMR_IM16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
1255 #define EXTI_IMR_IM17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
1256 #define EXTI_IMR_IM18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
1257 #define EXTI_IMR_IM19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
1258 #define EXTI_IMR_IM20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
1259 #define EXTI_IMR_IM21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
1260 #define EXTI_IMR_IM22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
1261 #define EXTI_IMR_IM23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
1262 #define EXTI_IMR_IM25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
1263 #define EXTI_IMR_IM26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
1264 #define EXTI_IMR_IM28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
1265 #define EXTI_IMR_IM29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
1266
1267 /****************** Bit definition for EXTI_EMR register ********************/
1268 #define EXTI_EMR_EM0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
1269 #define EXTI_EMR_EM1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
1270 #define EXTI_EMR_EM2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
1271 #define EXTI_EMR_EM3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
1272 #define EXTI_EMR_EM4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
1273 #define EXTI_EMR_EM5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
1274 #define EXTI_EMR_EM6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
1275 #define EXTI_EMR_EM7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
1276 #define EXTI_EMR_EM8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
1277 #define EXTI_EMR_EM9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
1278 #define EXTI_EMR_EM10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
1279 #define EXTI_EMR_EM11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
1280 #define EXTI_EMR_EM12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
1281 #define EXTI_EMR_EM13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
1282 #define EXTI_EMR_EM14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
1283 #define EXTI_EMR_EM15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
1284 #define EXTI_EMR_EM16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
1285 #define EXTI_EMR_EM17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
1286 #define EXTI_EMR_EM18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
1287 #define EXTI_EMR_EM19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
1288 #define EXTI_EMR_EM20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
1289 #define EXTI_EMR_EM21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
1290 #define EXTI_EMR_EM22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
1291 #define EXTI_EMR_EM23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
1292 #define EXTI_EMR_EM25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
1293 #define EXTI_EMR_EM26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
1294 #define EXTI_EMR_EM28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
1295 #define EXTI_EMR_EM29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
1296
1297 /******************* Bit definition for EXTI_RTSR register ******************/
1298 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
1299 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
1300 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
1301 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
1302 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
1303 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
1304 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
1305 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
1306 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
1307 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
1308 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
1309 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
1310 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
1311 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
1312 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
1313 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
1314 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
1315 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
1316 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
1317 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
1318 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
1319 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
1320
1321 /******************* Bit definition for EXTI_FTSR register *******************/
1322 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
1323 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
1324 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
1325 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
1326 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
1327 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
1328 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
1329 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
1330 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
1331 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
1332 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
1333 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
1334 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
1335 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
1336 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
1337 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
1338 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
1339 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
1340 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
1341 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
1342 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
1343 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
1344
1345 /******************* Bit definition for EXTI_SWIER register *******************/
1346 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
1347 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
1348 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
1349 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
1350 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
1351 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
1352 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
1353 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
1354 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
1355 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
1356 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
1357 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
1358 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
1359 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
1360 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
1361 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
1362 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
1363 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
1364 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
1365 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
1366 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
1367 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
1368
1369 /****************** Bit definition for EXTI_PR register *********************/
1370 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
1371 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
1372 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
1373 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
1374 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
1375 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
1376 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
1377 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
1378 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
1379 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
1380 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
1381 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
1382 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
1383 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
1384 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
1385 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
1386 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
1387 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
1388 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
1389 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
1390 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
1391 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
1392
1393 /******************************************************************************/
1394 /* */
1395 /* FLASH and Option Bytes Registers */
1396 /* */
1397 /******************************************************************************/
1398
1399 /******************* Bit definition for FLASH_ACR register ******************/
1400 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
1401 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
1402 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
1403 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
1404 #define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020) /*!< Disable Buffer */
1405 #define FLASH_ACR_PRE_READ ((uint32_t)0x00000040) /*!< Pre-read data address */
1406
1407 /******************* Bit definition for FLASH_PECR register ******************/
1408 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
1409 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
1410 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
1411 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
1412 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
1413 #define FLASH_PECR_FIX ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
1414 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
1415 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
1416 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
1417 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
1418 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
1419 #define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000) /*!< Half array mode */
1420
1421 /****************** Bit definition for FLASH_PDKEYR register ******************/
1422 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1423
1424 /****************** Bit definition for FLASH_PEKEYR register ******************/
1425 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
1426
1427 /****************** Bit definition for FLASH_PRGKEYR register ******************/
1428 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
1429
1430 /****************** Bit definition for FLASH_OPTKEYR register ******************/
1431 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
1432
1433 /****************** Bit definition for FLASH_SR register *******************/
1434 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
1435 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
1436 #define FLASH_SR_HVOFF ((uint32_t)0x00000004) /*!< End of high voltage */
1437 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
1438
1439 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
1440 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
1441 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
1442 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option Valid error */
1443 #define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
1444 #define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000) /*!< Not Zero error */
1445 #define FLASH_SR_FWWERR ((uint32_t)0x00020000) /*!< Write/Errase operation aborted */
1446
1447 /* alias maintained for legacy */
1448 #define FLASH_SR_FWWER FLASH_SR_FWWERR
1449 #define FLASH_SR_ENHV FLASH_SR_HVOFF
1450 #define FLASH_SR_ENDHV FLASH_SR_HVOFF
1451
1452 /****************** Bit definition for FLASH_OPTR register *******************/
1453 #define FLASH_OPTR_RDPROT ((uint32_t)0x000000FF) /*!< Read Protection */
1454 #define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
1455 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
1456 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
1457 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
1458 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
1459 #define FLASH_OPTR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
1460 #define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000) /*!< BOOT1 */
1461
1462 /****************** Bit definition for FLASH_WRPR register ******************/
1463 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
1464
1465 /******************************************************************************/
1466 /* */
1467 /* General Purpose IOs (GPIO) */
1468 /* */
1469 /******************************************************************************/
1470 /******************* Bit definition for GPIO_MODER register *****************/
1471 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003)
1472 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001)
1473 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002)
1474 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000C)
1475 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004)
1476 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008)
1477 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030)
1478 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010)
1479 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020)
1480 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0)
1481 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040)
1482 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080)
1483 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300)
1484 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100)
1485 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200)
1486 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00)
1487 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400)
1488 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800)
1489 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000)
1490 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000)
1491 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000)
1492 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000)
1493 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000)
1494 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000)
1495 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000)
1496 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000)
1497 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000)
1498 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000)
1499 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000)
1500 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000)
1501 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000)
1502 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000)
1503 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000)
1504 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000)
1505 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000)
1506 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000)
1507 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000)
1508 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000)
1509 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000)
1510 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000)
1511 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000)
1512 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000)
1513 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000)
1514 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000)
1515 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000)
1516 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000)
1517 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000)
1518 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000)
1519
1520 /****************** Bit definition for GPIO_OTYPER register *****************/
1521 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
1522 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
1523 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
1524 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
1525 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
1526 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
1527 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
1528 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
1529 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
1530 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
1531 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
1532 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
1533 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
1534 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
1535 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
1536 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
1537
1538 /**************** Bit definition for GPIO_OSPEEDR register ******************/
1539 #define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003)
1540 #define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001)
1541 #define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002)
1542 #define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000C)
1543 #define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004)
1544 #define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008)
1545 #define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030)
1546 #define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010)
1547 #define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020)
1548 #define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0)
1549 #define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040)
1550 #define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080)
1551 #define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300)
1552 #define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100)
1553 #define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200)
1554 #define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00)
1555 #define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400)
1556 #define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800)
1557 #define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000)
1558 #define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000)
1559 #define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000)
1560 #define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000)
1561 #define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000)
1562 #define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000)
1563 #define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000)
1564 #define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000)
1565 #define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000)
1566 #define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000)
1567 #define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000)
1568 #define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000)
1569 #define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000)
1570 #define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000)
1571 #define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000)
1572 #define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000)
1573 #define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000)
1574 #define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000)
1575 #define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000)
1576 #define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000)
1577 #define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000)
1578 #define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000)
1579 #define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000)
1580 #define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000)
1581 #define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000)
1582 #define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000)
1583 #define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000)
1584 #define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000)
1585 #define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000)
1586 #define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000)
1587
1588 /******************* Bit definition for GPIO_PUPDR register ******************/
1589 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003)
1590 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001)
1591 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002)
1592 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000C)
1593 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004)
1594 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008)
1595 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030)
1596 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010)
1597 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020)
1598 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0)
1599 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040)
1600 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080)
1601 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300)
1602 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100)
1603 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200)
1604 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00)
1605 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400)
1606 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800)
1607 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000)
1608 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000)
1609 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000)
1610 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000)
1611 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000)
1612 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000)
1613 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000)
1614 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000)
1615 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000)
1616 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000)
1617 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000)
1618 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000)
1619 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000)
1620 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000)
1621 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000)
1622 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000)
1623 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000)
1624 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000)
1625 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000)
1626 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000)
1627 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000)
1628 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000)
1629 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000)
1630 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000)
1631 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000)
1632 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000)
1633 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000)
1634 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000)
1635 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000)
1636 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000)
1637
1638 /******************* Bit definition for GPIO_IDR register *******************/
1639 #define GPIO_IDR_ID0 ((uint32_t)0x00000001)
1640 #define GPIO_IDR_ID1 ((uint32_t)0x00000002)
1641 #define GPIO_IDR_ID2 ((uint32_t)0x00000004)
1642 #define GPIO_IDR_ID3 ((uint32_t)0x00000008)
1643 #define GPIO_IDR_ID4 ((uint32_t)0x00000010)
1644 #define GPIO_IDR_ID5 ((uint32_t)0x00000020)
1645 #define GPIO_IDR_ID6 ((uint32_t)0x00000040)
1646 #define GPIO_IDR_ID7 ((uint32_t)0x00000080)
1647 #define GPIO_IDR_ID8 ((uint32_t)0x00000100)
1648 #define GPIO_IDR_ID9 ((uint32_t)0x00000200)
1649 #define GPIO_IDR_ID10 ((uint32_t)0x00000400)
1650 #define GPIO_IDR_ID11 ((uint32_t)0x00000800)
1651 #define GPIO_IDR_ID12 ((uint32_t)0x00001000)
1652 #define GPIO_IDR_ID13 ((uint32_t)0x00002000)
1653 #define GPIO_IDR_ID14 ((uint32_t)0x00004000)
1654 #define GPIO_IDR_ID15 ((uint32_t)0x00008000)
1655
1656 /****************** Bit definition for GPIO_ODR register ********************/
1657 #define GPIO_ODR_OD0 ((uint32_t)0x00000001)
1658 #define GPIO_ODR_OD1 ((uint32_t)0x00000002)
1659 #define GPIO_ODR_OD2 ((uint32_t)0x00000004)
1660 #define GPIO_ODR_OD3 ((uint32_t)0x00000008)
1661 #define GPIO_ODR_OD4 ((uint32_t)0x00000010)
1662 #define GPIO_ODR_OD5 ((uint32_t)0x00000020)
1663 #define GPIO_ODR_OD6 ((uint32_t)0x00000040)
1664 #define GPIO_ODR_OD7 ((uint32_t)0x00000080)
1665 #define GPIO_ODR_OD8 ((uint32_t)0x00000100)
1666 #define GPIO_ODR_OD9 ((uint32_t)0x00000200)
1667 #define GPIO_ODR_OD10 ((uint32_t)0x00000400)
1668 #define GPIO_ODR_OD11 ((uint32_t)0x00000800)
1669 #define GPIO_ODR_OD12 ((uint32_t)0x00001000)
1670 #define GPIO_ODR_OD13 ((uint32_t)0x00002000)
1671 #define GPIO_ODR_OD14 ((uint32_t)0x00004000)
1672 #define GPIO_ODR_OD15 ((uint32_t)0x00008000)
1673
1674 /****************** Bit definition for GPIO_BSRR register ********************/
1675 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
1676 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
1677 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
1678 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
1679 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
1680 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
1681 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
1682 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
1683 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
1684 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
1685 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
1686 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
1687 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
1688 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
1689 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
1690 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
1691 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
1692 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
1693 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
1694 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
1695 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
1696 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
1697 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
1698 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
1699 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
1700 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
1701 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
1702 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
1703 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
1704 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
1705 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
1706 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
1707
1708 /****************** Bit definition for GPIO_LCKR register ********************/
1709 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
1710 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
1711 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
1712 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
1713 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
1714 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
1715 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
1716 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
1717 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
1718 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
1719 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
1720 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
1721 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
1722 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
1723 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
1724 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
1725 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
1726
1727 /****************** Bit definition for GPIO_BRR register *********************/
1728 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
1729 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
1730 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
1731 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
1732 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
1733 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
1734 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
1735 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
1736 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
1737 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
1738 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
1739 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
1740 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
1741 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
1742 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
1743 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
1744
1745 /******************************************************************************/
1746 /* */
1747 /* Inter-integrated Circuit Interface (I2C) */
1748 /* */
1749 /******************************************************************************/
1750
1751 /******************* Bit definition for I2C_CR1 register *******************/
1752 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
1753 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
1754 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
1755 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
1756 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
1757 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
1758 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
1759 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
1760 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
1761 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
1762 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
1763 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
1764 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
1765 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
1766 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
1767 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
1768 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
1769 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
1770 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
1771 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
1772
1773 /****************** Bit definition for I2C_CR2 register ********************/
1774 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
1775 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
1776 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
1777 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
1778 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
1779 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
1780 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
1781 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
1782 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
1783 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
1784 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
1785
1786 /******************* Bit definition for I2C_OAR1 register ******************/
1787 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
1788 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
1789 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
1790
1791 /******************* Bit definition for I2C_OAR2 register ******************/
1792 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
1793 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
1794 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
1795
1796 /******************* Bit definition for I2C_TIMINGR register *******************/
1797 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
1798 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
1799 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
1800 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
1801 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
1802
1803 /******************* Bit definition for I2C_TIMEOUTR register *******************/
1804 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
1805 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
1806 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
1807 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
1808 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
1809
1810 /****************** Bit definition for I2C_ISR register *********************/
1811 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
1812 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
1813 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
1814 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
1815 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
1816 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
1817 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
1818 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
1819 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
1820 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
1821 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
1822 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
1823 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
1824 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
1825 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
1826 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
1827 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
1828
1829 /****************** Bit definition for I2C_ICR register *********************/
1830 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
1831 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
1832 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
1833 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
1834 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
1835 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
1836 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
1837 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
1838 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
1839
1840 /****************** Bit definition for I2C_PECR register *********************/
1841 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
1842
1843 /****************** Bit definition for I2C_RXDR register *********************/
1844 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
1845
1846 /****************** Bit definition for I2C_TXDR register *********************/
1847 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
1848
1849 /******************************************************************************/
1850 /* */
1851 /* Independent WATCHDOG (IWDG) */
1852 /* */
1853 /******************************************************************************/
1854 /******************* Bit definition for IWDG_KR register ********************/
1855 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
1856
1857 /******************* Bit definition for IWDG_PR register ********************/
1858 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
1859 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1860 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1861 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1862
1863 /******************* Bit definition for IWDG_RLR register *******************/
1864 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
1865
1866 /******************* Bit definition for IWDG_SR register ********************/
1867 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
1868 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
1869 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
1870
1871 /******************* Bit definition for IWDG_KR register ********************/
1872 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
1873
1874 /******************************************************************************/
1875 /* */
1876 /* LCD Controller (LCD) */
1877 /* */
1878 /******************************************************************************/
1879
1880 /******************* Bit definition for LCD_CR register *********************/
1881 #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
1882 #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
1883
1884 #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
1885 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
1886 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
1887 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
1888
1889 #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
1890 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
1891 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
1892
1893 /******************* Bit definition for LCD_FCR register ********************/
1894 #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
1895 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
1896 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
1897
1898 #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
1899 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1900 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1901 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
1902
1903 #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
1904 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
1905 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
1906 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
1907
1908 #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
1909 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1910 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1911 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
1912
1913 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
1914 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
1915 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
1916 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
1917
1918 #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
1919 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1920 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1921
1922 #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
1923 #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
1924
1925 /******************* Bit definition for LCD_SR register *********************/
1926 #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
1927 #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
1928 #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
1929 #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
1930 #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
1931 #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
1932
1933 /******************* Bit definition for LCD_CLR register ********************/
1934 #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
1935 #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
1936
1937 /******************* Bit definition for LCD_RAM register ********************/
1938 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
1939
1940 /******************************************************************************/
1941 /* */
1942 /* Low Power Timer (LPTTIM) */
1943 /* */
1944 /******************************************************************************/
1945 /****************** Bit definition for LPTIM_ISR register *******************/
1946 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
1947 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
1948 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
1949 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
1950 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
1951 #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
1952 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
1953
1954 /****************** Bit definition for LPTIM_ICR register *******************/
1955 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
1956 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
1957 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
1958 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
1959 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
1960 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
1961 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
1962
1963 /****************** Bit definition for LPTIM_IER register ********************/
1964 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
1965 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
1966 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
1967 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
1968 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
1969 #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
1970 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
1971
1972 /****************** Bit definition for LPTIM_CFGR register *******************/
1973 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
1974
1975 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
1976 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
1977 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
1978
1979 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
1980 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
1981 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
1982
1983 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
1984 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1985 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1986
1987 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
1988 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
1989 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
1990 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
1991
1992 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
1993 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
1994 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
1995 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
1996
1997 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
1998 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
1999 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
2000
2001 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
2002 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
2003 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
2004 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
2005 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
2006 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
2007
2008 /****************** Bit definition for LPTIM_CR register ********************/
2009 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
2010 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /*!< Timer start in single mode */
2011 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
2012
2013 /****************** Bit definition for LPTIM_CMP register *******************/
2014 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
2015
2016 /****************** Bit definition for LPTIM_ARR register *******************/
2017 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
2018
2019 /****************** Bit definition for LPTIM_CNT register *******************/
2020 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
2021
2022 /******************************************************************************/
2023 /* */
2024 /* MIFARE Firewall */
2025 /* */
2026 /******************************************************************************/
2027
2028 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
2029 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /*!< Code Segment Start Address */
2030 #define FW_CSL_LENG ((uint32_t)0x003FFF00) /*!< Code Segment Length */
2031 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /*!< Non Volatile Dat Segment Start Address */
2032 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /*!< Non Volatile Data Segment Length */
2033 #define FW_VDSSA_ADD ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Start Address */
2034 #define FW_VDSL_LENG ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Length */
2035
2036 /**************************Bit definition for CR register *********************/
2037 #define FW_CR_FPA ((uint32_t)0x00000001) /*!< Firewall Pre Arm*/
2038 #define FW_CR_VDS ((uint32_t)0x00000002) /*!< Volatile Data Sharing*/
2039 #define FW_CR_VDE ((uint32_t)0x00000004) /*!< Volatile Data Execution*/
2040
2041 /******************************************************************************/
2042 /* */
2043 /* Power Control (PWR) */
2044 /* */
2045 /******************************************************************************/
2046
2047 /******************** Bit definition for PWR_CR register ********************/
2048 #define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
2049 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
2050 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
2051 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
2052 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
2053
2054 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
2055 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2056 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2057 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
2058
2059 /*!< PVD level configuration */
2060 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
2061 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
2062 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
2063 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
2064 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
2065 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
2066 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
2067 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
2068
2069 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
2070 #define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
2071 #define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
2072
2073 #define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
2074 #define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2075 #define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2076 #define PWR_CR_DSEEKOFF ((uint32_t)0x00002000) /*!< Deep Sleep mode with EEPROM kept Off */
2077 #define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
2078
2079 /******************* Bit definition for PWR_CSR register ********************/
2080 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
2081 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
2082 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
2083 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
2084 #define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
2085 #define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
2086
2087 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
2088 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
2089
2090 /******************************************************************************/
2091 /* */
2092 /* Reset and Clock Control */
2093 /* */
2094 /******************************************************************************/
2095
2096 /******************** Bit definition for RCC_CR register ********************/
2097 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
2098 #define RCC_CR_HSIKERON ((uint32_t)0x00000002) /*!< Internal High Speed clock enable for some IPs Kernel */
2099 #define RCC_CR_HSIRDY ((uint32_t)0x00000004) /*!< Internal High Speed clock ready flag */
2100 #define RCC_CR_HSIDIVEN ((uint32_t)0x00000008) /*!< Internal High Speed clock divider enable */
2101 #define RCC_CR_HSIDIVF ((uint32_t)0x00000010) /*!< Internal High Speed clock divider flag */
2102 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
2103 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
2104 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
2105 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
2106 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
2107 #define RCC_CR_CSSHSEON ((uint32_t)0x00080000) /*!< HSE Clock Security System enable */
2108 #define RCC_CR_RTCPRE ((uint32_t)0x00300000) /*!< RTC/LCD prescaler [1:0] bits */
2109 #define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000) /*!< RTC/LCD prescaler Bit 0 */
2110 #define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000) /*!< RTC/LCD prescaler Bit 1 */
2111 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
2112 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
2113
2114 /******************** Bit definition for RCC_ICSCR register *****************/
2115 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
2116 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
2117
2118 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
2119 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
2120 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
2121 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
2122 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
2123 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
2124 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
2125 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
2126 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
2127 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
2128
2129 /******************** Bit definition for RCC_CRRCR register *****************/
2130 #define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001) /*!< HSI 48MHz clock enable */
2131 #define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002) /*!< HSI 48MHz clock ready flag */
2132 #define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00) /*!< HSI 48MHz clock Calibration */
2133
2134 /******************* Bit definition for RCC_CFGR register *******************/
2135 /*!< SW configuration */
2136 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
2137 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2138 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2139
2140 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
2141 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
2142 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
2143 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
2144
2145 /*!< SWS configuration */
2146 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
2147 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2148 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2149
2150 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
2151 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
2152 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
2153 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
2154
2155 /*!< HPRE configuration */
2156 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
2157 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2158 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2159 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
2160 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
2161
2162 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
2163 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
2164 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
2165 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
2166 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
2167 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
2168 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
2169 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
2170 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
2171
2172 /*!< PPRE1 configuration */
2173 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
2174 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2175 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2176 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2177
2178 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2179 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
2180 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
2181 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
2182 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
2183
2184 /*!< PPRE2 configuration */
2185 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
2186 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2187 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2188 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
2189
2190 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
2191 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
2192 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
2193 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
2194 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
2195
2196 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /*!< Wake Up from Stop Clock selection */
2197
2198 /*!< PLL entry clock source*/
2199 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
2200
2201 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
2202 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
2203
2204
2205 /*!< PLLMUL configuration */
2206 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
2207 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2208 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2209 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
2210 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
2211
2212 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
2213 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
2214 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
2215 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
2216 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
2217 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
2218 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
2219 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
2220 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
2221
2222 /*!< PLLDIV configuration */
2223 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
2224 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
2225 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
2226
2227 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
2228 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
2229 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
2230
2231 /*!< MCO configuration */
2232 #define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
2233 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2234 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2235 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
2236 #define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
2237
2238 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2239 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected as MCO source */
2240 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
2241 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
2242 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
2243 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
2244 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
2245 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
2246 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
2247
2248 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
2249 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
2250 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
2251 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
2252 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
2253 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
2254
2255 /*!<****************** Bit definition for RCC_CIER register ********************/
2256 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Enable */
2257 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Enable */
2258 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Enable */
2259 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Enable */
2260 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Enable */
2261 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Enable */
2262 #define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Enable */
2263 #define RCC_CIER_LSECSSIE ((uint32_t)0x00000080) /*!< LSE CSS Interrupt Enable */
2264
2265 /*!<****************** Bit definition for RCC_CIFR register ********************/
2266 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
2267 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
2268 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
2269 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
2270 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
2271 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
2272 #define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
2273 #define RCC_CIFR_LSECSSF ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt flag */
2274 #define RCC_CIFR_CSSF ((uint32_t)0x00000100) /*!< Clock Security System Interrupt flag */
2275
2276 /*!<****************** Bit definition for RCC_CICR register ********************/
2277 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Clear */
2278 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Clear */
2279 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Clear */
2280 #define RCC_CICR_HSERDYC ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Clear */
2281 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Clear */
2282 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Clear */
2283 #define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Clear */
2284 #define RCC_CICR_LSECSSC ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt Clear */
2285 #define RCC_CICR_CSSC ((uint32_t)0x00000100) /*!< Clock Security System Interrupt Clear */
2286
2287 /***************** Bit definition for RCC_IOPRSTR register ******************/
2288 #define RCC_IOPRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
2289 #define RCC_IOPRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
2290 #define RCC_IOPRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
2291 #define RCC_IOPRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
2292 #define RCC_IOPRSTR_GPIOHRST ((uint32_t)0x00000080) /*!< GPIO port H reset */
2293
2294 /****************** Bit definition for RCC_AHBRST register ******************/
2295 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x00000001) /*!< DMA1 reset */
2296 #define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100) /*!< Memory interface reset reset */
2297 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
2298 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000) /*!< TSC reset */
2299 #define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000) /*!< RNG reset */
2300
2301 /***************** Bit definition for RCC_APB2RSTR register *****************/
2302 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
2303 #define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004) /*!< TIM21 clock reset */
2304 #define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020) /*!< TIM22 clock reset */
2305 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 clock reset */
2306 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
2307 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
2308 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
2309
2310 /***************** Bit definition for RCC_APB1RSTR register *****************/
2311 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
2312 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
2313 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD clock reset */
2314 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
2315 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
2316 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
2317 #define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000) /*!< LPUART1 clock reset */
2318 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
2319 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
2320 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
2321 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
2322 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
2323 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
2324 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000) /*!< LPTIM1 clock reset */
2325
2326 /***************** Bit definition for RCC_IOPENR register ******************/
2327 #define RCC_IOPENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
2328 #define RCC_IOPENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
2329 #define RCC_IOPENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
2330 #define RCC_IOPENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
2331 #define RCC_IOPENR_GPIOHEN ((uint32_t)0x00000080) /*!< GPIO port H clock enable */
2332
2333 /***************** Bit definition for RCC_AHBENR register ******************/
2334 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
2335 #define RCC_AHBENR_MIFEN ((uint32_t)0x00000100) /*!< NVM interface clock enable bit */
2336 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
2337 #define RCC_AHBENR_TSCEN ((uint32_t)0x00010000) /*!< TSC clock enable */
2338 #define RCC_AHBENR_RNGEN ((uint32_t)0x00100000) /*!< RNG clock enable */
2339
2340 /***************** Bit definition for RCC_APB2ENR register ******************/
2341 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
2342 #define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004) /*!< TIM21 clock enable */
2343 #define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020) /*!< TIM22 clock enable */
2344 #define RCC_APB2ENR_MIFIEN ((uint32_t)0x00000080) /*!< MiFare Firewall clock enable */
2345 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
2346 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
2347 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
2348 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
2349
2350 /***************** Bit definition for RCC_APB1ENR register ******************/
2351 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
2352 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
2353 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
2354 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
2355 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
2356 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
2357 #define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000) /*!< LPUART1 clock enable */
2358 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
2359 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
2360 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
2361 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
2362 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
2363 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
2364 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000) /*!< LPTIM1 clock enable */
2365
2366 /****************** Bit definition for RCC_IOPSMENR register ****************/
2367 #define RCC_IOPSMENR_GPIOASMEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
2368 #define RCC_IOPSMENR_GPIOBSMEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
2369 #define RCC_IOPSMENR_GPIOCSMEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
2370 #define RCC_IOPSMENR_GPIODSMEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
2371 #define RCC_IOPSMENR_GPIOHSMEN ((uint32_t)0x00000080) /*!< GPIO port H clock enabled in sleep mode */
2372
2373 /***************** Bit definition for RCC_AHBSMENR register ******************/
2374 #define RCC_AHBSMENR_DMA1SMEN ((uint32_t)0x00000001) /*!< DMA1 clock enabled in sleep mode */
2375 #define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100) /*!< NVM interface clock enable during sleep mode */
2376 #define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200) /*!< SRAM clock enabled in sleep mode */
2377 #define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
2378 #define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000) /*!< TSC clock enabled in sleep mode */
2379 #define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000) /*!< RNG clock enabled in sleep mode */
2380
2381 /***************** Bit definition for RCC_APB2SMENR register ******************/
2382 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001) /*!< SYSCFG clock enabled in sleep mode */
2383 #define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004) /*!< TIM21 clock enabled in sleep mode */
2384 #define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020) /*!< TIM22 clock enabled in sleep mode */
2385 #define RCC_APB2SMENR_ADC1SMEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
2386 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
2387 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
2388 #define RCC_APB2SMENR_DBGMCUSMEN ((uint32_t)0x00400000) /*!< DBGMCU clock enabled in sleep mode */
2389
2390 /***************** Bit definition for RCC_APB1SMENR register ******************/
2391 #define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
2392 #define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
2393 #define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
2394 #define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
2395 #define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000) /*!< SPI2 clock enabled in sleep mode */
2396 #define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000) /*!< USART2 clock enabled in sleep mode */
2397 #define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000) /*!< LPUART1 clock enabled in sleep mode */
2398 #define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000) /*!< I2C1 clock enabled in sleep mode */
2399 #define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000) /*!< I2C2 clock enabled in sleep mode */
2400 #define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
2401 #define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000) /*!< CRS clock enabled in sleep mode */
2402 #define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000) /*!< PWR clock enabled in sleep mode */
2403 #define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000) /*!< DAC clock enabled in sleep mode */
2404 #define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000) /*!< LPTIM1 clock enabled in sleep mode */
2405
2406 /******************* Bit definition for RCC_CCIPR register *******************/
2407 /*!< USART1 Clock source selection */
2408 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003) /*!< USART1SEL[1:0] bits */
2409 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2410 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2411
2412 /*!< USART2 Clock source selection */
2413 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C) /*!< USART2SEL[1:0] bits */
2414 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2415 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2416
2417 /*!< LPUART1 Clock source selection */
2418 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
2419 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */
2420 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
2421
2422 /*!< I2C1 Clock source selection */
2423 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
2424 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2425 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2426
2427
2428 /*!< LPTIM1 Clock source selection */
2429 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
2430 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2431 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2432
2433 /*!< HSI48 Clock source selection */
2434 #define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000) /*!< HSI48 RC clock source selection bit for USB and RNG*/
2435
2436 /* Bit name alias maintained for legacy */
2437 #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
2438
2439 /******************* Bit definition for RCC_CSR register *******************/
2440 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
2441 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
2442
2443 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
2444 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
2445 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
2446
2447 #define RCC_CSR_LSEDRV ((uint32_t)0x00001800) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
2448 #define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2449 #define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2450
2451 #define RCC_CSR_LSECSSON ((uint32_t)0x00002000) /*!< External Low Speed oscillator CSS Enable */
2452 #define RCC_CSR_LSECSSD ((uint32_t)0x00004000) /*!< External Low Speed oscillator CSS Detected */
2453
2454 /*!< RTC congiguration */
2455 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
2456 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2457 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2458
2459 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2460 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
2461 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
2462 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock used as RTC clock */
2463
2464 #define RCC_CSR_RTCEN ((uint32_t)0x00040000) /*!< RTC clock enable */
2465 #define RCC_CSR_RTCRST ((uint32_t)0x00080000) /*!< RTC software reset */
2466
2467 #define RCC_CSR_RMVF ((uint32_t)0x00800000) /*!< Remove reset flag */
2468 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000) /*!< Mifare Firewall reset flag */
2469 #define RCC_CSR_OBL ((uint32_t)0x02000000) /*!< OBL reset flag */
2470 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
2471 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
2472 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
2473 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
2474 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
2475 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
2476
2477 /******************************************************************************/
2478 /* */
2479 /* RNG */
2480 /* */
2481 /******************************************************************************/
2482 /******************** Bits definition for RNG_CR register *******************/
2483 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
2484 #define RNG_CR_IE ((uint32_t)0x00000008)
2485
2486 /******************** Bits definition for RNG_SR register *******************/
2487 #define RNG_SR_DRDY ((uint32_t)0x00000001)
2488 #define RNG_SR_CECS ((uint32_t)0x00000002)
2489 #define RNG_SR_SECS ((uint32_t)0x00000004)
2490 #define RNG_SR_CEIS ((uint32_t)0x00000020)
2491 #define RNG_SR_SEIS ((uint32_t)0x00000040)
2492
2493 /******************************************************************************/
2494 /* */
2495 /* Real-Time Clock (RTC) */
2496 /* */
2497 /******************************************************************************/
2498 /******************** Bits definition for RTC_TR register *******************/
2499 #define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
2500 #define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
2501 #define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
2502 #define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
2503 #define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
2504 #define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
2505 #define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
2506 #define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
2507 #define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
2508 #define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
2509 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
2510 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
2511 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
2512 #define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
2513 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
2514 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
2515 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
2516 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
2517 #define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
2518 #define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
2519 #define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
2520 #define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
2521 #define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
2522 #define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
2523 #define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
2524 #define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
2525 #define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
2526
2527 /******************** Bits definition for RTC_DR register *******************/
2528 #define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
2529 #define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
2530 #define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
2531 #define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
2532 #define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
2533 #define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
2534 #define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
2535 #define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
2536 #define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
2537 #define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
2538 #define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
2539 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
2540 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
2541 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
2542 #define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
2543 #define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
2544 #define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
2545 #define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
2546 #define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
2547 #define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
2548 #define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
2549 #define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
2550 #define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
2551 #define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
2552 #define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
2553 #define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
2554 #define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
2555 #define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
2556
2557 /******************** Bits definition for RTC_CR register *******************/
2558 #define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
2559 #define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
2560 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
2561 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
2562 #define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
2563 #define RTC_CR_COSEL ((uint32_t)0x00080000) /*!< */
2564 #define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
2565 #define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
2566 #define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
2567 #define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
2568 #define RTC_CR_WUTIE ((uint32_t)0x00004000) /*!< */
2569 #define RTC_CR_ALRBIE ((uint32_t)0x00002000) /*!< */
2570 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
2571 #define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
2572 #define RTC_CR_WUTE ((uint32_t)0x00000400) /*!< */
2573 #define RTC_CR_ALRBE ((uint32_t)0x00000200) /*!< */
2574 #define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
2575 #define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
2576 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
2577 #define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
2578 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
2579 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) /*!< */
2580 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) /*!< */
2581 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) /*!< */
2582 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) /*!< */
2583
2584 /******************** Bits definition for RTC_ISR register ******************/
2585 #define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
2586 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
2587 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
2588 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
2589 #define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
2590 #define RTC_ISR_WUTF ((uint32_t)0x00000400) /*!< */
2591 #define RTC_ISR_ALRBF ((uint32_t)0x00000200) /*!< */
2592 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
2593 #define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
2594 #define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
2595 #define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
2596 #define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
2597 #define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
2598 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) /*!< */
2599 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) /*!< */
2600 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
2601
2602 /******************** Bits definition for RTC_PRER register *****************/
2603 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
2604 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
2605
2606 /******************** Bits definition for RTC_WUTR register *****************/
2607 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
2608
2609 /******************** Bits definition for RTC_ALRMAR register ***************/
2610 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
2611 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
2612 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
2613 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
2614 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
2615 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
2616 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
2617 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
2618 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
2619 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
2620 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
2621 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
2622 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
2623 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
2624 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
2625 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
2626 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
2627 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
2628 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
2629 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
2630 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
2631 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
2632 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
2633 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
2634 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
2635 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
2636 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
2637 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
2638 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
2639 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
2640 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
2641 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
2642 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
2643 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
2644 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
2645 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
2646 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
2647 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
2648 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
2649 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
2650
2651 /******************** Bits definition for RTC_ALRMBR register ***************/
2652 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) /*!< */
2653 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) /*!< */
2654 #define RTC_ALRMBR_DT ((uint32_t)0x30000000) /*!< */
2655 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) /*!< */
2656 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) /*!< */
2657 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) /*!< */
2658 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) /*!< */
2659 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) /*!< */
2660 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) /*!< */
2661 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) /*!< */
2662 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) /*!< */
2663 #define RTC_ALRMBR_PM ((uint32_t)0x00400000) /*!< */
2664 #define RTC_ALRMBR_HT ((uint32_t)0x00300000) /*!< */
2665 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) /*!< */
2666 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) /*!< */
2667 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) /*!< */
2668 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) /*!< */
2669 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) /*!< */
2670 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) /*!< */
2671 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) /*!< */
2672 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) /*!< */
2673 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) /*!< */
2674 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) /*!< */
2675 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) /*!< */
2676 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) /*!< */
2677 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) /*!< */
2678 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) /*!< */
2679 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) /*!< */
2680 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) /*!< */
2681 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) /*!< */
2682 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) /*!< */
2683 #define RTC_ALRMBR_ST ((uint32_t)0x00000070) /*!< */
2684 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) /*!< */
2685 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) /*!< */
2686 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) /*!< */
2687 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) /*!< */
2688 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) /*!< */
2689 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) /*!< */
2690 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) /*!< */
2691 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) /*!< */
2692
2693 /******************** Bits definition for RTC_WPR register ******************/
2694 #define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
2695
2696 /******************** Bits definition for RTC_SSR register ******************/
2697 #define RTC_SSR_SS ((uint32_t)0x0000FFFF) /*!< */
2698
2699 /******************** Bits definition for RTC_SHIFTR register ***************/
2700 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
2701 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
2702
2703 /******************** Bits definition for RTC_TSTR register *****************/
2704 #define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
2705 #define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
2706 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
2707 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
2708 #define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
2709 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
2710 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
2711 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
2712 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
2713 #define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
2714 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
2715 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
2716 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
2717 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
2718 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
2719 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
2720 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
2721 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
2722 #define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
2723 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
2724 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
2725 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
2726 #define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
2727 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
2728 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
2729 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
2730 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
2731
2732 /******************** Bits definition for RTC_TSDR register *****************/
2733 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
2734 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
2735 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
2736 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
2737 #define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
2738 #define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
2739 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
2740 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
2741 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
2742 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
2743 #define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
2744 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
2745 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
2746 #define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
2747 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
2748 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
2749 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
2750 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
2751
2752 /******************** Bits definition for RTC_TSSSR register ****************/
2753 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
2754
2755 /******************** Bits definition for RTC_CAL register *****************/
2756 #define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
2757 #define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
2758 #define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
2759 #define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
2760 #define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
2761 #define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
2762 #define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
2763 #define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
2764 #define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
2765 #define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
2766 #define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
2767 #define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
2768 #define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
2769
2770 /******************** Bits definition for RTC_TAMPCR register ****************/
2771 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000) /*!< */
2772 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000) /*!< */
2773 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000) /*!< */
2774 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000) /*!< */
2775 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000) /*!< */
2776 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000) /*!< */
2777 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
2778 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
2779 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
2780 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
2781 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
2782 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
2783 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
2784 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
2785 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
2786 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
2787 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
2788 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080) /*!< */
2789 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010) /*!< */
2790 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008) /*!< */
2791 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004) /*!< */
2792 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
2793 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001) /*!< */
2794
2795 /******************** Bits definition for RTC_ALRMASSR register *************/
2796 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
2797 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
2798 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
2799 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
2800 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
2801 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
2802
2803 /******************** Bits definition for RTC_ALRMBSSR register *************/
2804 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
2805 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
2806 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
2807 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
2808 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
2809 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
2810
2811 /******************** Bits definition for RTC_OR register ****************/
2812 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002) /*!< */
2813 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
2814
2815 /* Bit names aliases maintained for legacy */
2816 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
2817
2818 /******************** Bits definition for RTC_BKP0R register ****************/
2819 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
2820
2821 /******************** Bits definition for RTC_BKP1R register ****************/
2822 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
2823
2824 /******************** Bits definition for RTC_BKP2R register ****************/
2825 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
2826
2827 /******************** Bits definition for RTC_BKP3R register ****************/
2828 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
2829
2830 /******************** Bits definition for RTC_BKP4R register ****************/
2831 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
2832
2833 /******************************************************************************/
2834 /* */
2835 /* Serial Peripheral Interface (SPI) */
2836 /* */
2837 /******************************************************************************/
2838 /******************* Bit definition for SPI_CR1 register ********************/
2839 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
2840 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
2841 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
2842 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
2843 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
2844 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
2845 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
2846 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
2847 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
2848 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
2849 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
2850 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
2851 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
2852 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
2853 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
2854 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
2855 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
2856
2857 /******************* Bit definition for SPI_CR2 register ********************/
2858 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
2859 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
2860 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
2861 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
2862 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
2863 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
2864 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
2865
2866 /******************** Bit definition for SPI_SR register ********************/
2867 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
2868 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
2869 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
2870 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
2871 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
2872 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
2873 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
2874 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
2875 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
2876
2877 /******************** Bit definition for SPI_DR register ********************/
2878 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
2879
2880 /******************* Bit definition for SPI_CRCPR register ******************/
2881 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
2882
2883 /****************** Bit definition for SPI_RXCRCR register ******************/
2884 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
2885
2886 /****************** Bit definition for SPI_TXCRCR register ******************/
2887 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
2888
2889 /****************** Bit definition for SPI_I2SCFGR register *****************/
2890 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
2891 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
2892 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
2893 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
2894 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
2895 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
2896 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2897 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2898 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
2899 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
2900 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2901 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2902 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
2903 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
2904 /****************** Bit definition for SPI_I2SPR register *******************/
2905 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
2906 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
2907 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
2908
2909 /******************************************************************************/
2910 /* */
2911 /* System Configuration (SYSCFG) */
2912 /* */
2913 /******************************************************************************/
2914 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
2915 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
2916 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
2917 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
2918 #define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
2919 #define SYSCFG_CFGR1_BOOT_MOD_0 ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
2920 #define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
2921
2922 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
2923 #define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001) /*!< Firewall disable bit */
2924 #define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000000E) /*!< Connection of internal Vlcd rail to external capacitors */
2925 #define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002)
2926 #define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004)
2927 #define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008)
2928 #define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
2929 #define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
2930 #define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
2931 #define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
2932 #define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
2933 #define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
2934
2935 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
2936 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
2937 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
2938 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
2939 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
2940
2941 /**
2942 * @brief EXTI0 configuration
2943 */
2944 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
2945 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
2946 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
2947 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
2948
2949 /**
2950 * @brief EXTI1 configuration
2951 */
2952 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
2953 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
2954 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
2955 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
2956
2957 /**
2958 * @brief EXTI2 configuration
2959 */
2960 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
2961 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
2962 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
2963 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
2964
2965 /**
2966 * @brief EXTI3 configuration
2967 */
2968 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
2969 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
2970 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
2971
2972 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
2973 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
2974 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
2975 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
2976 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
2977
2978 /**
2979 * @brief EXTI4 configuration
2980 */
2981 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
2982 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
2983 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
2984
2985 /**
2986 * @brief EXTI5 configuration
2987 */
2988 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
2989 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
2990 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
2991
2992 /**
2993 * @brief EXTI6 configuration
2994 */
2995 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
2996 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
2997 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
2998
2999 /**
3000 * @brief EXTI7 configuration
3001 */
3002 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
3003 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
3004 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
3005
3006 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
3007 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
3008 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
3009 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
3010 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
3011
3012 /**
3013 * @brief EXTI8 configuration
3014 */
3015 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
3016 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
3017 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
3018
3019 /**
3020 * @brief EXTI9 configuration
3021 */
3022 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
3023 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
3024 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
3025
3026 /**
3027 * @brief EXTI10 configuration
3028 */
3029 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
3030 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
3031 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
3032
3033 /**
3034 * @brief EXTI11 configuration
3035 */
3036 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
3037 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
3038 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
3039
3040 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
3041 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
3042 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
3043 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
3044 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
3045
3046 /**
3047 * @brief EXTI12 configuration
3048 */
3049 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
3050 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
3051 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
3052
3053 /**
3054 * @brief EXTI13 configuration
3055 */
3056 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
3057 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
3058 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
3059
3060 /**
3061 * @brief EXTI14 configuration
3062 */
3063 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
3064 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
3065 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
3066
3067 /**
3068 * @brief EXTI15 configuration
3069 */
3070 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
3071 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
3072 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
3073
3074
3075 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
3076 #define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001) /*!< Vref Enable bit*/
3077 #define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
3078 #define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
3079 #define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
3080 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
3081 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
3082 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
3083 #define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
3084 #define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
3085 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
3086 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
3087 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
3088 #define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000) /*!< VREFINT ready flag */
3089 #define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
3090
3091 /* Bit names aliases maintained for legacy */
3092
3093 #define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
3094 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
3095 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
3096 #define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
3097 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_REF_HSI48_RDYF
3098 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF
3099
3100 /******************************************************************************/
3101 /* */
3102 /* Timers (TIM) */
3103 /* */
3104 /******************************************************************************/
3105 /******************* Bit definition for TIM_CR1 register ********************/
3106 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
3107 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
3108 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
3109 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
3110 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
3111
3112 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
3113 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3114 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3115
3116 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
3117
3118 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
3119 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3120 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3121
3122 /******************* Bit definition for TIM_CR2 register ********************/
3123 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
3124 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
3125 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
3126
3127 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
3128 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3129 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3130 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3131
3132 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
3133 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
3134 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
3135 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
3136 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
3137 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
3138 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
3139 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
3140
3141 /******************* Bit definition for TIM_SMCR register *******************/
3142 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
3143 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3144 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3145 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3146
3147 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
3148
3149 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
3150 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3151 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3152 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3153
3154 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
3155
3156 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
3157 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3158 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3159 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3160 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3161
3162 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
3163 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3164 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3165
3166 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
3167 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
3168
3169 /******************* Bit definition for TIM_DIER register *******************/
3170 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
3171 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
3172 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
3173 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
3174 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
3175 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
3176 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
3177 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
3178 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
3179 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
3180 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
3181 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
3182
3183 /******************** Bit definition for TIM_SR register ********************/
3184 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
3185 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
3186 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
3187 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
3188 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
3189 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
3190 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
3191 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
3192 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
3193 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
3194 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
3195 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
3196
3197 /******************* Bit definition for TIM_EGR register ********************/
3198 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
3199 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
3200 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
3201 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
3202 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
3203 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
3204 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
3205 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
3206
3207 /****************** Bit definition for TIM_CCMR1 register *******************/
3208 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
3209 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3210 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3211
3212 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
3213 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
3214
3215 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
3216 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3217 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3218 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3219
3220 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
3221
3222 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
3223 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3224 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3225
3226 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
3227 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
3228
3229 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
3230 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3231 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3232 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3233
3234 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
3235
3236 /*----------------------------------------------------------------------------*/
3237
3238 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
3239 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3240 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3241
3242 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
3243 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3244 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3245 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3246 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3247
3248 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
3249 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3250 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3251
3252 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
3253 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3254 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3255 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3256 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
3257
3258 /****************** Bit definition for TIM_CCMR2 register *******************/
3259 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
3260 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3261 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3262
3263 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
3264 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
3265
3266 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
3267 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3268 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3269 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3270
3271 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
3272
3273 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
3274 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3275 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3276
3277 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
3278 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
3279
3280 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
3281 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3282 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3283 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3284
3285 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
3286
3287 /*----------------------------------------------------------------------------*/
3288
3289 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
3290 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3291 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3292
3293 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
3294 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3295 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3296 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3297 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3298
3299 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
3300 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3301 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3302
3303 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
3304 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3305 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3306 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3307 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
3308
3309 /******************* Bit definition for TIM_CCER register *******************/
3310 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
3311 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
3312 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
3313 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
3314 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
3315 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
3316 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
3317 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
3318 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
3319 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
3320 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
3321 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
3322 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
3323 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
3324 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
3325
3326 /******************* Bit definition for TIM_CNT register ********************/
3327 #define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
3328
3329 /******************* Bit definition for TIM_PSC register ********************/
3330 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
3331
3332 /******************* Bit definition for TIM_ARR register ********************/
3333 #define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
3334
3335 /******************* Bit definition for TIM_RCR register ********************/
3336 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
3337
3338 /******************* Bit definition for TIM_CCR1 register *******************/
3339 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
3340
3341 /******************* Bit definition for TIM_CCR2 register *******************/
3342 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
3343
3344 /******************* Bit definition for TIM_CCR3 register *******************/
3345 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
3346
3347 /******************* Bit definition for TIM_CCR4 register *******************/
3348 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
3349
3350 /******************* Bit definition for TIM_BDTR register *******************/
3351 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
3352 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3353 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3354 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3355 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3356 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3357 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3358 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3359 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3360
3361 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
3362 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3363 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3364
3365 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
3366 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
3367 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
3368 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
3369 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
3370 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
3371
3372 /******************* Bit definition for TIM_DCR register ********************/
3373 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
3374 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3375 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3376 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3377 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3378 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3379
3380 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
3381 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3382 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3383 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3384 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3385 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3386
3387 /******************* Bit definition for TIM_DMAR register *******************/
3388 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
3389
3390 /******************* Bit definition for TIM_OR register *********************/
3391 #define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
3392 #define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3393 #define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3394 #define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3395 #define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
3396 #define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3397 #define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3398
3399 #define TIM21_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
3400 #define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3401 #define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3402 #define TIM21_OR_TI1_RMP ((uint32_t)0x0000001C) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
3403 #define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3404 #define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3405 #define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010) /*!<Bit 2 */
3406 #define TIM21_OR_TI2_RMP ((uint32_t)0x00000020) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
3407
3408 #define TIM22_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
3409 #define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3410 #define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3411 #define TIM22_OR_TI1_RMP ((uint32_t)0x0000000C) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
3412 #define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3413 #define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3414
3415
3416 /******************************************************************************/
3417 /* */
3418 /* Touch Sensing Controller (TSC) */
3419 /* */
3420 /******************************************************************************/
3421 /******************* Bit definition for TSC_CR register *********************/
3422 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
3423 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
3424 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
3425 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
3426 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
3427
3428 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
3429 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3430 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3431 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3432
3433 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
3434 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3435 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3436 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3437
3438 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
3439 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
3440
3441 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
3442 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3443 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3444 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3445 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
3446 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
3447 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
3448 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
3449
3450 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
3451 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3452 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3453 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3454 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3455
3456 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
3457 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3458 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3459 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
3460 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
3461
3462 /******************* Bit definition for TSC_IER register ********************/
3463 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
3464 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
3465
3466 /******************* Bit definition for TSC_ICR register ********************/
3467 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
3468 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
3469
3470 /******************* Bit definition for TSC_ISR register ********************/
3471 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
3472 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
3473
3474 /******************* Bit definition for TSC_IOHCR register ******************/
3475 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
3476 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
3477 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
3478 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
3479 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
3480 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
3481 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
3482 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
3483 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
3484 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
3485 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
3486 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
3487 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
3488 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
3489 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
3490 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
3491 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
3492 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
3493 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
3494 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
3495 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
3496 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
3497 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
3498 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
3499 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
3500 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
3501 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
3502 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
3503 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
3504 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
3505 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
3506 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
3507
3508 /******************* Bit definition for TSC_IOASCR register *****************/
3509 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
3510 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
3511 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
3512 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
3513 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
3514 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
3515 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
3516 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
3517 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
3518 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
3519 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
3520 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
3521 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
3522 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
3523 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
3524 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
3525 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
3526 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
3527 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
3528 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
3529 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
3530 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
3531 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
3532 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
3533 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
3534 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
3535 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
3536 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
3537 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
3538 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
3539 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
3540 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
3541
3542 /******************* Bit definition for TSC_IOSCR register ******************/
3543 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
3544 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
3545 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
3546 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
3547 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
3548 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
3549 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
3550 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
3551 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
3552 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
3553 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
3554 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
3555 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
3556 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
3557 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
3558 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
3559 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
3560 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
3561 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
3562 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
3563 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
3564 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
3565 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
3566 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
3567 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
3568 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
3569 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
3570 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
3571 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
3572 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
3573 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
3574 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
3575
3576 /******************* Bit definition for TSC_IOCCR register ******************/
3577 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
3578 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
3579 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
3580 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
3581 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
3582 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
3583 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
3584 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
3585 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
3586 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
3587 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
3588 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
3589 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
3590 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
3591 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
3592 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
3593 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
3594 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
3595 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
3596 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
3597 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
3598 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
3599 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
3600 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
3601 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
3602 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
3603 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
3604 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
3605 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
3606 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
3607 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
3608 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
3609
3610 /******************* Bit definition for TSC_IOGCSR register *****************/
3611 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
3612 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
3613 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
3614 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
3615 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
3616 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
3617 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
3618 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
3619 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
3620 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
3621 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
3622 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
3623 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
3624 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
3625 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
3626 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
3627
3628 /******************* Bit definition for TSC_IOGXCR register *****************/
3629 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
3630
3631 /******************************************************************************/
3632 /* */
3633 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
3634 /* */
3635 /******************************************************************************/
3636 /****************** Bit definition for USART_CR1 register *******************/
3637 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
3638 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
3639 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
3640 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
3641 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
3642 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
3643 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
3644 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
3645 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
3646 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
3647 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
3648 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
3649 #define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
3650 #define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
3651 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
3652 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
3653 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
3654 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
3655 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3656 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3657 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3658 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3659 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3660 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
3661 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
3662 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
3663 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
3664 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
3665 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
3666 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
3667 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
3668 #define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
3669 /****************** Bit definition for USART_CR2 register *******************/
3670 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
3671 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
3672 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
3673 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
3674 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
3675 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
3676 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
3677 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
3678 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3679 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3680 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
3681 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
3682 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
3683 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
3684 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
3685 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
3686 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
3687 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
3688 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
3689 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
3690 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
3691 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
3692
3693 /****************** Bit definition for USART_CR3 register *******************/
3694 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
3695 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
3696 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
3697 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
3698 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
3699 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
3700 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
3701 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
3702 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
3703 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
3704 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
3705 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
3706 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
3707 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
3708 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
3709 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
3710 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
3711 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
3712 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
3713 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
3714 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
3715 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
3716 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
3717 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
3718 #define USART_CR3_UCESM ((uint32_t)0x00800000) /*!< Clock Enable in Stop mode */
3719
3720 /****************** Bit definition for USART_BRR register *******************/
3721 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
3722 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
3723
3724 /****************** Bit definition for USART_GTPR register ******************/
3725 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
3726 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
3727
3728
3729 /******************* Bit definition for USART_RTOR register *****************/
3730 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
3731 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
3732
3733 /******************* Bit definition for USART_RQR register ******************/
3734 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
3735 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
3736 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
3737 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
3738 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
3739
3740 /******************* Bit definition for USART_ISR register ******************/
3741 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
3742 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
3743 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
3744 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
3745 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
3746 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
3747 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
3748 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
3749 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
3750 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
3751 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
3752 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
3753 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
3754 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
3755 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
3756 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
3757 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
3758 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
3759 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
3760 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
3761 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
3762 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
3763
3764 /******************* Bit definition for USART_ICR register ******************/
3765 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
3766 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
3767 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
3768 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
3769 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
3770 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
3771 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
3772 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
3773 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
3774 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
3775 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
3776 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
3777
3778 /******************* Bit definition for USART_RDR register ******************/
3779 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
3780
3781 /******************* Bit definition for USART_TDR register ******************/
3782 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
3783
3784 /******************************************************************************/
3785 /* */
3786 /* USB Device General registers */
3787 /* */
3788 /******************************************************************************/
3789 #define USB_BASE ((uint32_t)0x40005C00) /*!< USB_IP Peripheral Registers base address */
3790 #define USB_PMAADDR ((uint32_t)0x40006000) /*!< USB_IP Packet Memory Area base address */
3791
3792 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
3793 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
3794 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
3795 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
3796 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
3797 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
3798 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
3799
3800 /**************************** ISTR interrupt events *************************/
3801 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
3802 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
3803 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
3804 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
3805 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
3806 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
3807 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
3808 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
3809 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
3810 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
3811 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
3812
3813 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
3814 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
3815 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
3816 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
3817 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
3818 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
3819 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
3820 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
3821 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
3822 /************************* CNTR control register bits definitions ***********/
3823 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
3824 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
3825 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
3826 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
3827 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
3828 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
3829 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
3830 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
3831 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
3832 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
3833 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
3834 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
3835 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
3836 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
3837 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
3838 /************************* BCDR control register bits definitions ***********/
3839 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
3840 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
3841 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
3842 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
3843 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
3844 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
3845 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
3846 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
3847 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
3848 /*************************** LPM register bits definitions ******************/
3849 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
3850 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
3851 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
3852 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
3853 /******************** FNR Frame Number Register bit definitions ************/
3854 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
3855 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
3856 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
3857 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
3858 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
3859 /******************** DADDR Device ADDRess bit definitions ****************/
3860 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
3861 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
3862 /****************************** Endpoint register *************************/
3863 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
3864 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
3865 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
3866 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
3867 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
3868 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
3869 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
3870 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
3871 /* bit positions */
3872 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
3873 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
3874 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
3875 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
3876 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
3877 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
3878 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
3879 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
3880 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
3881 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
3882
3883 /* EndPoint REGister MASK (no toggle fields) */
3884 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
3885 /*!< EP_TYPE[1:0] EndPoint TYPE */
3886 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
3887 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
3888 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
3889 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
3890 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
3891 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
3892
3893 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
3894 /*!< STAT_TX[1:0] STATus for TX transfer */
3895 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
3896 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
3897 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
3898 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
3899 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
3900 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
3901 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
3902 /*!< STAT_RX[1:0] STATus for RX transfer */
3903 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
3904 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
3905 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
3906 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
3907 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
3908 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
3909 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
3910
3911 /******************************************************************************/
3912 /* */
3913 /* Window WATCHDOG (WWDG) */
3914 /* */
3915 /******************************************************************************/
3916
3917 /******************* Bit definition for WWDG_CR register ********************/
3918 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
3919 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
3920 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
3921 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
3922 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
3923 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
3924 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
3925 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
3926
3927 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
3928
3929 /******************* Bit definition for WWDG_CFR register *******************/
3930 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
3931 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
3932 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
3933 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
3934 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
3935 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
3936 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
3937 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
3938
3939 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
3940 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
3941 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
3942
3943 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
3944
3945 /******************* Bit definition for WWDG_SR register ********************/
3946 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
3947
3948 /**
3949 * @}
3950 */
3951
3952 /**
3953 * @}
3954 */
3955
3956 /** @addtogroup Exported_macros
3957 * @{
3958 */
3959
3960 /******************************* ADC Instances ********************************/
3961 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
3962
3963 /******************************* COMP Instances *******************************/
3964 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
3965 ((INSTANCE) == COMP2))
3966
3967 /******************************* CRC Instances ********************************/
3968 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
3969
3970 /******************************* DAC Instances *********************************/
3971 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
3972
3973 /******************************* DMA Instances *********************************/
3974 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
3975 ((INSTANCE) == DMA1_Stream1) || \
3976 ((INSTANCE) == DMA1_Stream2) || \
3977 ((INSTANCE) == DMA1_Stream3) || \
3978 ((INSTANCE) == DMA1_Stream4) || \
3979 ((INSTANCE) == DMA1_Stream5) || \
3980 ((INSTANCE) == DMA1_Stream6) || \
3981 ((INSTANCE) == DMA1_Stream7))
3982
3983 /******************************* GPIO Instances *******************************/
3984 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
3985 ((INSTANCE) == GPIOB) || \
3986 ((INSTANCE) == GPIOC) || \
3987 ((INSTANCE) == GPIOD) || \
3988 ((INSTANCE) == GPIOH))
3989
3990 /******************************** I2C Instances *******************************/
3991 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
3992 ((INSTANCE) == I2C2))
3993
3994 /******************************** I2S Instances *******************************/
3995 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
3996
3997 /******************************* RNG Instances ********************************/
3998 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
3999
4000 /****************************** RTC Instances *********************************/
4001 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
4002
4003 /******************************** SMBUS Instances *****************************/
4004 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
4005
4006 /******************************** SPI Instances *******************************/
4007 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
4008 ((INSTANCE) == SPI2))
4009
4010 /****************** LPTIM Instances : All supported instances *****************/
4011 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
4012
4013 /****************** TIM Instances : All supported instances *******************/
4014 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4015 ((INSTANCE) == TIM6) || \
4016 ((INSTANCE) == TIM21) || \
4017 ((INSTANCE) == TIM22))
4018
4019 /************* TIM Instances : at least 1 capture/compare channel *************/
4020 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4021 ((INSTANCE) == TIM21) || \
4022 ((INSTANCE) == TIM22))
4023
4024 /************ TIM Instances : at least 2 capture/compare channels *************/
4025 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4026 ((INSTANCE) == TIM21) || \
4027 ((INSTANCE) == TIM22))
4028
4029 /************ TIM Instances : at least 3 capture/compare channels *************/
4030 #define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
4031
4032 /************ TIM Instances : at least 4 capture/compare channels *************/
4033 #define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
4034
4035 /******************** TIM Instances : Advanced-control timers *****************/
4036
4037 /******************* TIM Instances : Timer input XOR function *****************/
4038 #define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
4039
4040 /****************** TIM Instances : DMA requests generation (UDE) *************/
4041 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4042 ((INSTANCE) == TIM6))
4043
4044 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
4045 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
4046
4047 /************ TIM Instances : DMA requests generation (COMDE) *****************/
4048 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
4049
4050 /******************** TIM Instances : DMA burst feature ***********************/
4051 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
4052
4053 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
4054 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4055 ((INSTANCE) == TIM6) || \
4056 ((INSTANCE) == TIM21) || \
4057 ((INSTANCE) == TIM22))
4058
4059 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
4060 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4061 ((INSTANCE) == TIM21) || \
4062 ((INSTANCE) == TIM22))
4063
4064 /********************** TIM Instances : 32 bit Counter ************************/
4065
4066 /***************** TIM Instances : external trigger input availabe ************/
4067 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4068 ((INSTANCE) == TIM21) || \
4069 ((INSTANCE) == TIM22))
4070
4071 /****************** TIM Instances : remapping capability **********************/
4072 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4073 ((INSTANCE) == TIM21) || \
4074 ((INSTANCE) == TIM22))
4075
4076 /******************* TIM Instances : output(s) available **********************/
4077 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
4078 ((((INSTANCE) == TIM2) && \
4079 (((CHANNEL) == TIM_CHANNEL_1) || \
4080 ((CHANNEL) == TIM_CHANNEL_2) || \
4081 ((CHANNEL) == TIM_CHANNEL_3) || \
4082 ((CHANNEL) == TIM_CHANNEL_4))) \
4083 || \
4084 (((INSTANCE) == TIM21) && \
4085 (((CHANNEL) == TIM_CHANNEL_1) || \
4086 ((CHANNEL) == TIM_CHANNEL_2))) \
4087 || \
4088 (((INSTANCE) == TIM22) && \
4089 (((CHANNEL) == TIM_CHANNEL_1) || \
4090 ((CHANNEL) == TIM_CHANNEL_2))))
4091
4092 /******************** UART Instances : Asynchronous mode **********************/
4093 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4094 ((INSTANCE) == USART2) || \
4095 ((INSTANCE) == LPUART1))
4096
4097 /******************** USART Instances : Synchronous mode **********************/
4098 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4099 ((INSTANCE) == USART2))
4100
4101 /****************** USART Instances : Auto Baud Rate detection ****************/
4102
4103 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4104 ((INSTANCE) == USART2))
4105
4106 /******************** UART Instances : Half-Duplex mode **********************/
4107 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4108 ((INSTANCE) == USART2) || \
4109 ((INSTANCE) == LPUART1))
4110
4111 /******************** UART Instances : LIN mode **********************/
4112 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4113 ((INSTANCE) == USART2))
4114
4115 /******************** UART Instances : Wake-up from Stop mode **********************/
4116
4117 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4118 ((INSTANCE) == USART2) || \
4119 ((INSTANCE) == LPUART1))
4120
4121 /****************** UART Instances : Hardware Flow control ********************/
4122 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4123 ((INSTANCE) == USART2) || \
4124 ((INSTANCE) == LPUART1))
4125
4126 /********************* UART Instances : Smard card mode ***********************/
4127 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4128 ((INSTANCE) == USART2))
4129
4130 /*********************** UART Instances : IRDA mode ***************************/
4131 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4132 ((INSTANCE) == USART2))
4133
4134 /****************************** IWDG Instances ********************************/
4135 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
4136
4137 /****************************** USB Instances ********************************/
4138 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
4139
4140 /****************************** WWDG Instances ********************************/
4141 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
4142
4143 /****************************** LCD Instances ********************************/
4144 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
4145
4146 /**
4147 * @}
4148 */
4149
4150 /******************************************************************************/
4151 /* For a painless codes migration between the STM32L0xx device product */
4152 /* lines, the aliases defined below are put in place to overcome the */
4153 /* differences in the interrupt handlers and IRQn definitions. */
4154 /* No need to update developed interrupt code when moving across */
4155 /* product lines within the same STM32L0 Family */
4156 /******************************************************************************/
4157
4158 /* Aliases for __IRQn */
4159
4160 #define LPUART1_IRQn RNG_LPUART1_IRQn
4161 #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
4162 #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
4163 #define TIM6_IRQn TIM6_DAC_IRQn
4164 #define RCC_IRQn RCC_CRS_IRQn
4165
4166 /* Aliases for __IRQHandler */
4167 #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
4168 #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
4169 #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
4170 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
4171 #define RCC_IRQHandler RCC_CRS_IRQHandler
4172
4173 /**
4174 * @}
4175 */
4176
4177 /**
4178 * @}
4179 */
4180
4181 #ifdef __cplusplus
4182 }
4183 #endif /* __cplusplus */
4184
4185 #endif /* __STM32L053xx_H */
4186
4187
4188
4189 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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