tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32L1xx_HAL_DMA_H
  40 #define __STM32L1xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32l1xx_hal_def.h"
  48
  49 /** @addtogroup STM32L1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup DMA
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup DMA_Exported_Types DMA Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  DMA Configuration Structure definition
  64   */
  65 typedef struct
  66 {
  67   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  68                                            from memory to memory or from peripheral to memory.
  69                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  70
  71   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  72                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  73
  74   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  75                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  76
  77   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  78                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  79
  80   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  81                                            This parameter can be a value of @ref DMA_Memory_data_size */
  82
  83   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  84                                            This parameter can be a value of @ref DMA_mode
  85                                            @note The circular buffer mode cannot be used if the memory-to-memory
  86                                                  data transfer is configured on the selected Channel */
  87
  88   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
  89                                             This parameter can be a value of @ref DMA_Priority_level */
  90
  91 } DMA_InitTypeDef;
  92
  93 /**
  94   * @brief DMA Configuration enumeration values definition
  95   */
  96 typedef enum
  97 {
  98   DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
  99   DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
 100
 101 } DMA_ControlTypeDef;
 102
 103 /**
 104   * @brief  HAL DMA State structures definition
 105   */
 106 typedef enum
 107 {
 108   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
 109   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use   */
 110   HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
 111   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
 112   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
 113   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
 114
 115 }HAL_DMA_StateTypeDef;
 116
 117 /**
 118   * @brief  HAL DMA Error Code structure definition
 119   */
 120 typedef enum
 121 {
 122   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
 123   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
 124
 125 }HAL_DMA_LevelCompleteTypeDef;
 126
 127
 128 /**
 129   * @brief  DMA handle Structure definition
 130   */
 131 typedef struct __DMA_HandleTypeDef
 132 {
 133   DMA_Channel_TypeDef    *Instance;                       /*!< Register base address                  */
 134
 135   DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */
 136
 137   HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */
 138
 139   HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
 140
 141   void                  *Parent;                                                      /*!< Parent object state                    */
 142
 143   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 144
 145   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 146
 147   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 148
 149   __IO uint32_t              ErrorCode;                                               /*!< DMA Error code                         */
 150
 151 } DMA_HandleTypeDef;
 152 /**
 153   * @}
 154   */
 155
 156
 157
 158 /* Exported constants --------------------------------------------------------*/
 159
 160 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 161   * @{
 162   */
 163
 164 /** @defgroup DMA_Error_Code DMA_Error_Code
 165   * @{
 166   */
 167 #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
 168 #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
 169 #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
 170 /**
 171   * @}
 172   */
 173
 174
 175 /** @defgroup DMA_Data_transfer_direction DMA_Data_transfer_direction
 176   * @{
 177   */
 178 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
 179 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
 180 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction     */
 181
 182 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 183                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 184                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 185 /**
 186   * @}
 187   */
 188
 189 /** @defgroup DMA_Data_buffer_size DMA_Data_buffer_size
 190   * @{
 191   */
 192 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 193 /**
 194   * @}
 195   */
 196
 197 /** @defgroup DMA_Peripheral_incremented_mode DMA_Peripheral_incremented_mode
 198   * @{
 199   */
 200 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
 201 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
 202
 203 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 204                                             ((STATE) == DMA_PINC_DISABLE))
 205 /**
 206   * @}
 207   */
 208
 209 /** @defgroup DMA_Memory_incremented_mode DMA_Memory_incremented_mode
 210   * @{
 211   */
 212 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
 213 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
 214
 215 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 216                                         ((STATE) == DMA_MINC_DISABLE))
 217 /**
 218   * @}
 219   */
 220
 221 /** @defgroup DMA_Peripheral_data_size DMA_Peripheral_data_size
 222   * @{
 223   */
 224 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
 225 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
 226 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
 227
 228 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 229                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 230                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 231 /**
 232   * @}
 233   */
 234
 235
 236 /** @defgroup DMA_Memory_data_size DMA_Memory_data_size
 237   * @{
 238   */
 239 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
 240 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
 241 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
 242
 243 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 244                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 245                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 246 /**
 247   * @}
 248   */
 249
 250 /** @defgroup DMA_mode DMA_mode
 251   * @{
 252   */
 253 #define DMA_NORMAL         ((uint32_t)0x00000000)      /*!< Normal Mode                  */
 254 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
 255
 256 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 257                            ((MODE) == DMA_CIRCULAR))
 258 /**
 259   * @}
 260   */
 261
 262 /** @defgroup DMA_Priority_level DMA_Priority_level
 263   * @{
 264   */
 265 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
 266 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
 267 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
 268 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
 269
 270 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 271                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 272                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 273                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 274 /**
 275   * @}
 276   */
 277
 278
 279 /** @defgroup DMA_interrupt_enable_definitions DMA_interrupt_enable_definitions
 280   * @{
 281   */
 282
 283 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
 284 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
 285 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
 286
 287 /**
 288   * @}
 289   */
 290
 291 /** @defgroup DMA_flag_definitions DMA_flag_definitions
 292   * @{
 293   */
 294
 295 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
 296 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
 297 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
 298 #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
 299 #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
 300 #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
 301 #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
 302 #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
 303 #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
 304 #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
 305 #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
 306 #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
 307 #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
 308 #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
 309 #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
 310 #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
 311 #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
 312 #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
 313 #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
 314 #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
 315 #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
 316 #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
 317 #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
 318 #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
 319 #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
 320 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
 321 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
 322 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
 323
 324
 325 /**
 326   * @}
 327   */
 328
 329 /**
 330   * @}
 331   */
 332
 333 /* Exported macros -----------------------------------------------------------*/
 334 /** @defgroup DMA_Exported_macros DMA Exported Macros
 335   * @{
 336   */
 337
 338 /** @brief  Reset DMA handle state
 339   * @param  __HANDLE__: DMA handle.
 340   * @retval None
 341   */
 342 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 343
 344 /**
 345   * @brief  Enable the specified DMA Channel.
 346   * @param  __HANDLE__: DMA handle
 347   * @retval None.
 348   */
 349 #define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
 350
 351 /**
 352   * @brief  Disable the specified DMA Channel.
 353   * @param  __HANDLE__: DMA handle
 354   * @retval None.
 355   */
 356 #define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
 357
 358
 359 /* Interrupt & Flag management */
 360
 361 /**
 362   * @brief  Enables the specified DMA Channel interrupts.
 363   * @param  __HANDLE__: DMA handle
 364   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 365   *          This parameter can be any combination of the following values:
 366   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 367   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 368   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 369   * @retval None
 370   */
 371 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
 372
 373 /**
 374   * @brief  Disables the specified DMA Channel interrupts.
 375   * @param  __HANDLE__: DMA handle
 376   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 377   *          This parameter can be any combination of the following values:
 378   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 379   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 380   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 381   * @retval None
 382   */
 383 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
 384
 385 /**
 386   * @brief  Checks whether the specified DMA Channel interrupt has occurred or not.
 387   * @param  __HANDLE__: DMA handle
 388   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 389   *          This parameter can be one of the following values:
 390   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 391   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 392   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 393   * @retval The state of DMA_IT (SET or RESET).
 394   */
 395 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 396
 397 /**
 398   * @}
 399   */
 400
 401
 402 /* Include DMA HAL Extension module */
 403 #include "stm32l1xx_hal_dma_ex.h"
 404
 405 /* Exported functions --------------------------------------------------------*/
 406 /** @addtogroup DMA_Exported_Functions
 407   * @{
 408   */
 409
 410
 411 /* Initialization and de-initialization functions *****************************/
 412 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 413 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
 414
 415 /* IO operation functions *****************************************************/
 416 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 417 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 418 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 419 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 420 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 421
 422 /* Peripheral State and Error functions ***************************************/
 423 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 424 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 425 /**
 426   * @}
 427   */
 428
 429
 430 /**
 431   * @}
 432   */
 433
 434 /**
 435   * @}
 436   */
 437
 438 #ifdef __cplusplus
 439 }
 440 #endif
 441
 442 #endif /* __STM32L1xx_HAL_DMA_H */
 443
 444 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/