tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32l1xx_hal_nor.c
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    5-September-2014
   7   * @brief   NOR HAL module driver.
   8   *          This file provides a generic firmware to drive NOR memories mounted
   9   *          as external device.
  10   *
  11   @verbatim
  12   ==============================================================================
  13                      ##### How to use this driver #####
  14   ==============================================================================
  15     [..]
  16       This driver is a generic layered driver which contains a set of APIs used to
  17       control NOR flash memories. It uses the FSMC layer functions to interface
  18       with NOR devices. This driver is used as follows:
  19
  20       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
  21           with control and timing parameters for both normal and extended mode.
  22
  23       (+) Read NOR flash memory manufacturer code and device IDs using the function
  24           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
  25           structure declared by the function caller.
  26
  27       (+) Access NOR flash memory by read/write data unit operations using the functions
  28           HAL_NOR_Read(), HAL_NOR_Program().
  29
  30       (+) Perform NOR flash erase block/chip operations using the functions
  31           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
  32
  33       (+) Read the NOR flash CFI (common flash interface) IDs using the function
  34           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
  35           structure declared by the function caller.
  36
  37       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
  38           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
  39
  40       (+) You can monitor the NOR device HAL state by calling the function
  41           HAL_NOR_GetState()
  42     [..]
  43      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
  44          If a NOR flash device contains different operations and/or implementations,
  45          it should be implemented separately.
  46
  47      *** NOR HAL driver macros list ***
  48      =============================================
  49      [..]
  50        Below the list of most used macros in NOR HAL driver.
  51
  52       (+) __NOR_WRITE : NOR memory write data to specified address
  53
  54   @endverbatim
  55   ******************************************************************************
  56   * @attention
  57   *
  58   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  59   *
  60   * Redistribution and use in source and binary forms, with or without modification,
  61   * are permitted provided that the following conditions are met:
  62   *   1. Redistributions of source code must retain the above copyright notice,
  63   *      this list of conditions and the following disclaimer.
  64   *   2. Redistributions in binary form must reproduce the above copyright notice,
  65   *      this list of conditions and the following disclaimer in the documentation
  66   *      and/or other materials provided with the distribution.
  67   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  68   *      may be used to endorse or promote products derived from this software
  69   *      without specific prior written permission.
  70   *
  71   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  72   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  73   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  74   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  75   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  76   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  77   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  78   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  79   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  80   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  81   *
  82   ******************************************************************************
  83   */
  84
  85 /* Includes ------------------------------------------------------------------*/
  86 #include "stm32l1xx_hal.h"
  87
  88 /** @addtogroup STM32L1xx_HAL_Driver
  89   * @{
  90   */
  91
  92 /** @defgroup NOR NOR
  93   * @brief NOR driver modules
  94   * @{
  95   */
  96 #ifdef HAL_NOR_MODULE_ENABLED
  97 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
  98
  99 /* Private typedef -----------------------------------------------------------*/
 100 /* Private define ------------------------------------------------------------*/
 101 /* Private macro -------------------------------------------------------------*/
 102 /* Private variables ---------------------------------------------------------*/
 103
 104 /** @defgroup NOR_Private_Variables NOR Private Variables
 105   * @{
 106   */
 107
 108 static uint32_t uwNORAddress            = NOR_MEMORY_ADRESS1;
 109 static uint32_t uwNORMememoryDataWidth  = NOR_MEMORY_8B;
 110
 111 /**
 112   * @}
 113   */
 114
 115 /* Private function prototypes -----------------------------------------------*/
 116 /* Private functions ---------------------------------------------------------*/
 117
 118 /** @defgroup NOR_Exported_Functions NOR Exported Functions
 119   * @{
 120   */
 121
 122 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
 123   * @brief    Initialization and Configuration functions
 124   *
 125   @verbatim
 126   ==============================================================================
 127            ##### NOR Initialization and de_initialization functions #####
 128   ==============================================================================
 129   [..]
 130     This section provides functions allowing to initialize/de-initialize
 131     the NOR memory
 132
 133 @endverbatim
 134   * @{
 135   */
 136
 137 /**
 138   * @brief  Perform the NOR memory Initialization sequence
 139   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 140   *                the configuration information for NOR module.
 141   * @param  Timing: pointer to NOR control timing structure
 142   * @param  ExtTiming: pointer to NOR extended mode timing structure
 143   * @retval HAL status
 144   */
 145 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
 146 {
 147   /* Check the NOR handle parameter */
 148   if(hnor == HAL_NULL)
 149   {
 150      return HAL_ERROR;
 151   }
 152
 153   if(hnor->State == HAL_NOR_STATE_RESET)
 154   {
 155     /* Initialize the low level hardware (MSP) */
 156     HAL_NOR_MspInit(hnor);
 157   }
 158
 159   /* Initialize NOR control Interface */
 160   FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
 161
 162   /* Initialize NOR timing Interface */
 163   FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
 164
 165   /* Initialize NOR extended mode timing Interface */
 166   FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
 167
 168   /* Enable the NORSRAM device */
 169   __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
 170
 171   /* Initialize NOR address mapped by FSMC */
 172   if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM1)
 173   {
 174     uwNORAddress = NOR_MEMORY_ADRESS1;
 175   }
 176   else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM2)
 177   {
 178     uwNORAddress = NOR_MEMORY_ADRESS2;
 179   }
 180   else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM3)
 181   {
 182     uwNORAddress = NOR_MEMORY_ADRESS3;
 183   }
 184   else
 185   {
 186     uwNORAddress = NOR_MEMORY_ADRESS4;
 187   }
 188
 189   /* Initialize NOR Memory Data Width*/
 190   if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
 191   {
 192     uwNORMememoryDataWidth = NOR_MEMORY_8B;
 193   }
 194   else
 195   {
 196     uwNORMememoryDataWidth = NOR_MEMORY_16B;
 197   }
 198
 199   /* Check the NOR controller state */
 200   hnor->State = HAL_NOR_STATE_READY;
 201
 202   return HAL_OK;
 203 }
 204
 205 /**
 206   * @brief  Perform NOR memory De-Initialization sequence
 207   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 208   *                the configuration information for NOR module.
 209   * @retval HAL status
 210   */
 211 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
 212 {
 213   /* De-Initialize the low level hardware (MSP) */
 214   HAL_NOR_MspDeInit(hnor);
 215
 216   /* Configure the NOR registers with their reset values */
 217   FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
 218
 219   /* Update the NOR controller state */
 220   hnor->State = HAL_NOR_STATE_RESET;
 221
 222   /* Release Lock */
 223   __HAL_UNLOCK(hnor);
 224
 225   return HAL_OK;
 226 }
 227
 228 /**
 229   * @brief  NOR MSP Init
 230   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 231   *                the configuration information for NOR module.
 232   * @retval None
 233   */
 234 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
 235 {
 236   /* NOTE : This function Should not be modified, when the callback is needed,
 237             the HAL_NOR_MspInit could be implemented in the user file
 238    */
 239 }
 240
 241 /**
 242   * @brief  NOR MSP DeInit
 243   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 244   *                the configuration information for NOR module.
 245   * @retval None
 246   */
 247 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
 248 {
 249   /* NOTE : This function Should not be modified, when the callback is needed,
 250             the HAL_NOR_MspDeInit could be implemented in the user file
 251    */
 252 }
 253
 254 /**
 255   * @brief  NOR BSP Wait fro Ready/Busy signal
 256   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 257   *                the configuration information for NOR module.
 258   * @param  Timeout: Maximum timeout value
 259   * @retval None
 260   */
 261 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
 262 {
 263   /* NOTE : This function Should not be modified, when the callback is needed,
 264             the HAL_NOR_BspWait could be implemented in the user file
 265    */
 266 }
 267
 268 /**
 269   * @}
 270   */
 271
 272 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
 273   * @brief    Input Output and memory control functions
 274   *
 275   @verbatim
 276   ==============================================================================
 277                 ##### NOR Input and Output functions #####
 278   ==============================================================================
 279   [..]
 280     This section provides functions allowing to use and control the NOR memory
 281
 282 @endverbatim
 283   * @{
 284   */
 285
 286 /**
 287   * @brief  Read NOR flash IDs
 288   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 289   *                the configuration information for NOR module.
 290   * @param  pNOR_ID : pointer to NOR ID structure
 291   * @retval HAL status
 292   */
 293 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
 294 {
 295   /* Process Locked */
 296   __HAL_LOCK(hnor);
 297
 298   /* Check the NOR controller state */
 299   if(hnor->State == HAL_NOR_STATE_BUSY)
 300   {
 301      return HAL_BUSY;
 302   }
 303
 304   /* Update the NOR controller state */
 305   hnor->State = HAL_NOR_STATE_BUSY;
 306
 307   /* Send read ID command */
 308   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
 309   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
 310   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0090);
 311
 312   /* Read the NOR IDs */
 313   pNOR_ID->ManufacturerCode = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, MC_ADDRESS);
 314   pNOR_ID->DeviceCode1      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE1_ADDR);
 315   pNOR_ID->DeviceCode2      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE2_ADDR);
 316   pNOR_ID->DeviceCode3      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE3_ADDR);
 317
 318   /* Check the NOR controller state */
 319   hnor->State = HAL_NOR_STATE_READY;
 320
 321   /* Process unlocked */
 322   __HAL_UNLOCK(hnor);
 323
 324   return HAL_OK;
 325 }
 326
 327 /**
 328   * @brief  Returns the NOR memory to Read mode.
 329   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 330   *                the configuration information for NOR module.
 331   * @retval HAL status
 332   */
 333 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
 334 {
 335   /* Process Locked */
 336   __HAL_LOCK(hnor);
 337
 338   /* Check the NOR controller state */
 339   if(hnor->State == HAL_NOR_STATE_BUSY)
 340   {
 341      return HAL_BUSY;
 342   }
 343
 344   __NOR_WRITE(uwNORAddress, 0x00F0);
 345
 346   /* Check the NOR controller state */
 347   hnor->State = HAL_NOR_STATE_READY;
 348
 349   /* Process unlocked */
 350   __HAL_UNLOCK(hnor);
 351
 352   return HAL_OK;
 353 }
 354
 355 /**
 356   * @brief  Read data from NOR memory
 357   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 358   *                the configuration information for NOR module.
 359   * @param  pAddress: pointer to Device address
 360   * @param  pData : pointer to read data
 361   * @retval HAL status
 362   */
 363 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
 364 {
 365   /* Process Locked */
 366   __HAL_LOCK(hnor);
 367
 368   /* Check the NOR controller state */
 369   if(hnor->State == HAL_NOR_STATE_BUSY)
 370   {
 371      return HAL_BUSY;
 372   }
 373
 374   /* Update the NOR controller state */
 375   hnor->State = HAL_NOR_STATE_BUSY;
 376
 377   /* Send read data command */
 378   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA);
 379   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055);
 380   __NOR_WRITE(*pAddress, 0x00F0);
 381
 382   /* Read the data */
 383   *pData = *(__IO uint32_t *)pAddress;
 384
 385   /* Check the NOR controller state */
 386   hnor->State = HAL_NOR_STATE_READY;
 387
 388   /* Process unlocked */
 389   __HAL_UNLOCK(hnor);
 390
 391   return HAL_OK;
 392 }
 393
 394 /**
 395   * @brief  Program data to NOR memory
 396   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 397   *                the configuration information for NOR module.
 398   * @param  pAddress: Device address
 399   * @param  pData : pointer to the data to write
 400   * @retval HAL status
 401   */
 402 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
 403 {
 404   /* Process Locked */
 405   __HAL_LOCK(hnor);
 406
 407   /* Check the NOR controller state */
 408   if(hnor->State == HAL_NOR_STATE_BUSY)
 409   {
 410      return HAL_BUSY;
 411   }
 412
 413   /* Update the NOR controller state */
 414   hnor->State = HAL_NOR_STATE_BUSY;
 415
 416   /* Send program data command */
 417   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
 418   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
 419   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00A0);
 420
 421   /* Write the data */
 422   __NOR_WRITE(pAddress, *pData);
 423
 424   /* Check the NOR controller state */
 425   hnor->State = HAL_NOR_STATE_READY;
 426
 427   /* Process unlocked */
 428   __HAL_UNLOCK(hnor);
 429
 430   return HAL_OK;
 431 }
 432
 433 /**
 434   * @brief  Reads a block of data from the FSMC NOR memory.
 435   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 436   *                the configuration information for NOR module.
 437   * @param  uwAddress: NOR memory internal address to read from.
 438   * @param  pData: pointer to the buffer that receives the data read from the
 439   *         NOR memory.
 440   * @param  uwBufferSize : number of Half word to read.
 441   * @retval HAL status
 442   */
 443 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
 444 {
 445   /* Process Locked */
 446   __HAL_LOCK(hnor);
 447
 448   /* Check the NOR controller state */
 449   if(hnor->State == HAL_NOR_STATE_BUSY)
 450   {
 451      return HAL_BUSY;
 452   }
 453
 454   /* Update the NOR controller state */
 455   hnor->State = HAL_NOR_STATE_BUSY;
 456
 457   /* Send read data command */
 458   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA);
 459   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055);
 460   __NOR_WRITE(uwAddress, 0x00F0);
 461
 462   /* Read buffer */
 463   while( uwBufferSize > 0)
 464   {
 465     *pData++ = *(__IO uint16_t *)uwAddress;
 466     uwAddress += 2;
 467     uwBufferSize--;
 468   }
 469
 470   /* Check the NOR controller state */
 471   hnor->State = HAL_NOR_STATE_READY;
 472
 473   /* Process unlocked */
 474   __HAL_UNLOCK(hnor);
 475
 476   return HAL_OK;
 477 }
 478
 479 /**
 480   * @brief  Writes a half-word buffer to the FSMC NOR memory. This function
 481   *         must be used only with S29GL128P NOR memory.
 482   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 483   *                the configuration information for NOR module.
 484   * @param  uwAddress: NOR memory internal address from which the data
 485   * @param  pData: pointer to source data buffer.
 486   * @param  uwBufferSize: number of Half words to write. The maximum allowed
 487   * @retval HAL status
 488   */
 489 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
 490 {
 491   uint32_t lastloadedaddress = 0;
 492   uint32_t currentaddress = 0;
 493   uint32_t endaddress = 0;
 494
 495   /* Process Locked */
 496   __HAL_LOCK(hnor);
 497
 498   /* Check the NOR controller state */
 499   if(hnor->State == HAL_NOR_STATE_BUSY)
 500   {
 501      return HAL_BUSY;
 502   }
 503
 504   /* Update the NOR controller state */
 505   hnor->State = HAL_NOR_STATE_BUSY;
 506
 507   /* Initialize variables */
 508   currentaddress    = uwAddress;
 509   endaddress        = uwAddress + uwBufferSize - 1;
 510   lastloadedaddress = uwAddress;
 511
 512   /* Issue unlock command sequence */
 513   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
 514   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
 515
 516   /* Write Buffer Load Command */
 517   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), 0x25);
 518   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), (uwBufferSize - 1));
 519
 520   /* Load Data into NOR Buffer */
 521   while(currentaddress <= endaddress)
 522   {
 523     /* Store last loaded address & data value (for polling) */
 524     lastloadedaddress = currentaddress;
 525
 526     __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, currentaddress), *pData++);
 527
 528     currentaddress += 1;
 529   }
 530
 531   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, lastloadedaddress), 0x29);
 532
 533   /* Check the NOR controller state */
 534   hnor->State = HAL_NOR_STATE_READY;
 535
 536   /* Process unlocked */
 537   __HAL_UNLOCK(hnor);
 538
 539   return HAL_OK;
 540
 541 }
 542
 543 /**
 544   * @brief  Erase the specified block of the NOR memory
 545   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 546   *                the configuration information for NOR module.
 547   * @param  BlockAddress : Block to erase address
 548   * @param  Address: Device address
 549   * @retval HAL status
 550   */
 551 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
 552 {
 553   /* Process Locked */
 554   __HAL_LOCK(hnor);
 555
 556   /* Check the NOR controller state */
 557   if(hnor->State == HAL_NOR_STATE_BUSY)
 558   {
 559      return HAL_BUSY;
 560   }
 561
 562   /* Update the NOR controller state */
 563   hnor->State = HAL_NOR_STATE_BUSY;
 564
 565   /* Send block erase command sequence */
 566   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
 567   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
 568   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080);
 569   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
 570   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
 571   __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
 572
 573   /* Check the NOR memory status and update the controller state */
 574   hnor->State = HAL_NOR_STATE_READY;
 575
 576   /* Process unlocked */
 577   __HAL_UNLOCK(hnor);
 578
 579   return HAL_OK;
 580
 581 }
 582
 583 /**
 584   * @brief  Erase the entire NOR chip.
 585   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 586   *                the configuration information for NOR module.
 587   * @param  Address : Device address
 588   * @retval HAL status
 589   */
 590 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
 591 {
 592   /* Process Locked */
 593   __HAL_LOCK(hnor);
 594
 595   /* Check the NOR controller state */
 596   if(hnor->State == HAL_NOR_STATE_BUSY)
 597   {
 598      return HAL_BUSY;
 599   }
 600
 601   /* Update the NOR controller state */
 602   hnor->State = HAL_NOR_STATE_BUSY;
 603
 604   /* Send NOR chip erase command sequence */
 605   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
 606   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
 607   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080);
 608   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
 609   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
 610   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0010);
 611
 612   /* Check the NOR memory status and update the controller state */
 613   hnor->State = HAL_NOR_STATE_READY;
 614
 615   /* Process unlocked */
 616   __HAL_UNLOCK(hnor);
 617
 618   return HAL_OK;
 619 }
 620
 621 /**
 622   * @brief  Read NOR flash CFI IDs
 623   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 624   *                the configuration information for NOR module.
 625   * @param  pNOR_CFI : pointer to NOR CFI IDs structure
 626   * @retval HAL status
 627   */
 628 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
 629 {
 630   /* Process Locked */
 631   __HAL_LOCK(hnor);
 632
 633   /* Check the NOR controller state */
 634   if(hnor->State == HAL_NOR_STATE_BUSY)
 635   {
 636      return HAL_BUSY;
 637   }
 638
 639   /* Update the NOR controller state */
 640   hnor->State = HAL_NOR_STATE_BUSY;
 641
 642   /* Send read CFI query command */
 643   __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0055), 0x0098);
 644
 645   /* read the NOR CFI information */
 646   pNOR_CFI->CFI1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI1_ADDRESS);
 647   pNOR_CFI->CFI2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI2_ADDRESS);
 648   pNOR_CFI->CFI3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI3_ADDRESS);
 649   pNOR_CFI->CFI4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI4_ADDRESS);
 650
 651   /* Check the NOR controller state */
 652   hnor->State = HAL_NOR_STATE_READY;
 653
 654   /* Process unlocked */
 655   __HAL_UNLOCK(hnor);
 656
 657   return HAL_OK;
 658 }
 659
 660 /**
 661   * @}
 662   */
 663
 664 /** @defgroup NOR_Exported_Functions_Group3 Control functions
 665  *  @brief   management functions
 666  *
 667 @verbatim
 668   ==============================================================================
 669                         ##### NOR Control functions #####
 670   ==============================================================================
 671   [..]
 672     This subsection provides a set of functions allowing to control dynamically
 673     the NOR interface.
 674
 675 @endverbatim
 676   * @{
 677   */
 678
 679 /**
 680   * @brief  Enables dynamically NOR write operation.
 681   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 682   *                the configuration information for NOR module.
 683   * @retval HAL status
 684   */
 685 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
 686 {
 687   /* Process Locked */
 688   __HAL_LOCK(hnor);
 689
 690   /* Enable write operation */
 691   FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
 692
 693   /* Update the NOR controller state */
 694   hnor->State = HAL_NOR_STATE_READY;
 695
 696   /* Process unlocked */
 697   __HAL_UNLOCK(hnor);
 698
 699   return HAL_OK;
 700 }
 701
 702 /**
 703   * @brief  Disables dynamically NOR write operation.
 704   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 705   *                the configuration information for NOR module.
 706   * @retval HAL status
 707   */
 708 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
 709 {
 710   /* Process Locked */
 711   __HAL_LOCK(hnor);
 712
 713   /* Update the SRAM controller state */
 714   hnor->State = HAL_NOR_STATE_BUSY;
 715
 716   /* Disable write operation */
 717   FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
 718
 719   /* Update the NOR controller state */
 720   hnor->State = HAL_NOR_STATE_PROTECTED;
 721
 722   /* Process unlocked */
 723   __HAL_UNLOCK(hnor);
 724
 725   return HAL_OK;
 726 }
 727
 728 /**
 729   * @}
 730   */
 731
 732 /** @defgroup NOR_Exported_Functions_Group4 State functions
 733  *  @brief   Peripheral State functions
 734  *
 735 @verbatim
 736   ==============================================================================
 737                       ##### NOR State functions #####
 738   ==============================================================================
 739   [..]
 740     This subsection permits to get in run-time the status of the NOR controller
 741     and the data flow.
 742
 743 @endverbatim
 744   * @{
 745   */
 746
 747 /**
 748   * @brief  return the NOR controller state
 749   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 750   *                the configuration information for NOR module.
 751   * @retval NOR controller state
 752   */
 753 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
 754 {
 755   return hnor->State;
 756 }
 757
 758 /**
 759   * @brief  Returns the NOR operation status.
 760   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
 761   *                the configuration information for NOR module.
 762   * @param  Address: Device address
 763   * @param  Timeout: NOR progamming Timeout
 764   * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
 765   *         or NOR_TIMEOUT
 766   */
 767 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
 768 {
 769   NOR_StatusTypedef status = NOR_ONGOING;
 770   uint16_t tmpSR1 = 0, tmpSR2 = 0;
 771   uint32_t tickstart = 0;
 772
 773   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
 774   HAL_NOR_MspWait(hnor, Timeout);
 775
 776   /* Get the NOR memory operation status -------------------------------------*/
 777   while(status != NOR_TIMEOUT)
 778   {
 779     /* Get tick */
 780     tickstart = HAL_GetTick();
 781
 782     if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
 783     {
 784       status = NOR_TIMEOUT;
 785     }
 786
 787     /* Read NOR status register (DQ6 and DQ5) */
 788     tmpSR1 = *(__IO uint16_t *)Address;
 789     tmpSR2 = *(__IO uint16_t *)Address;
 790
 791     /* If DQ6 did not toggle between the two reads then return NOR_Success */
 792     if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
 793     {
 794       return NOR_SUCCESS;
 795     }
 796
 797     if((tmpSR1 & 0x0020) == 0x0020)
 798     {
 799       return NOR_ONGOING;
 800     }
 801
 802     tmpSR1 = *(__IO uint16_t *)Address;
 803     tmpSR2 = *(__IO uint16_t *)Address;
 804
 805     /* If DQ6 did not toggle between the two reads then return NOR_Success */
 806     if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
 807     {
 808       return NOR_SUCCESS;
 809     }
 810
 811     if((tmpSR1 & 0x0020) == 0x0020)
 812     {
 813       return NOR_ERROR;
 814     }
 815   }
 816
 817   /* Return the operation status */
 818   return status;
 819 }
 820
 821 /**
 822   * @}
 823   */
 824
 825 /**
 826   * @}
 827   */
 828 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 829 #endif /* HAL_NOR_MODULE_ENABLED */
 830 /**
 831   * @}
 832   */
 833
 834 /**
 835   * @}
 836   */
 837
 838 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/