tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/core_ca_mmu.h

   1 ;/**************************************************************************//**
   2 ; * @file     core_ca_mmu.h
   3 ; * @brief    MMU Startup File for
   4 ; *           VE_A9_MP Device Series
   5 ; * @version  V1.01
   6 ; * @date     25 March 2013
   7 ; *
   8 ; * @note
   9 ; *
  10 ; ******************************************************************************/
  11 ;/* Copyright (c) 2012 ARM LIMITED
  12 ;
  13 ;   All rights reserved.
  14 ;   Redistribution and use in source and binary forms, with or without
  15 ;   modification, are permitted provided that the following conditions are met:
  16 ;   - Redistributions of source code must retain the above copyright
  17 ;     notice, this list of conditions and the following disclaimer.
  18 ;   - Redistributions in binary form must reproduce the above copyright
  19 ;     notice, this list of conditions and the following disclaimer in the
  20 ;     documentation and/or other materials provided with the distribution.
  21 ;   - Neither the name of ARM nor the names of its contributors may be used
  22 ;     to endorse or promote products derived from this software without
  23 ;     specific prior written permission.
  24 ;   *
  25 ;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26 ;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27 ;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28 ;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  29 ;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30 ;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31 ;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32 ;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33 ;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34 ;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35 ;   POSSIBILITY OF SUCH DAMAGE.
  36 ;   ---------------------------------------------------------------------------*/
  37
  38 #ifdef __cplusplus
  39  extern "C" {
  40 #endif
  41
  42 #ifndef _MMU_FUNC_H
  43 #define _MMU_FUNC_H
  44
  45 #define SECTION_DESCRIPTOR      (0x2)
  46 #define SECTION_MASK            (0xFFFFFFFC)
  47
  48 #define SECTION_TEXCB_MASK      (0xFFFF8FF3)
  49 #define SECTION_B_SHIFT         (2)
  50 #define SECTION_C_SHIFT         (3)
  51 #define SECTION_TEX0_SHIFT      (12)
  52 #define SECTION_TEX1_SHIFT      (13)
  53 #define SECTION_TEX2_SHIFT      (14)
  54
  55 #define SECTION_XN_MASK         (0xFFFFFFEF)
  56 #define SECTION_XN_SHIFT        (4)
  57
  58 #define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
  59 #define SECTION_DOMAIN_SHIFT    (5)
  60
  61 #define SECTION_P_MASK          (0xFFFFFDFF)
  62 #define SECTION_P_SHIFT         (9)
  63
  64 #define SECTION_AP_MASK         (0xFFFF73FF)
  65 #define SECTION_AP_SHIFT        (10)
  66 #define SECTION_AP2_SHIFT       (15)
  67
  68 #define SECTION_S_MASK          (0xFFFEFFFF)
  69 #define SECTION_S_SHIFT         (16)
  70
  71 #define SECTION_NG_MASK         (0xFFFDFFFF)
  72 #define SECTION_NG_SHIFT        (17)
  73
  74 #define SECTION_NS_MASK         (0xFFF7FFFF)
  75 #define SECTION_NS_SHIFT        (19)
  76
  77
  78 #define PAGE_L1_DESCRIPTOR      (0x1)
  79 #define PAGE_L1_MASK            (0xFFFFFFFC)
  80
  81 #define PAGE_L2_4K_DESC         (0x2)
  82 #define PAGE_L2_4K_MASK         (0xFFFFFFFD)
  83
  84 #define PAGE_L2_64K_DESC        (0x1)
  85 #define PAGE_L2_64K_MASK        (0xFFFFFFFC)
  86
  87 #define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
  88 #define PAGE_4K_B_SHIFT         (2)
  89 #define PAGE_4K_C_SHIFT         (3)
  90 #define PAGE_4K_TEX0_SHIFT      (6)
  91 #define PAGE_4K_TEX1_SHIFT      (7)
  92 #define PAGE_4K_TEX2_SHIFT      (8)
  93
  94 #define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
  95 #define PAGE_64K_B_SHIFT        (2)
  96 #define PAGE_64K_C_SHIFT        (3)
  97 #define PAGE_64K_TEX0_SHIFT     (12)
  98 #define PAGE_64K_TEX1_SHIFT     (13)
  99 #define PAGE_64K_TEX2_SHIFT     (14)
 100
 101 #define PAGE_TEXCB_MASK         (0xFFFF8FF3)
 102 #define PAGE_B_SHIFT            (2)
 103 #define PAGE_C_SHIFT            (3)
 104 #define PAGE_TEX_SHIFT          (12)
 105
 106 #define PAGE_XN_4K_MASK         (0xFFFFFFFE)
 107 #define PAGE_XN_4K_SHIFT        (0)
 108 #define PAGE_XN_64K_MASK        (0xFFFF7FFF)
 109 #define PAGE_XN_64K_SHIFT       (15)
 110
 111
 112 #define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
 113 #define PAGE_DOMAIN_SHIFT       (5)
 114
 115 #define PAGE_P_MASK             (0xFFFFFDFF)
 116 #define PAGE_P_SHIFT            (9)
 117
 118 #define PAGE_AP_MASK            (0xFFFFFDCF)
 119 #define PAGE_AP_SHIFT           (4)
 120 #define PAGE_AP2_SHIFT          (9)
 121
 122 #define PAGE_S_MASK             (0xFFFFFBFF)
 123 #define PAGE_S_SHIFT            (10)
 124
 125 #define PAGE_NG_MASK            (0xFFFFF7FF)
 126 #define PAGE_NG_SHIFT           (11)
 127
 128 #define PAGE_NS_MASK            (0xFFFFFFF7)
 129 #define PAGE_NS_SHIFT           (3)
 130
 131 #define OFFSET_1M               (0x00100000)
 132 #define OFFSET_64K              (0x00010000)
 133 #define OFFSET_4K               (0x00001000)
 134
 135 #define DESCRIPTOR_FAULT        (0x00000000)
 136
 137 /* ###########################  MMU Function Access  ########################### */
 138 /** \ingroup  MMU_FunctionInterface
 139     \defgroup MMU_Functions MMU Functions Interface
 140   @{
 141  */
 142
 143 /* Attributes enumerations */
 144
 145 /* Region size attributes */
 146 typedef enum
 147 {
 148    SECTION,
 149    PAGE_4k,
 150    PAGE_64k,
 151 } mmu_region_size_Type;
 152
 153 /* Region type attributes */
 154 typedef enum
 155 {
 156    NORMAL,
 157    DEVICE,
 158    SHARED_DEVICE,
 159    NON_SHARED_DEVICE,
 160    STRONGLY_ORDERED
 161 } mmu_memory_Type;
 162
 163 /* Region cacheability attributes */
 164 typedef enum
 165 {
 166    NON_CACHEABLE,
 167    WB_WA,
 168    WT,
 169    WB_NO_WA,
 170 } mmu_cacheability_Type;
 171
 172 /* Region parity check attributes */
 173 typedef enum
 174 {
 175    ECC_DISABLED,
 176    ECC_ENABLED,
 177 } mmu_ecc_check_Type;
 178
 179 /* Region execution attributes */
 180 typedef enum
 181 {
 182    EXECUTE,
 183    NON_EXECUTE,
 184 } mmu_execute_Type;
 185
 186 /* Region global attributes */
 187 typedef enum
 188 {
 189    GLOBAL,
 190    NON_GLOBAL,
 191 } mmu_global_Type;
 192
 193 /* Region shareability attributes */
 194 typedef enum
 195 {
 196    NON_SHARED,
 197    SHARED,
 198 } mmu_shared_Type;
 199
 200 /* Region security attributes */
 201 typedef enum
 202 {
 203    SECURE,
 204    NON_SECURE,
 205 } mmu_secure_Type;
 206
 207 /* Region access attributes */
 208 typedef enum
 209 {
 210    NO_ACCESS,
 211    RW,
 212    READ,
 213 } mmu_access_Type;
 214
 215 /* Memory Region definition */
 216 typedef struct RegionStruct {
 217     mmu_region_size_Type rg_t;
 218     mmu_memory_Type mem_t;
 219     uint8_t domain;
 220     mmu_cacheability_Type inner_norm_t;
 221     mmu_cacheability_Type outer_norm_t;
 222     mmu_ecc_check_Type e_t;
 223     mmu_execute_Type xn_t;
 224     mmu_global_Type g_t;
 225     mmu_secure_Type sec_t;
 226     mmu_access_Type priv_t;
 227     mmu_access_Type user_t;
 228     mmu_shared_Type sh_t;
 229
 230 } mmu_region_attributes_Type;
 231
 232 /** \brief  Set section execution-never attribute
 233
 234     The function sets section execution-never attribute
 235
 236     \param [out]    descriptor_l1  L1 descriptor.
 237     \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
 238
 239     \return          0
 240  */
 241 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
 242 {
 243     *descriptor_l1 &= SECTION_XN_MASK;
 244     *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
 245     return 0;
 246 }
 247
 248 /** \brief  Set section domain
 249
 250     The function sets section domain
 251
 252     \param [out]    descriptor_l1  L1 descriptor.
 253     \param [in]            domain  Section domain
 254
 255     \return          0
 256  */
 257 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
 258 {
 259     *descriptor_l1 &= SECTION_DOMAIN_MASK;
 260     *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
 261     return 0;
 262 }
 263
 264 /** \brief  Set section parity check
 265
 266     The function sets section parity check
 267
 268     \param [out]    descriptor_l1  L1 descriptor.
 269     \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
 270
 271     \return          0
 272  */
 273 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 274 {
 275     *descriptor_l1 &= SECTION_P_MASK;
 276     *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
 277     return 0;
 278 }
 279
 280 /** \brief  Set section access privileges
 281
 282     The function sets section access privileges
 283
 284     \param [out]    descriptor_l1  L1 descriptor.
 285     \param [in]              user  User Level Access: NO_ACCESS, RW, READ
 286     \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
 287     \param [in]               afe  Access flag enable
 288
 289     \return          0
 290  */
 291 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
 292 {
 293     uint32_t ap = 0;
 294
 295     if (afe == 0) { //full access
 296         if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
 297         else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
 298         else if ((priv == RW) && (user == READ))        { ap = 0x2; }
 299         else if ((priv == RW) && (user == RW))          { ap = 0x3; }
 300         else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
 301         else if ((priv == READ) && (user == READ))      { ap = 0x6; }
 302     }
 303
 304     else { //Simplified access
 305         if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
 306         else if ((priv == RW) && (user == RW))          { ap = 0x3; }
 307         else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
 308         else if ((priv == READ) && (user == READ))      { ap = 0x7; }
 309     }
 310
 311     *descriptor_l1 &= SECTION_AP_MASK;
 312     *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
 313     *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
 314
 315     return 0;
 316 }
 317
 318 /** \brief  Set section shareability
 319
 320     The function sets section shareability
 321
 322     \param [out]    descriptor_l1  L1 descriptor.
 323     \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
 324
 325     \return          0
 326  */
 327 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
 328 {
 329     *descriptor_l1 &= SECTION_S_MASK;
 330     *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
 331     return 0;
 332 }
 333
 334 /** \brief  Set section Global attribute
 335
 336     The function sets section Global attribute
 337
 338     \param [out]    descriptor_l1  L1 descriptor.
 339     \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
 340
 341     \return          0
 342  */
 343 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
 344 {
 345     *descriptor_l1 &= SECTION_NG_MASK;
 346     *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
 347     return 0;
 348 }
 349
 350 /** \brief  Set section Security attribute
 351
 352     The function sets section Global attribute
 353
 354     \param [out]    descriptor_l1  L1 descriptor.
 355     \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
 356
 357     \return          0
 358  */
 359 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 360 {
 361     *descriptor_l1 &= SECTION_NS_MASK;
 362     *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
 363     return 0;
 364 }
 365
 366 /* Page 4k or 64k */
 367 /** \brief  Set 4k/64k page execution-never attribute
 368
 369     The function sets 4k/64k page execution-never attribute
 370
 371     \param [out]    descriptor_l2  L2 descriptor.
 372     \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
 373     \param [in]              page  Page size: PAGE_4k, PAGE_64k,
 374
 375     \return          0
 376  */
 377 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
 378 {
 379     if (page == PAGE_4k)
 380     {
 381         *descriptor_l2 &= PAGE_XN_4K_MASK;
 382         *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
 383     }
 384     else
 385     {
 386         *descriptor_l2 &= PAGE_XN_64K_MASK;
 387         *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
 388     }
 389     return 0;
 390 }
 391
 392 /** \brief  Set 4k/64k page domain
 393
 394     The function sets 4k/64k page domain
 395
 396     \param [out]    descriptor_l1  L1 descriptor.
 397     \param [in]            domain  Page domain
 398
 399     \return          0
 400  */
 401 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
 402 {
 403     *descriptor_l1 &= PAGE_DOMAIN_MASK;
 404     *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
 405     return 0;
 406 }
 407
 408 /** \brief  Set 4k/64k page parity check
 409
 410     The function sets 4k/64k page parity check
 411
 412     \param [out]    descriptor_l1  L1 descriptor.
 413     \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
 414
 415     \return          0
 416  */
 417 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 418 {
 419     *descriptor_l1 &= SECTION_P_MASK;
 420     *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
 421     return 0;
 422 }
 423
 424 /** \brief  Set 4k/64k page access privileges
 425
 426     The function sets 4k/64k page access privileges
 427
 428     \param [out]    descriptor_l2  L2 descriptor.
 429     \param [in]              user  User Level Access: NO_ACCESS, RW, READ
 430     \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
 431     \param [in]               afe  Access flag enable
 432
 433     \return          0
 434  */
 435 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
 436 {
 437     uint32_t ap = 0;
 438
 439     if (afe == 0) { //full access
 440         if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
 441         else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
 442         else if ((priv == RW) && (user == READ))        { ap = 0x2; }
 443         else if ((priv == RW) && (user == RW))          { ap = 0x3; }
 444         else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
 445         else if ((priv == READ) && (user == READ))      { ap = 0x6; }
 446     }
 447
 448     else { //Simplified access
 449         if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
 450         else if ((priv == RW) && (user == RW))          { ap = 0x3; }
 451         else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
 452         else if ((priv == READ) && (user == READ))      { ap = 0x7; }
 453     }
 454
 455     *descriptor_l2 &= PAGE_AP_MASK;
 456     *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
 457     *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
 458
 459     return 0;
 460 }
 461
 462 /** \brief  Set 4k/64k page shareability
 463
 464     The function sets 4k/64k page shareability
 465
 466     \param [out]    descriptor_l2  L2 descriptor.
 467     \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
 468
 469     \return          0
 470  */
 471 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
 472 {
 473     *descriptor_l2 &= PAGE_S_MASK;
 474     *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
 475     return 0;
 476 }
 477
 478 /** \brief  Set 4k/64k page Global attribute
 479
 480     The function sets 4k/64k page Global attribute
 481
 482     \param [out]    descriptor_l2  L2 descriptor.
 483     \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
 484
 485     \return          0
 486  */
 487 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
 488 {
 489     *descriptor_l2 &= PAGE_NG_MASK;
 490     *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
 491     return 0;
 492 }
 493
 494 /** \brief  Set 4k/64k page Security attribute
 495
 496     The function sets 4k/64k page Global attribute
 497
 498     \param [out]    descriptor_l1  L1 descriptor.
 499     \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
 500
 501     \return          0
 502  */
 503 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 504 {
 505     *descriptor_l1 &= PAGE_NS_MASK;
 506     *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
 507     return 0;
 508 }
 509
 510
 511 /** \brief  Set Section memory attributes
 512
 513     The function sets section memory attributes
 514
 515     \param [out]    descriptor_l1  L1 descriptor.
 516     \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
 517     \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
 518     \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
 519
 520     \return          0
 521  */
 522 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
 523 {
 524     *descriptor_l1 &= SECTION_TEXCB_MASK;
 525
 526     if (STRONGLY_ORDERED == mem)
 527     {
 528         return 0;
 529     }
 530     else if (SHARED_DEVICE == mem)
 531     {
 532         *descriptor_l1 |= (1 << SECTION_B_SHIFT);
 533     }
 534     else if (NON_SHARED_DEVICE == mem)
 535     {
 536         *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
 537     }
 538     else if (NORMAL == mem)
 539     {
 540            *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
 541            switch(inner)
 542            {
 543             case NON_CACHEABLE:
 544             break;
 545             case WB_WA:
 546                 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
 547                 break;
 548             case WT:
 549                 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
 550                 break;
 551             case WB_NO_WA:
 552                 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
 553                 break;
 554         }
 555         switch(outer)
 556         {
 557             case NON_CACHEABLE:
 558              break;
 559             case WB_WA:
 560                 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
 561                 break;
 562             case WT:
 563                 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
 564                 break;
 565             case WB_NO_WA:
 566                 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
 567                 break;
 568         }
 569     }
 570
 571     return 0;
 572 }
 573
 574 /** \brief  Set 4k/64k page memory attributes
 575
 576     The function sets 4k/64k page memory attributes
 577
 578     \param [out]    descriptor_l2  L2 descriptor.
 579     \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
 580     \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
 581     \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
 582
 583     \return          0
 584  */
 585 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
 586 {
 587     *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
 588
 589     if (page == PAGE_64k)
 590     {
 591         //same as section
 592         __memory_section(descriptor_l2, mem, outer, inner);
 593     }
 594     else
 595     {
 596         if (STRONGLY_ORDERED == mem)
 597         {
 598             return 0;
 599         }
 600         else if (SHARED_DEVICE == mem)
 601         {
 602             *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
 603         }
 604         else if (NON_SHARED_DEVICE == mem)
 605         {
 606              *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
 607         }
 608         else if (NORMAL == mem)
 609         {
 610             *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
 611             switch(inner)
 612             {
 613                 case NON_CACHEABLE:
 614                 break;
 615                 case WB_WA:
 616                      *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
 617                      break;
 618                 case WT:
 619                     *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
 620                      break;
 621                 case WB_NO_WA:
 622                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
 623                     break;
 624             }
 625             switch(outer)
 626             {
 627                 case NON_CACHEABLE:
 628                 break;
 629                 case WB_WA:
 630                       *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
 631                     break;
 632                 case WT:
 633                      *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
 634                     break;
 635                 case WB_NO_WA:
 636                     *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
 637                     break;
 638             }
 639         }
 640     }
 641
 642     return 0;
 643 }
 644
 645 /** \brief  Create a L1 section descriptor
 646
 647     The function creates a section descriptor.
 648
 649     Assumptions:
 650     - 16MB super sections not suported
 651     - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
 652     - Functions always return 0
 653
 654     \param [out]       descriptor  L1 descriptor
 655     \param [out]      descriptor2  L2 descriptor
 656     \param [in]               reg  Section attributes
 657
 658     \return          0
 659  */
 660 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
 661 {
 662     *descriptor  = 0;
 663
 664    __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
 665    __xn_section(descriptor,reg.xn_t);
 666    __domain_section(descriptor, reg.domain);
 667    __p_section(descriptor, reg.e_t);
 668    __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
 669    __shared_section(descriptor,reg.sh_t);
 670    __global_section(descriptor,reg.g_t);
 671    __secure_section(descriptor,reg.sec_t);
 672    *descriptor &= SECTION_MASK;
 673    *descriptor |= SECTION_DESCRIPTOR;
 674
 675    return 0;
 676
 677 }
 678
 679
 680 /** \brief  Create a L1 and L2 4k/64k page descriptor
 681
 682     The function creates a 4k/64k page descriptor.
 683     Assumptions:
 684     - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
 685     - Functions always return 0
 686
 687     \param [out]       descriptor  L1 descriptor
 688     \param [out]      descriptor2  L2 descriptor
 689     \param [in]               reg  4k/64k page attributes
 690
 691     \return          0
 692  */
 693 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
 694 {
 695     *descriptor  = 0;
 696     *descriptor2 = 0;
 697
 698     switch (reg.rg_t)
 699     {
 700         case PAGE_4k:
 701             __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
 702             __xn_page(descriptor2, reg.xn_t, PAGE_4k);
 703             __domain_page(descriptor, reg.domain);
 704             __p_page(descriptor, reg.e_t);
 705             __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
 706             __shared_page(descriptor2,reg.sh_t);
 707             __global_page(descriptor2,reg.g_t);
 708             __secure_page(descriptor,reg.sec_t);
 709             *descriptor &= PAGE_L1_MASK;
 710             *descriptor |= PAGE_L1_DESCRIPTOR;
 711             *descriptor2 &= PAGE_L2_4K_MASK;
 712             *descriptor2 |= PAGE_L2_4K_DESC;
 713             break;
 714
 715         case PAGE_64k:
 716             __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
 717             __xn_page(descriptor2, reg.xn_t, PAGE_64k);
 718             __domain_page(descriptor, reg.domain);
 719             __p_page(descriptor, reg.e_t);
 720             __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
 721             __shared_page(descriptor2,reg.sh_t);
 722             __global_page(descriptor2,reg.g_t);
 723             __secure_page(descriptor,reg.sec_t);
 724             *descriptor &= PAGE_L1_MASK;
 725             *descriptor |= PAGE_L1_DESCRIPTOR;
 726             *descriptor2 &= PAGE_L2_64K_MASK;
 727             *descriptor2 |= PAGE_L2_64K_DESC;
 728             break;
 729
 730         case SECTION:
 731             //error
 732             break;
 733
 734     }
 735
 736    return 0;
 737
 738 }
 739
 740 /** \brief  Create a 1MB Section
 741
 742     \param [in]               ttb  Translation table base address
 743     \param [in]      base_address  Section base address
 744     \param [in]             count  Number of sections to create
 745     \param [in]     descriptor_l1  L1 descriptor (region attributes)
 746
 747  */
 748 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
 749 {
 750     uint32_t offset;
 751     uint32_t entry;
 752     uint32_t i;
 753
 754     offset = base_address >> 20;
 755     entry  = (base_address & 0xFFF00000) | descriptor_l1;
 756
 757     //4 bytes aligned
 758     ttb = ttb + offset;
 759
 760     for (i = 0; i < count; i++ )
 761     {
 762         //4 bytes aligned
 763        *ttb++ = entry;
 764        entry += OFFSET_1M;
 765     }
 766 }
 767
 768 /** \brief  Create a 4k page entry
 769
 770     \param [in]               ttb  L1 table base address
 771     \param [in]      base_address  4k base address
 772     \param [in]             count  Number of 4k pages to create
 773     \param [in]     descriptor_l1  L1 descriptor (region attributes)
 774     \param [in]            ttb_l2  L2 table base address
 775     \param [in]     descriptor_l2  L2 descriptor (region attributes)
 776
 777  */
 778 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
 779 {
 780
 781     uint32_t offset, offset2;
 782     uint32_t entry, entry2;
 783     uint32_t i;
 784
 785
 786     offset = base_address >> 20;
 787     entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
 788
 789     //4 bytes aligned
 790     ttb += offset;
 791     //create l1_entry
 792     *ttb = entry;
 793
 794     offset2 = (base_address & 0xff000) >> 12;
 795     ttb_l2 += offset2;
 796     entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
 797     for (i = 0; i < count; i++ )
 798     {
 799         //4 bytes aligned
 800        *ttb_l2++ = entry2;
 801        entry2 += OFFSET_4K;
 802     }
 803 }
 804
 805 /** \brief  Create a 64k page entry
 806
 807     \param [in]               ttb  L1 table base address
 808     \param [in]      base_address  64k base address
 809     \param [in]             count  Number of 64k pages to create
 810     \param [in]     descriptor_l1  L1 descriptor (region attributes)
 811     \param [in]            ttb_l2  L2 table base address
 812     \param [in]     descriptor_l2  L2 descriptor (region attributes)
 813
 814  */
 815 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
 816 {
 817     uint32_t offset, offset2;
 818     uint32_t entry, entry2;
 819     uint32_t i,j;
 820
 821
 822     offset = base_address >> 20;
 823     entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
 824
 825     //4 bytes aligned
 826     ttb += offset;
 827     //create l1_entry
 828     *ttb = entry;
 829
 830     offset2 = (base_address & 0xff000) >> 12;
 831     ttb_l2 += offset2;
 832     entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
 833     for (i = 0; i < count; i++ )
 834     {
 835         //create 16 entries
 836         for (j = 0; j < 16; j++)
 837             //4 bytes aligned
 838             *ttb_l2++ = entry2;
 839         entry2 += OFFSET_64K;
 840     }
 841 }
 842
 843 /*@} end of MMU_Functions */
 844 #endif
 845
 846 #ifdef __cplusplus
 847 }
 848 #endif